CN110729185B - Planarization process - Google Patents
Planarization process Download PDFInfo
- Publication number
- CN110729185B CN110729185B CN201810777912.8A CN201810777912A CN110729185B CN 110729185 B CN110729185 B CN 110729185B CN 201810777912 A CN201810777912 A CN 201810777912A CN 110729185 B CN110729185 B CN 110729185B
- Authority
- CN
- China
- Prior art keywords
- grinding
- metal
- polishing
- material layer
- metal gate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/30625—With simultaneous mechanical treatment, e.g. mechanico-chemical polishing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/32115—Planarisation
- H01L21/3212—Planarisation by chemical mechanical polishing [CMP]
Abstract
A planarization process method, comprising: providing a semiconductor substrate and a metal material layer, wherein the metal material layer is arranged above the semiconductor substrate, a metal grid and side walls are formed in the semiconductor substrate and the metal material layer, the side walls are formed on two side walls of the metal grid, a first part of the metal grid is formed in the semiconductor substrate, and a second part of the metal grid is formed in the metal material layer; grinding the metal material layer by adopting a first grinding process, or grinding part of the side wall and the second part of the metal grid to enable the second part of the rest metal grid to have a first height; and performing a second grinding process on the rest metal gate and the side wall to expose the semiconductor substrate, wherein the first grinding process and the second grinding process respectively have a grinding rate ratio on the metal material layer or the metal gate to the side wall. The two-step process of grinding the second portion of the metal gate enables good control of the height dimension of the final metal gate structure.
Description
Technical Field
The invention relates to the field of semiconductor manufacturing, in particular to a planarization process method.
Background
In the manufacturing process of the semiconductor device, after the groove is filled with the metal material, the groove needs to be ground to remove the reserved metal material, and the surface of the metal material layer is flattened, so that other materials can be conveniently deposited subsequently. For example, in the process of forming the metal gate, the top of the metal material is generally higher than the top of the metal gate, and the height of the metal gate is controlled by using a chemical mechanical planarization process.
However, in actual processes, the height of the final metal gate structure is easily lower than a set target height, which reduces the performance of the semiconductor device.
Therefore, a planarization process for controlling the height of the metal gate during the polishing process is needed.
Disclosure of Invention
The embodiment of the invention discloses a planarization process method, wherein a two-step grinding process is implemented to grind the second part of a metal grid, so that the height dimension of the final metal grid is effectively controlled.
A planarization process method, comprising: providing a semiconductor substrate and a metal material layer, wherein the metal material layer is arranged above the semiconductor substrate, a metal grid and a side wall are formed in the semiconductor substrate and the metal material layer, the side wall is formed on two side walls of the metal grid, a first part of the metal grid is formed in the semiconductor substrate, and a second part of the metal grid is formed in the metal material layer; grinding the metal material layer by adopting a first grinding process, or grinding part of the side wall and the second part of the metal grid to enable the second part of the rest metal grid to have a first height; and performing a second grinding process on the rest metal gate and the side wall to expose the semiconductor substrate, wherein the first grinding process and the second grinding process respectively have a grinding rate ratio to the metal material layer or the metal gate and the side wall, and the grinding rate ratio of the second grinding process is greater than that of the first grinding process.
According to one aspect of the invention, the grinding rate ratio is γ, and γ is 0.5. ltoreq. γ.ltoreq.4 under the first grinding process conditions.
According to an aspect of the invention, the second polishing process has a polishing rate for the metal material layer or the metal gate greater than a polishing rate for the sidewall.
According to one aspect of the invention, γ ≧ 10 under the conditions of the second grinding process.
According to one aspect of the invention, the material of the sidewall spacers comprises one or a combination of two of SiN, SiON.
According to one aspect of the invention, the first height ranges from
According to one aspect of the present invention, the first polishing process has a polishing rate in a range of
According to one aspect of the present invention, the second polishing process has a polishing rate in a range of
According to one aspect of the invention, the second portion of the metal gate has a height in the range of
According to one aspect of the invention, the material of the metal material layer and the material of the metal gate are both tungsten.
According to one aspect of the present invention, before the first grinding process, grinding a portion of the metal material layer by using a first pre-grinding process is further included.
According to one aspect of the invention, the first pre-grinding process has a grinding rate in the range of
According to one aspect of the invention, the distance between the top of the remaining metal material layer and the top of the sidewall is in the range of
According to an aspect of the present invention, after the first pre-grinding process, further comprising: and grinding the rest metal material layer by adopting a second pre-grinding process to expose the top of the side wall.
According to an aspect of the present invention, the polishing rate range and the polishing selection ratio of the second pre-polishing process are the same as those of the second polishing process.
Compared with the prior art, the technical scheme of the invention has the following advantages:
in the technical scheme of the invention, the metal material layer is ground by adopting a first grinding process, or part of the side wall and the second part of the metal grid are ground, so that the remaining second part of the metal grid has a first height, and a second grinding process is carried out on the remaining metal grid and the side wall. And the second part of the metal gate is ground by implementing the two processes, so that the metal gate structure can be protected from being damaged. Meanwhile, the grinding rate ratio of the second grinding process is larger than that of the first grinding process, and the grinding rate of the second grinding process to the metal material layer or the metal grid is larger than that to the side wall. When the second part of the rest metal grid electrode is ground, a larger grinding rate ratio is selected, the time and the position of the grinding stop can be well controlled, the first part of the metal grid electrode is prevented from being excessively ground, and the height dimension of the metal grid electrode is ensured to be consistent with the target design dimension.
Further, the second portion of the metal gate has a height in the range of
The second portion of the metal gate is reserved to facilitate subsequent processing while avoiding over-grinding the first portion of the metal gate.
Drawings
FIGS. 1-5 are schematic structural views of a planarization process according to one embodiment of the present invention;
fig. 6-8 are schematic structural views of a planarization process according to another embodiment of the present invention.
Detailed Description
As mentioned above, the conventional planarization process has the problem of over polishing the metal gate.
The research finds that the reasons causing the problems are as follows: when the second part of the metal gate is removed by grinding, the grinding speed of the metal gate is closer to the grinding speed of the side wall, the time and the position of the grinding termination are not easy to control, excessive grinding is easy to occur, the height of the metal gate is finally reduced, and the performance of a semiconductor device is reduced.
In order to solve the problem, the invention provides a planarization process method, a two-step grinding process is adopted to remove the second part of the metal gate, the grinding rate ratio of the second grinding process is greater than that of the first grinding process, the time and the position of the grinding stop are easy to control, and the metal gate is ensured to have the target height size.
Various exemplary embodiments of the present invention will now be described in detail with reference to the accompanying drawings. It should be understood that the relative arrangement of parts and steps, numerical expressions, and numerical values set forth in these embodiments should not be construed as limiting the scope of the present invention unless it is specifically stated otherwise.
Further, it should be understood that the dimensions of the various elements shown in the figures are not necessarily drawn to scale relative to actual scale, for example, the thickness or width of some layers may be exaggerated relative to other layers for ease of illustration.
The following description of the exemplary embodiment(s) is merely illustrative and is not intended to limit the invention or its application or uses in any way.
Techniques, methods, and apparatus known to those of ordinary skill in the relevant art may not be discussed in detail, but are intended to be part of the specification as applicable.
It should be noted that like reference numerals and letters refer to like items in the following figures, and thus, once an item is defined or illustrated in one figure, further discussion thereof will not be required in the subsequent description of the figures.
First embodiment
Referring to fig. 1, a metal material layer 120 is formed on a semiconductor substrate 100, and a metal gate 130 is formed in the semiconductor substrate 100 and the metal material layer 120.
The semiconductor substrate 100 serves as a process base for forming a semiconductor device. The material of the semiconductor substrate 100 is at least one of the following materials: polysilicon, silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-on-insulator-germanium (S-SiGeOI), silicon-on-insulator-germanium (SiGeOI), and the like. In the embodiment of the present invention, the material of the semiconductor substrate 100 is polysilicon, and the semiconductor substrate 100 further includes other structures, such as: the structures of metal plugs, metal connection layers, dielectric layers, etc., or other semiconductor devices including these structures, are not limited in this respect.
In the embodiment of the present invention, in order to form the metal gate 130 (as shown in the dashed line frame of fig. 1) to sufficiently fill the groove, after the metal gate 130 is formed, the metal material is formed to form the metal material layer 120 covering the semiconductor substrate 100 and the metal gate 130.
It should be noted that, in other embodiments of the present invention, the top of the metal material layer 120 may be flush with the top of the sidewall 110 and the top of the metal gate 130, which is not limited herein.
Obviously, the metal material layer 120 and the metal gate 130 are made of the same material, and the same material is selected to facilitate the control of the forming process. Specifically, in the embodiment of the present invention, the material of the metal material layer 120 and the material of the metal gate 130 are both tungsten (W).
It should be noted that, in other embodiments of the present invention, the materials of the metal material layer 120 and the metal gate 130 may also be different, and the materials of the two may also include other materials, such as aluminum (Al), and the like, which is not limited herein.
The metal gate 130 plays a controlling role. In the embodiment of the present invention, the metal gate 130 includes a first portion i and a second portion ii. A first portion i of the metal gate 130 is formed in the semiconductor substrate 100 and a second portion ii of the metal gate 130 is formed in the metal material layer 120.
In actual manufacturing processes, the first portion i of the metal gate 130 is a metal gate structure in the final semiconductor device, and the second portion ii of the metal gate 130 is a margin designed to avoid the loss of the final metal gate structure in subsequent processes, so the second portion ii of the metal gate 130 needs to be removed in subsequent processes.
In embodiments of the present invention, the "margin" of a structure means that the top of the structure is higher than the top of the semiconductor substrate 100. Hereinafter, the expression "rich portion" is the same as that herein.
The second portion II of the metal gate 130 has a height in the range of
(Here, the height is in the range of not less than
Is less than or equal to
I.e., ranges include the end point values and subsequent ranges are intended to be synonymous herein). Specifically, in the embodiment of the present invention, the height of the second portion ii of the metal gate 130 is as follows
In another embodiment of the present invention, the second portion II of the metal gate 130 has a height of
In another embodiment of the present invention, the second portion II of the metal gate 130 has a height of
In yet another embodiment of the present invention, the second portion II of the metal gate 130 has a height of
In the embodiment of the invention, the sidewalls 110 are further formed on two sidewalls of the metal gate 130. In general, the sidewall spacers 110 serve as isolation insulators. In order to finally form a metal gate structure with complete structure, the sidewall 110 has a margin, and this margin needs to be removed subsequently together with the second portion ii of the metal gate 130.
It should be noted that the height of the margin portion of the sidewall 110 is not particularly limited herein, as long as the top of the sidewall 110 is higher than the top of the semiconductor substrate 100.
The material of the sidewall spacers 110 includes SiN, SiON, or a combination of both. Specifically, in the embodiment of the present invention, the material of the sidewall spacer 110 is SiN.
In an embodiment of the present invention, the sidewall 110 also functions to stop grinding, which will be described in detail below.
Referring to fig. 2, a portion of the metal material layer 120 is polished by a first pre-polishing process.
Polishing the portion of the metal material layer 120 is prepared to remove the second portion ii of the metal gate 130.
The first pre-grinding process has a grinding rate range of
Faster polishing rates can save process time. Specifically, in the embodiment of the present invention, the polishing rate of the first pre-polishing process is
In another embodiment of the present invention, the first pre-grinding process has a grinding rate of
In another embodiment of the present invention, the first pre-grinding process has a grinding rate of
In the embodiment of the present invention, in order to prevent the first pre-polishing process with a faster polishing rate from damaging the structure of the metal gate 130 or the sidewall 110, the remaining portion of the metal material layer 120 is required at the end of the first pre-polishing process. The distance between the top of the remaining metal material layer 120 and the top of the sidewall 110 is h1，
In the embodiment of the present invention, it is,
in a further embodiment of the present invention,
in a still further embodiment of the present invention,
in a further embodiment of the present invention,
referring to fig. 3, the remaining metal material layer 120 is polished by a second pre-polishing process to expose the top of the sidewall 110.
The top of the sidewall spacers 110 are exposed for subsequent removal of the excess sidewall spacers 110 and the second portion ii of the metal gate 130.
The second pre-grinding process has a grinding rate range of
Specifically, in the embodiment of the present invention, the second pre-grinding process has a grinding rate of
In another embodiment of the present invention, the second pre-grinding process has a grinding rate of
In another embodiment of the present invention, the second pre-grinding process has a grinding rate of
In yet another embodiment of the present invention, the second pre-grinding process has a grinding rate of
Obviously, the polishing rate of the second pre-polishing process is smaller than that of the first pre-polishing process. The grinding rate is reduced, the grinding process is relatively smooth and fine, and the metal gate 130 or the side wall 110 structure can be effectively protected when the side wall 110 is exposed.
When the top of the sidewall 110 is exposed according to the embodiment of the present invention, it is necessary to expose the topThe second pre-grinding process is stopped. Therefore, the second pre-grinding process has a certain grinding rate ratio γ to the metal material layer 120 and to the side wall 110. Here, if the second pre-grinding process grinds the metal material layer 120 at a rate v1The polishing rate to the sidewall 110 is v2Then γ ═ v1:v2Hereinafter, the polishing rate ratio γ is the same as that used herein. In an embodiment of the present invention, γ of the second pre-grinding process is ≧ 10. Specifically, in the present embodiment, γ of the second pre-grinding process is 10. In another embodiment of the present invention, γ of the second pre-grinding process is 35. Obviously, the polishing rate of the metal material layer 120 by the second pre-polishing process is greater than that of the sidewall 110.
When the second pre-polishing process polishes the exposed sidewall 110, the polishing rate of the second pre-polishing process is decreased by the larger polishing rate ratio γ, and the polishing is stopped. Therefore, the sidewall 110 can stop the polishing as mentioned above.
Referring to fig. 4, a second portion of the metal gate 130 is polished by a first polishing process.
A first polishing process is performed to remove a second portion of the metal gate 130. The first polishing process has a polishing rate in the range of
Specifically, in the embodiment of the present invention, the polishing rate of the first polishing process is
In another embodiment of the present invention, the first polishing process has a polishing rate of
Meanwhile, gamma is more than or equal to 0.5 and less than or equal to 4 under the condition of the first grinding process. Specifically, in the present embodiment, γ is 0.5. In another embodiment of the present invention, γ ═ 4.
Obviously, the polishing rate of the first polishing process and the polishing rate of the second pre-polishing process are in the same range, and the polishing rates may be equal, but γ of the two processes is different. In different grinding processes, the purpose of having different grinding rate ratios under the same grinding rate can be achieved by adjusting the types of the grinding agents or adding grinding inhibitors and the like.
As mentioned above, the second pre-grinding process has a larger γ, which can stop the grinding on the sidewall 110. The gamma of the first grinding process is smaller, and the grinding removal rates of the side wall 110 and the metal gate 130 are close to each other, so that the side wall 110 and the metal gate 130 can be simultaneously ground and removed, and the purpose of removing the second part of the metal gate 130 is further achieved.
In one planarization process, a first polishing process is used to remove a second portion of the metal gate 130. However, since the polishing rates of the sidewall 110 and the metal gate 130 are close to each other, it is difficult to control the timing and position of the stop of polishing, and over-polishing is easy to remove a first portion i (the final metal gate structure) of a part of the metal gate 130, which results in a reduction in the height of the metal gate structure in the final semiconductor device, and thus the desired control target is not achieved, and the performance of the semiconductor device is reduced.
Therefore, in the embodiment of the present invention, after the first polishing process is stopped, a second portion of the metal gate 130 needs to remain. The remaining second portion of the metal gate 130 has a first height h2，
In particular, in the embodiments of the present invention,
in a further embodiment of the present invention,
referring to fig. 5, a second grinding process is performed to grind the remaining second portions of the sidewall spacers 110 and the metal gate 130.
The second grinding process finally removes the second portion of the metal gate 130. The second polishing process has a polishing rate in the range of
Specifically, in the embodiment of the present invention, the second polishing process has a polishing rate of
In another embodiment of the present invention, the second polishing process has a polishing rate of
In embodiments of the present invention, γ ≧ 10 for the second milling process. Specifically, in the embodiment of the present invention, γ of the second polishing process is 10. That is, the polishing rate of the metal material layer 120 or the metal gate 130 by the second polishing process is greater than the polishing rate of the sidewall 110. The second grinding process has larger gamma, the position and the time of stopping grinding are easy to control, and the first part I of the partial metal grid 130 is prevented from being ground and lost due to over grinding, so that the reduction of the structure height of the metal grid in the final device is avoided, and the performance of the semiconductor device is improved.
Obviously, the polishing rate range and the polishing selection ratio of the second pre-polishing process are the same as those of the second polishing process. In other embodiments of the present invention, the specific grinding rates and specific grinding selection ratios of the second pre-grinding process and the second grinding process may also be different, but it is necessary to ensure that the two processes have a larger grinding selection ratio.
In summary, the embodiment of the present invention discloses a planarization process method, wherein two process steps, namely a first polishing process and a second polishing process, are adopted when removing the second portion of the metal gate, and the polishing selection ratio of the second polishing process is smaller than that of the first polishing process, so that the first portion of the metal gate is not excessively polished, the height of the final metal gate structure is ensured, the performance of the semiconductor device is improved, and the polishing efficiency is also improved.
Second embodiment
The second embodiment differs from the first embodiment in that: and directly grinding the metal material layer, the side wall and part of the second part of the metal grid by adopting a first grinding process, so that the second part of the remaining metal grid has a first height. The subsequent process steps are identical to those of the first embodiment.
Referring to fig. 6, a semiconductor substrate 200, a sidewall spacer 210, a metal material layer 220 and a metal gate 230 are provided.
The structure, function and positional relationship of the semiconductor substrate 200, the sidewall spacers 210, the metal material layer 220 and the metal gate 230 are the same as those of the first embodiment, and are not described herein again.
Referring to fig. 7, the metal material layer 220, a portion of the second portion of the metal gate 230, and the sidewall spacers 210 are polished by a first polishing process.
The first grinding is performed to remove the second portion of the metal gate 230. The range of the polishing rate and the range of the polishing rate ratio of the first polishing process are the same as those of the first embodiment. Specifically, in the embodiment of the present invention, the polishing rate of the first polishing process is
The polishing rate ratio γ of the first polishing process was 1.5. In another embodiment of the present invention, the first polishing process has a polishing rate of
γ＝2.5。
After the first polishing process is stopped, a second portion of the metal gate 230 needs to remain. The first height h of the second part of the metal gate 230 is remained2In accordance with the first embodiment. In particular, in the embodiments of the present invention,
in a further embodiment of the present invention,
referring to fig. 8, a second grinding process is performed to grind the remaining second portions of the sidewall spacers 210 and the metal gates 230.
The effect of the second polishing process, the range of polishing rates, and the range of polishing rate ratios γ are all consistent with the first embodiment. Specifically, in the embodiment of the present invention, the polishing rate of the second polishing process is
γ of the second grinding process is 25. In another embodiment of the present invention, the second polishing process has a polishing rate of
γ of the second grinding process is 40.
Similarly, please refer to the first embodiment for the purpose of selecting the first polishing process and the second polishing process, which will not be described herein again.
In summary, when the second portion of the metal gate is removed, two process steps, namely the first grinding process and the second grinding process, are adopted, and the grinding selection ratio of the second grinding process is smaller than that of the first grinding process, so that the first portion of the metal gate is not excessively ground, the height of the final metal gate structure is ensured, the performance of the semiconductor device is improved, and meanwhile, the grinding efficiency is also improved.
Thus far, the present invention has been described in detail. Some details well known in the art have not been described in order to avoid obscuring the concepts of the present invention. It will be fully apparent to those skilled in the art from the foregoing description how to practice the presently disclosed embodiments.
Although some specific embodiments of the present invention have been described in detail by way of example, it should be understood by those skilled in the art that the above examples are for illustration only and are not intended to limit the scope of the invention. It will be appreciated by those skilled in the art that modifications may be made to the above embodiments without departing from the scope and spirit of the invention. The scope of the invention is defined by the appended claims.
Claims (15)
1. A planarization process, comprising:
providing a semiconductor substrate and a metal material layer, wherein the metal material layer is arranged above the semiconductor substrate, a metal grid and a side wall are formed in the semiconductor substrate and the metal material layer, the side wall is formed on two side walls of the metal grid, a first part of the metal grid is formed in the semiconductor substrate, and a second part of the metal grid is formed in the metal material layer;
grinding part of the side wall and the second part of the metal grid by adopting a first grinding process to enable the rest of the second part of the metal grid to have a first height; and
and performing a second grinding process on the rest second part of the metal gate and the side wall to expose the semiconductor substrate, wherein the first grinding process and the second grinding process respectively have a grinding rate ratio to the metal material layer or the metal gate to the side wall, and the grinding rate ratio of the second grinding process is greater than that of the first grinding process.
2. The planarization process of claim 1, wherein the polishing rate ratio is γ, and 0.5 ≦ γ ≦ 4 under the first polishing process conditions.
3. The planarization process method of claim 1, wherein the second polishing process has a polishing rate for the metal material layer or the metal gate greater than a polishing rate for the sidewall.
4. The planarization process method of claim 3, wherein γ ≧ 10 under the conditions of the second grinding process.
5. The planarization process of claim 1, wherein the material of the sidewall spacers comprises one or a combination of SiN and SiON.
6. The planarization process of claim 1, wherein the first height ranges from
7. The planarization process of claim 1, wherein the first polishing process has a polishing rate in a range of
8. The planarization process of claim 1, wherein the second polishing process has a polishing rate in a range of
9. The planarization process of claim 1, wherein the second portion of the metal gate has a height in a range of
10. The planarization process of claim 1, wherein the metal material layer and the metal gate are both tungsten.
11. The planarization process of claim 1, further comprising grinding a portion of the metallic material layer using a first pre-grinding process prior to performing the first grinding process.
12. The planarization process method of claim 11, wherein the first pre-polishing process has a polishing rate range
13. The planarization process of claim 11, wherein the distance between the top of the remaining metal material layer and the top of the sidewall is in the range of
14. The planarization process of claim 11, after the first pre-grinding process, further comprising: and grinding the rest metal material layer by adopting a second pre-grinding process to expose the top of the side wall.
15. The planarization process of claim 14, wherein the second pre-polishing process has the same polishing rate range and polishing selectivity as the second polishing process.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810777912.8A CN110729185B (en) | 2018-07-16 | 2018-07-16 | Planarization process |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810777912.8A CN110729185B (en) | 2018-07-16 | 2018-07-16 | Planarization process |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN110729185A CN110729185A (en) | 2020-01-24 |
| CN110729185B true CN110729185B (en) | 2022-07-12 |
Family
ID=69217317
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201810777912.8A Active CN110729185B (en) | 2018-07-16 | 2018-07-16 | Planarization process |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN110729185B (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102931094A (en) * | 2011-08-09 | 2013-02-13 | 万国半导体股份有限公司 | Wafer level packaging structure with large contact area and preparation method thereof |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1755901A (en) * | 2004-09-29 | 2006-04-05 | 联华电子股份有限公司 | Chemical mechanical polishing technique |
| JP4440080B2 (en) * | 2004-11-12 | 2010-03-24 | 株式会社東芝 | Semiconductor device and manufacturing method thereof |
| US7816732B2 (en) * | 2008-06-23 | 2010-10-19 | Force Mos Technology Co., Ltd. | Integrated trench MOSFET and Schottky rectifier with trench contact structure |
| CN102569083B (en) * | 2010-12-23 | 2014-12-24 | 中芯国际集成电路制造(上海)有限公司 | Method for forming metal-oxide semiconductor with high potassium (K) metal gate |
| CN103165429B (en) * | 2011-12-15 | 2015-11-25 | 中芯国际集成电路制造(上海)有限公司 | Method for forming metallic grid |
-
2018
- 2018-07-16 CN CN201810777912.8A patent/CN110729185B/en active Active
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102931094A (en) * | 2011-08-09 | 2013-02-13 | 万国半导体股份有限公司 | Wafer level packaging structure with large contact area and preparation method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| CN110729185A (en) | 2020-01-24 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US7452817B2 (en) | CMP method providing reduced thickness variations | |
| KR102463863B1 (en) | Polishing compositions and methods of manufacturing semiconductor devices using the same | |
| US9515078B2 (en) | Semiconductor structure and method for forming the same | |
| US20150200111A1 (en) | Planarization scheme for finfet gate height uniformity control | |
| US9633855B2 (en) | Planarization process | |
| US9484263B1 (en) | Method of removing a hard mask on a gate | |
| US10679902B2 (en) | Semiconductor device and fabrication method thereof | |
| US20070072437A1 (en) | Method for forming narrow structures in a semiconductor device | |
| US20160104623A1 (en) | Methods for forming semiconductor device | |
| CN104576380B (en) | A kind of FINFET manufacture methods | |
| US9490175B2 (en) | Chemical mechanical polishing method for first interlayer dielectric layer | |
| US9425091B2 (en) | Method for forming semiconductor structure | |
| EP3240021B1 (en) | A method for fabricating a semiconductor structure | |
| US9543212B2 (en) | Preventing over-polishing of poly gate in metal-gate CMP | |
| US9299584B2 (en) | Methods of forming integrated circuits with a planarized permanent layer and methods for forming FinFET devices with a planarized permanent layer | |
| CN110729185B (en) | Planarization process | |
| CN104078346A (en) | Planarization method for semi-conductor device | |
| US9646840B2 (en) | Method for CMP of high-K metal gate structures | |
| US20150214114A1 (en) | Manufacturing method of semiconductor structure | |
| CN110957215B (en) | Planarization process | |
| CN110444470A (en) | A kind of method of different line width transistor gate height in improvement semiconductor devices | |
| US10147636B2 (en) | Methods for fabricating trench isolation structure | |
| US20170053911A1 (en) | Semiconductor device and semiconductor device manufacturing method | |
| CN111696864B (en) | Semiconductor device and method of forming the same | |
| CN110729183B (en) | Metal gate forming method and semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |