CN110727463A - Zero-level instruction circular buffer prefetching method and device based on dynamic credit - Google Patents
Zero-level instruction circular buffer prefetching method and device based on dynamic credit Download PDFInfo
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Abstract
The invention discloses a zero-level instruction circular buffer prefetching method based on dynamic credit. Judging the circulation direction of a circulation body when detecting that the circulation body exists in an instruction stream; determining the circulation outlet instruction information of the circulation body according to the circulation direction of the circulation body, and sending pre-fetching credit information to a first-level instruction cache control component according to the circulation outlet instruction information; and when detecting that the output instruction reaches the tail part of the loop body, judging the advancing direction of the loop body, and if the advancing direction of the loop body is the continuous loop direction, sending a prefetch starting signal to a prefetch credit management part of the first-level instruction cache control part. The invention also discloses a zero-level instruction circular buffer prefetching device based on the dynamic credit. By prefetching the instructions in the exit direction of the cycle, the instructions in the exit direction can be immediately provided from the zero-level instruction cache when the cycle in the zero-level instruction cycle cache exits, so that performance bubbles caused by miss of the zero-level instruction cache are avoided.
Description
Technical Field
The invention relates to the field of computer architecture and chip microstructure, in particular to a zero-level instruction circular buffer prefetching method and device based on dynamic credit.
Background
The processor pipeline needs to complete the basic flow of "fetch instruction- > parse instruction- > execute instruction". The first-level instruction cache is a key component in a processor pipeline, and by storing the instruction required by the latest execution in the first-level instruction cache, the pipeline can be prevented from frequently accessing the main memory, and the pipeline performance is further improved (the access time of the main memory is tens of times or hundreds of times of that of the instruction cache). In order to further play a role in the idea of instruction caching, the industry proposes the design of a zero-level instruction cache, and the core idea of the design is to arrange a zero-level instruction cache at a position closer to a component for executing instructions by a processor (for example, between two stages of "parse instruction" and "execute instruction"), store instructions which may need to be executed in the near-term in the zero-level instruction cache, and avoid accessing the first-level instruction cache.
Since the zero level instruction cache is deeply coupled to the pipeline, instruction miss (instruction miss: i.e., the required instruction is not present in the cache) occurs therein, which tends to cause instruction stall in the pipeline, thereby affecting pipeline performance.
In a specific implementation of the zero level instruction cache, the zero level instruction loop cache, the instruction cache identifies a loop body structure existing in the program, and when a loop body is found, execution of subsequent loop body code is allowed to be fetched from the instruction cache. Because the loop body is executed in a plurality of cycles, the cycle is finally ended, at this time, miss occurs in the cycle cache, and instruction fetch flow of the pipeline is interrupted, which causes performance loss.
Disclosure of Invention
The invention aims to provide a zero-level instruction circular buffer prefetching method and device based on dynamic credit, which can avoid the negative influence of the zero-level instruction buffer on the performance of a pipeline.
According to a first aspect of the present invention, there is provided a dynamic credit based zero level instruction loop buffer prefetch method, comprising:
when detecting that a loop body exists in the instruction stream, judging the loop direction of the loop body;
determining the circulation outlet instruction information of the circulation body according to the circulation direction of the circulation body, and sending pre-fetching credit information to a first-level instruction cache control component according to the circulation outlet instruction information;
when detecting that the output instruction reaches the tail of the loop body, judging the advancing direction of the loop body, and if the advancing direction of the loop body is the continuous loop direction, sending a prefetching starting signal to a prefetching credit management component of a first-level instruction cache control component; and if the advancing direction of the loop body is the loop exit direction, sending a recovery instruction fetching signal to a prefetch credit management part of the first-level instruction cache control part.
Further, the step of sending prefetch credit information to the first-level instruction cache control unit according to the loop exit instruction information may further include:
acquiring the total loadable instruction number and the size of a loop body, and calculating the number of prefetch instructions;
when the number of the prefetch instruction is smaller than the maximum credit value supported by the loop exit instruction information, taking the number of the prefetch instruction as the prefetch credit value in the prefetch credit information;
and when the number of the prefetch instructions is larger than the maximum credit value supported by the loop exit instruction information, taking the maximum credit value as the prefetch credit value in the prefetch credit information.
Further, after "when the number of prefetch instructions is less than the maximum credit value supported by the loop exit instruction information, the method takes the number of prefetch instructions as the prefetch credit value in the prefetch credit information", the method further includes:
when the prefetch credit value is detected to be zero, a suspend instruction fetch signal is sent to a prefetch credit management unit of the level one instruction cache control unit.
Further, when "when the loop body is detected to exist in the instruction stream, the loop direction of the loop body is determined", the method further includes:
when the loop body is detected, a suspend instruction fetch signal is sent to a prefetch credit management unit of the first level instruction cache control unit.
According to a second aspect of the present invention, there is provided a dynamic credit based zero level instruction loop buffer prefetch apparatus comprising:
a detection module: when detecting that a loop body exists in the instruction stream, judging the loop direction of the loop body;
a processing module: determining the circulation outlet instruction information of the circulation body according to the circulation direction of the circulation body, and sending pre-fetching credit information to a first-level instruction cache control component according to the circulation outlet instruction information;
a sending module: when detecting that the output instruction reaches the tail of the loop body, judging the advancing direction of the loop body, and if the advancing direction of the loop body is the continuous loop direction, sending a prefetching starting signal to a prefetching credit management component of a first-level instruction cache control component; and if the advancing direction of the loop body is the loop exit direction, sending a recovery instruction fetching signal to a prefetch credit management part of the first-level instruction cache control part.
Further, the step of sending prefetch credit information to the first-level instruction cache control unit according to the loop exit instruction information may further include:
a processing module: acquiring the total loadable instruction number and the size of a loop body, and calculating the number of prefetch instructions;
when the number of the prefetch instruction is smaller than the maximum credit value supported by the loop exit instruction information, taking the number of the prefetch instruction as the prefetch credit value in the prefetch credit information;
and when the number of the prefetch instructions is larger than the maximum credit value supported by the loop exit instruction information, taking the maximum credit value as the prefetch credit value in the prefetch credit information.
Further, after "when the number of prefetch instructions is less than the maximum credit value supported by the loop exit instruction information, the method takes the number of prefetch instructions as the prefetch credit value in the prefetch credit information", the method further includes:
a sending module: when the prefetch credit value is detected to be zero, a suspend instruction fetch signal is sent to a prefetch credit management unit of the level one instruction cache control unit.
Further, when "when the loop body is detected to exist in the instruction stream, the loop direction of the loop body is determined", the method further includes:
a sending module: when the loop body is detected, a suspend instruction fetch signal is sent to a prefetch credit management unit of the first level instruction cache control unit.
The invention has the beneficial effects that: 1. by prefetching the execution to be executed in a plurality of clock cycles after the loop exits, pipeline instruction cutoff during the loop exits is avoided, and further negative influence of zero-level instruction cache on pipeline performance is avoided. 2. By prefetching the instructions in the exit direction of the cycle, the instructions in the exit direction can be immediately provided from the zero-order instruction cache when the cycle in the zero-order instruction cycle cache exits, and performance bubbles caused by miss of the zero-order instruction cache are avoided.
Drawings
FIG. 1 is a flow diagram of a method for dynamic credit based zero level instruction loop buffer prefetching, according to an embodiment of the present invention;
FIG. 2 is a block diagram of a dynamic credit based zero level instruction loop buffer prefetch apparatus, according to an embodiment of the present invention.
FIG. 3 is a diagram of a zero level instruction cache and processor pipeline of the present invention, according to one embodiment of the present invention;
FIG. 4 is an instruction flow diagram illustrating the occurrence of a loop according to one embodiment of the invention;
FIG. 5 is a diagram illustrating operation of a prefetch credit state machine according to one embodiment of the invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. All other embodiments, which can be obtained by a person skilled in the art without any inventive step based on the embodiments of the present invention, are within the scope of the present invention.
Fig. 1, 3, 4, and 5 show the flow of a zero-level instruction loop buffer prefetch method based on dynamic credit according to an embodiment of the present invention, including:
and S11, judging the circulation direction of the circulation body when detecting that the circulation body exists in the command stream.
The execution subject of the method may be the zero level loop cache control logic.
It should be noted that, in the prior art, under the control of the zero-level loop cache control logic, a loop body instruction stream of several rounds is output to the execution unit, but the loop body in the program is not always circulated. When the zero-level loop cache control logic judges that the current loop adopts the loop exit direction, because the zero-level instruction loop cache only contains instructions inside the loop body, the next clock cycle cannot output instructions (instructions in the loop exit direction) from the zero-level instruction loop cache. In this case, it is necessary to notify the "first-level instruction cache control unit" to initiate instruction fetching, and since there are several stages of pipeline stations from the "zero-level instruction cache" to the "first-level instruction cache", instructions fetched from the first-level instruction cache need to pass through several clock cycles to reach the zero-level instruction cache, and are finally sent to the execution unit. During these clock cycles, the execution unit has no instructions available for execution, thereby creating a performance penalty for the pipeline.
In this embodiment, the zero-level loop cache control logic performs a first determination to determine the loop direction of the loop body when the loop body in the instruction stream is identified.
And S12, determining the loop exit instruction information of the loop body according to the loop direction of the loop body, and sending the prefetch credit information to the first-level instruction cache control component according to the loop exit instruction information.
In this embodiment, when the zero-level loop cache control logic determines that the loop takes the "direction to continue the loop", it notifies the "first-level instruction cache control unit" to perform prefetching, where the target of prefetching is an instruction in the "loop exit direction", and by storing these instructions in the zero-level instruction cache in advance (on the premise that the remaining capacity of the zero-level instruction cache allows storing the prefetched instruction), the performance loss caused by the occurrence of the "miss of the zero-level instruction cache" can be avoided. Wherein the number of prefetched instructions is controlled by prefetch credits.
S13, when detecting that the output instruction reaches the tail of the loop body, judging the advancing direction of the loop body, if the advancing direction of the loop body is the continuous loop direction, sending a prefetch starting signal to the prefetch credit management component of the first-level instruction cache control component; and if the advancing direction of the loop body is the loop exit direction, sending a recovery instruction fetching signal to a prefetch credit management part of the first-level instruction cache control part.
In the present embodiment, the state machine defaults to the state of S0 (normal fetch), where all fetches are from the level one instruction cache. The zero-level loop cache control logic outputs an instruction to reach the tail of the current loop body for the first time, and when the loop body is judged to adopt the 'continuous loop direction', a 'prefetch starting' signal is sent out to inform the prefetch credit management component, the state machine is transited from the S1 state to the S2 state, and meanwhile, the prefetch credit is transmitted to the prefetch credit management component. The zero-level loop cache control logic outputs an instruction to reach the tail of the current loop body for the first time, and when the loop body is judged to adopt the 'continuous loop direction', a 'prefetch starting' signal is sent out to inform the prefetch credit management component, the state machine is transited from the S1 state to the S2 state, and meanwhile, the prefetch credit is transmitted to the prefetch credit management component.
As a preferred embodiment, the step S12 of sending prefetch credit information to the first-level instruction cache control unit according to the loop-out instruction information specifically includes:
acquiring the total loadable instruction number and the size of a loop body, and calculating the number of prefetch instructions;
when the number of the prefetch instruction is smaller than the maximum credit value supported by the loop exit instruction information, taking the number of the prefetch instruction as the prefetch credit value in the prefetch credit information;
and when the number of the prefetch instructions is larger than the maximum credit value supported by the loop exit instruction information, taking the maximum credit value as the prefetch credit value in the prefetch credit information.
In the embodiment of the present specification, the calculation method of the prefetch credit is as follows: the currently identified loop body size (denoted L) is first calculated, while the number of instruction pieces that can be prefetched (C-L) is calculated from the total number of instructions that can be loaded in the zero level instruction cache (denoted C). Prefetching is performed using a credit mechanism, each credit indicating that 1 instruction can be prefetched. Prefetch credits = C-L when the result of C-L is less than the maximum credit value supported by the prefetch mechanism. Prefetch credits = maximum credit value when the result of C-L is equal to or greater than the maximum credit value supported by the prefetch mechanism.
As a preferred embodiment, after "when the number of prefetch instructions is less than the maximum credit value supported by the loop exit instruction information, taking the number of prefetch instructions as the prefetch credit value in the prefetch credit information" further includes:
when the prefetch credit value is detected to be zero, a suspend instruction fetch signal is sent to a prefetch credit management unit of the level one instruction cache control unit.
In this embodiment, in the S2 state, the prefetch credit management unit controls the primary instruction cache control unit to initiate fetching of the primary instruction cache several times according to the obtained credit value, and to continue to suspend fetching when the credit is exhausted.
As a preferred embodiment, when performing step S11, the method further includes:
when the loop body is detected, a suspend instruction fetch signal is sent to a prefetch credit management unit of the first level instruction cache control unit.
In this illustrative embodiment, the zero level loop cache control logic, upon identifying the loop body, will issue a "halt fetch" signal to the prefetch credit management unit that the state machine transitions from the S0 state to the S1 state. In the state of S1, the first-level instruction cache control unit does not operate and does not perform access to the first-level instruction cache, and all the fetch instructions are from the zero-level instruction cache.
FIG. 2 is a diagram illustrating the structure of a dynamic credit-based zero-level instruction loop buffer prefetch apparatus according to an embodiment of the present invention, including:
the detection module 21: when detecting that a loop body exists in the instruction stream, judging the loop direction of the loop body;
the processing module 22: determining the circulation outlet instruction information of the circulation body according to the circulation direction of the circulation body, and sending pre-fetching credit information to a first-level instruction cache control component according to the circulation outlet instruction information;
the sending module 23: when detecting that the output instruction reaches the tail of the loop body, judging the advancing direction of the loop body, and if the advancing direction of the loop body is the continuous loop direction, sending a prefetching starting signal to a prefetching credit management component of a first-level instruction cache control component; and if the advancing direction of the loop body is the loop exit direction, sending a recovery instruction fetching signal to a prefetch credit management part of the first-level instruction cache control part.
As a preferred embodiment, the step of sending prefetch credit information to the first-level instruction cache control unit according to the loop exit instruction information specifically further includes:
the processing module 22: acquiring the total loadable instruction number and the size of a loop body, and calculating the number of prefetch instructions;
when the number of the prefetch instruction is smaller than the maximum credit value supported by the loop exit instruction information, taking the number of the prefetch instruction as the prefetch credit value in the prefetch credit information;
and when the number of the prefetch instructions is larger than the maximum credit value supported by the loop exit instruction information, taking the maximum credit value as the prefetch credit value in the prefetch credit information.
As a preferred embodiment, after "when the number of prefetch instructions is less than the maximum credit value supported by the loop exit instruction information, taking the number of prefetch instructions as the prefetch credit value in the prefetch credit information" further includes:
the sending module 23: when the prefetch credit value is detected to be zero, a suspend instruction fetch signal is sent to a prefetch credit management unit of the level one instruction cache control unit.
As a preferred embodiment, when "when the loop body is detected to be present in the instruction stream, the loop direction of the loop body is determined", the method further includes:
the sending module 23: when the loop body is detected, a suspend instruction fetch signal is sent to a prefetch credit management unit of the first level instruction cache control unit.
Furthermore, those skilled in the art will appreciate that while some embodiments herein include some features included in other embodiments, rather than other features, combinations of features of different embodiments are meant to be within the scope of the invention and form different embodiments. For example, in the claims, any of the claimed embodiments may be used in any combination.
Those of ordinary skill in the art will understand that: the above embodiments are only used for illustrating the technical solutions of the present invention, and not for limiting the same, although the present invention is described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: it is possible to modify the solutions described in the above embodiments or to substitute some or all of the technical features of the embodiments, without departing from the scope of the present invention as defined in the claims.
Claims (8)
1. A zero level instruction loop buffer prefetch method based on dynamic credit, comprising:
s11, judging the circulation direction of the circulation body when detecting that the circulation body exists in the instruction stream;
s12, determining the circulation outlet instruction information of the circulation body according to the circulation direction of the circulation body, and sending pre-fetching credit information to a first-level instruction cache control component according to the circulation outlet instruction information;
s13, when detecting that the output instruction reaches the tail of the loop body, judging the advancing direction of the loop body, and if the advancing direction of the loop body is the continuous loop direction, sending a prefetch starting signal to a prefetch credit management component of the first-level instruction cache control component; and if the advancing direction of the loop body is the loop exit direction, sending a recovery instruction fetching signal to a prefetch credit management component of the first-level instruction cache control component.
2. The method according to claim 1, wherein the step S12 of sending prefetch credit information to the first-level instruction cache control unit according to the loop exit instruction information further comprises:
acquiring the total loadable instruction number and the size of a loop body, and calculating the number of prefetch instructions;
when the number of the prefetch instruction is smaller than the maximum credit value supported by the loop exit instruction information, taking the number of the prefetch instruction as the prefetch credit value in the prefetch credit information;
and when the number of the prefetch instruction is larger than the maximum credit value supported by the loop exit instruction information, taking the maximum credit value as the prefetch credit value in the prefetch credit information.
3. The method according to claim 2, wherein the step of using the number of prefetched instructions as the prefetch credit value in the prefetch credit information when the number of prefetched instructions is less than the maximum credit value supported by the loop exit instruction information further comprises the steps of:
when detecting that the prefetch credit value is zero, sending a pause instruction fetching signal to a prefetch credit management unit of the level one instruction cache control unit.
4. The zero-level instruction loop buffer prefetch method based on dynamic credit as claimed in claim 1, wherein when performing step S11, further comprising:
when the loop body is detected, sending a pause instruction fetching signal to a prefetch credit management unit of the first-level instruction cache control unit.
5. A dynamic credit based zero level instruction loop buffer prefetch apparatus comprising:
a detection module: when detecting that a loop body exists in the instruction stream, judging the loop direction of the loop body;
a processing module: determining the circulation outlet instruction information of the circulation body according to the circulation direction of the circulation body, and sending pre-fetching credit information to a first-level instruction cache control component according to the circulation outlet instruction information;
a sending module: when detecting that the output instruction reaches the tail of the loop body, judging the advancing direction of the loop body, and if the advancing direction of the loop body is the continuous loop direction, sending a prefetching starting signal to a prefetching credit management component of the first-level instruction cache control component; and if the advancing direction of the loop body is the loop exit direction, sending a recovery instruction fetching signal to a prefetch credit management component of the first-level instruction cache control component.
6. The apparatus as claimed in claim 5, wherein the step of sending prefetch credit information to the first level instruction cache control unit according to the loop exit instruction information further comprises:
a processing module: acquiring the total loadable instruction number and the size of a loop body, and calculating the number of prefetch instructions;
when the number of the prefetch instruction is smaller than the maximum credit value supported by the loop exit instruction information, taking the number of the prefetch instruction as the prefetch credit value in the prefetch credit information;
and when the number of the prefetch instruction is larger than the maximum credit value supported by the loop exit instruction information, taking the maximum credit value as the prefetch credit value in the prefetch credit information.
7. The apparatus as claimed in claim 6, wherein the means for prefetching the zero-level instruction loop buffer based on the dynamic credit further comprises, after "when the number of prefetched instructions is less than the maximum credit value supported by the loop exit instruction information, the number of prefetched instructions is used as the prefetch credit value in the prefetch credit information":
a sending module: when detecting that the prefetch credit value is zero, sending a pause instruction fetching signal to a prefetch credit management unit of the level one instruction cache control unit.
8. The zero-level instruction loop buffer prefetch apparatus based on dynamic credit as claimed in claim 5, wherein when "determining the loop direction of the loop body when detecting the loop body in the instruction stream", further comprising:
a sending module: when the loop body is detected, sending a pause instruction fetching signal to a prefetch credit management unit of the first-level instruction cache control unit.
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