CN110727216B - Data reading method and device of encoder and data reading device - Google Patents

Data reading method and device of encoder and data reading device Download PDF

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CN110727216B
CN110727216B CN201910898230.7A CN201910898230A CN110727216B CN 110727216 B CN110727216 B CN 110727216B CN 201910898230 A CN201910898230 A CN 201910898230A CN 110727216 B CN110727216 B CN 110727216B
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encoder
fpga
reset
signal
arm
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CN110727216A (en
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夏亮
赵晓兀
李令
谭先锋
曹祥
魏章保
兰东洋
杨海滨
杨宝军
王旭丽
韩堃
郑登华
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Chongqing Huashu Robot Co ltd
Chongqing Robotics Institute
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Chongqing Huashu Robot Co ltd
Chongqing Robotics Institute
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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B19/00—Programme-control systems
    • G05B19/02—Programme-control systems electric
    • G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers
    • G05B19/042—Programme control other than numerical control, i.e. in sequence controllers or logic controllers using digital processors
    • G05B19/0423—Input/output
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B19/00—Programme-control systems
    • G05B19/02—Programme-control systems electric
    • G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers
    • G05B19/042—Programme control other than numerical control, i.e. in sequence controllers or logic controllers using digital processors
    • G05B19/0421—Multiprocessor system

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Abstract

The invention relates to a data reading method and device of an encoder and a data reading device. The device for reading data by the encoder comprises an ARM (advanced RISC machine), an FPGA (field programmable gate array) and a storage program. Also relates to a data reading method of the encoder, which comprises the following steps: when the power is on, the FPGA analyzes a reset feedback signal from the encoder; according to the analysis result, after the encoder is determined to be reset, the FPGA sends a reset success signal to an ARM; and when the ARM receives the reset success signal, controlling an enabling signal. It also relates to a data reading device of an encoder, comprising: the device comprises an analysis module, a sending module and a control module. According to the invention, when the system is powered on, the ARM end is added to confirm the states of the FPGA end and the encoder, so that the accuracy of reading data by the ARM end is ensured, and the accuracy of data transmission of the encoder is improved.

Description

Data reading method and device of encoder and data reading device
Technical Field
The invention relates to the technical field of encoders and motor control, in particular to a data reading method and device of an encoder and a data reading device.
Background
In servo control, ARM + FPGA is a commonly used hardware solution. Because the servo control has high real-time requirement on the acquisition of the position of the motor rotating shaft, the FPGA with high real-time property is adopted to decode the serial signal of the encoder to obtain an encoder value and an alarm word. The ARM can obtain the position of the click rotating shaft only by reading the FPGA.
However, in the system power-on process, the ARM, the FPGA and the encoder are difficult to ensure the power-on at the same time due to different device characteristics. Generally, the time required for powering up the ARM and the encoder in the motor is short, and the time required for powering up the FPGA with the off-chip flash is longest. This will lead to the following problems: when the ARM and the encoder start to work and the ARM reads the encoder data at the FPGA end, the FPGA does not work at the moment, and the ARM reads an error value.
Disclosure of Invention
In order to solve the technical problems that the FPGA does not work and the ARM reads wrong values in the prior art, the invention provides a data reading method and device of an encoder and a data reading device.
The invention provides a data reading method of an encoder, which comprises the following steps: when the power is on, the power supply is started,
s1, the FPGA analyzes a reset feedback signal from the encoder;
s2, according to the analysis result, after the encoder is determined to be reset, the FPGA sends a reset success signal to an ARM;
and S3, if the ARM receives the reset success signal, controlling an enable signal.
The invention has the beneficial effects that: by the method, the reset success signal is set, so that the ARM can wait for the FPGA to prepare the encoder after being powered on, and then the encoder enable signal is controlled, thereby preventing the ARM from reading an error value.
Further, the reset feedback signal in S1 is a level pulse on an encoder output data line; the reset success signal in S2 is active high.
Further, the analyzing process comprises: the FPGA counts the level pulse, and a counting variable is set to be CNT; before the counting variable CNT does not reach a preset threshold value N, the FPGA sets the reset success signal to be 0; and when the counting variable CNT reaches a preset threshold value N, the FPGA sets the reset success signal to be 1.
The further beneficial effects are as follows: by counting the level pulses on the encoder output data line, the reset state of the encoder can be judged, and then the reset state is sent to the ARM by using a reset success signal.
Further, the ARM waits for the reset success signal to be valid all the time, and if the waiting time exceeds a preset first waiting time, an abnormal alarm is sent out.
The further beneficial effects are as follows: the encoder state can be known to the user by presetting the time for the ARM to wait for the successful reset signal to be effective.
Further, after receiving the reset success signal, the ARM sends a response signal to the FPGA.
The further beneficial effects are as follows: through the response signal, the ARM can take over the control right of the enabling signal from the FPGA.
The invention also provides a device for reading data from the encoder, which comprises an ARM (advanced RISC machine), an FPGA (field programmable gate array) and a storage program, and is characterized in that: the ARM and the FPGA are used for reading programs and can execute the steps of the method.
The present invention also provides a data reading apparatus of an encoder, comprising: the analysis module is used for controlling the FPGA to analyze a reset feedback signal from the encoder;
the sending module is used for controlling the FPGA to send a reset success signal to the ARM after the encoder is determined to be reset according to the analysis result;
and the control module is used for controlling the ARM to control an enabling signal after receiving the reset success signal.
The invention has the beneficial effects that: through foretell data reading device, set up the success signal that resets, can make ARM wait for FPGA after the power-on and prepare the encoder, control encoder enable signal again, avoided ARM to read wrong value.
Further, the FPGA controlled by the analysis module analyzes the reset feedback signal from the encoder into a level pulse on an output data line of the encoder; and the sending module controls the reset success signal sent by the FPGA to the ARM to be high-level effective.
Further, the analysis module includes: the counting module is used for controlling the FPGA to count the level pulse, and a counting variable is set as CNT; a signal setting 0 module, configured to set the reset success signal to 0 by the FPGA before the count variable CNT does not reach a preset threshold N; and the signal setting 1 module is used for setting the reset success signal to be 1 by the FPGA when the counting variable CNT reaches a preset threshold value N.
The further beneficial effects are as follows: by counting the level pulses on the encoder output data line, the reset state of the encoder can be judged, and then the reset state is sent to the ARM by using a reset success signal.
Further, the control module includes: the alarm module is used for waiting for the reset success signal to be effective all the time when the ARM is powered on, and sending an abnormal alarm when the waiting time exceeds a preset first waiting time; and the response module is used for sending a response signal to the FPGA after the ARM receives the reset success signal.
The further beneficial effects are as follows: the encoder state can be known by a user by presetting the time for waiting the valid time of the reset success signal; through the response signal, the ARM can take over the control right of the enabling signal from the FPGA.
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Fig. 1 is a flowchart illustrating a data reading method of an encoder according to an embodiment of the present invention;
fig. 2 is a second flowchart of a data reading method of an encoder according to an embodiment of the present invention;
FIG. 3 illustrates an exemplary encoder transmit and receive circuit according to an embodiment of the present invention;
fig. 4 is a schematic diagram of a control device of a data reading method of an encoder according to an embodiment of the present invention;
FIG. 5 is a diagram illustrating an encoder reset success or failure determination according to an embodiment of the present invention;
FIG. 6 is a functional block diagram of an encoder control power conversion according to an embodiment of the present invention;
FIG. 7 is a diagram illustrating an apparatus for reading data from an encoder according to an embodiment of the present invention;
fig. 8 is a schematic diagram of a data reading apparatus of an encoder according to an embodiment of the present invention.
Detailed Description
In the following description, for purposes of explanation and not limitation, specific details are set forth such as particular system structures, interfaces, techniques, etc. in order to provide a thorough understanding of the present invention. It will be apparent, however, to one skilled in the art that the present invention may be practiced in other embodiments that depart from these specific details. In other instances, detailed descriptions of well-known devices, circuits, and methods are omitted so as not to obscure the description of the present invention with unnecessary detail.
Example 1
As shown in fig. 1, embodiment 1 of the present invention provides a data reading method for an encoder, including: when the power is on, S1, the FPGA analyzes a reset feedback signal from the encoder; s2, according to the analysis result, after the encoder is determined to be reset, the FPGA sends a reset success signal to an ARM; and S3, if the ARM receives the reset success signal, controlling an enable signal.
In the prior art, the problems of different power-on of devices exist. In the system power-on process, the ARM, the FPGA and the encoder are difficult to ensure the power-on at the same time due to different device characteristics. Generally, the time required for powering up the ARM and the encoder in the motor is short, and the time required for powering up the FPGA with the off-chip flash is longest. This will lead to the following problems: when the ARM and the encoder start to work and the ARM reads the encoder data at the FPGA end, the FPGA does not work at the moment, and the ARM reads an error value.
The embodiment of the invention provides a data reading method of an encoder, and by the method, a reset success signal is set, so that an ARM can wait for an FPGA to prepare the encoder after being powered on, and then control an encoder enabling signal, thereby preventing the ARM from reading an error value.
Example 2
As shown in fig. 3, on the basis of embodiment 1, there is one encoder transmission and reception circuit. The left side of the dotted line is a section of the encoder, the right side of the dotted line is an encoder sending and receiving circuit on the PCB, the 485 chip serves as a bridge for communication between the encoder and the FPGA, the level conversion function is achieved, the differential signals of the encoder are converted into digital signals which can be identified by the FPGA, and the digital signals of the FPGA are converted into the differential signals of the encoder. The SDAT line, the SRQ line and the DE line are connected to pins of the FPGA. The SDAT line is the output of the 485 chip, sends a feedback signal of the encoder, and simultaneously serves as the input of the FPGA to receive a reset feedback signal. The SRQ line is used as the input of the 485 chip, receives a reset signal, and the output line of the FPGA sends the reset signal. When the DE line sends an enable signal on the 485 chip, the FPGA is set to be low, and the receiving time is set to be high.
As shown in fig. 4, the FPGA communicates with the encoder in a half-duplex manner. The FPGA sends command words to the SRQ line, and then receives the return data of the encoder from the SDAT line. The operation of the encoder is completed by the FPGA sending a corresponding command word to the encoder. The reset operation has a reset command word and the read position value has a read position command word. Typically, the power-up phase requires resetting the encoder, and the real-time position value is read after the reset is completed. Command word sending: and on the rising edge of the sending clock, the FPGA sends the command words from low order to high order to the SRQ line in sequence to finish serial sending. The transmit clock is typically 2.5M. After receiving the command word, the encoder responds according to the command word and returns data on the SDAT line. Data reception: and on the rising edge of the receiving clock, the FPGA sequentially reads in the serial data on the SDAT line, and converts the serial data into multi-bit data to complete serial receiving. The receive clock is typically the same clock as the transmit clock.
Example 3
On the basis of embodiment 1, in this embodiment, the reset feedback signal in S1 is a level pulse on an encoder output data line; the reset success signal in S2 is active high. The process of analyzing comprises: the FPGA counts the level pulse, and a counting variable is set to be CNT; before the counting variable CNT does not reach a preset threshold value N, the FPGA sets the reset success signal to be 0; and when the counting variable CNT reaches a preset threshold value N, the FPGA sets the reset success signal to be 1.
As shown in fig. 5, the determination of whether the encoder reset was successful or not. The EncoderOK signal in the figure is the reset success signal. The FPGA sends a reset instruction to the encoder to reset all errors, for example, the encoder is overspeed, overflows, the battery alarms and the like, the reset instruction is sent every 20uS, and the reset can be completed by continuously sending the reset instruction for 10 times. It can be known from the reset requirement description of the encoder that the reset process of the encoder is actually sending a reset command to the encoder, and the reset command lasts for a period of time at least greater than 200 uS. The CNT counts the falling edge pulses on the SDAT line (after the encoder receives the reset command from the FPGA, there must be feedback, which indicates the high/low level on the SDAT line), and its value indicates the length of the reset time. It is preferable that N is 500, and in general, when the CNT is 500, the reset time is more than 200uS, and the reset function can be completed, but it is needless to say that the value of N may be less than or greater than 500, and in practice, it is sufficient that reliable reset can be performed.
Example 4
On the basis of embodiment 2, in this embodiment, as shown in fig. 2, in a normal case where the FPGA analysis encoder is successfully reset and the ARM reads that the reset success signal is 1 within the predetermined time, the data reading method flow is steps S11 to S17; under the abnormal condition that the FPGA analysis encoder fails to reset and the ARM does not read the reset success signal to be 1 within the preset time, the data reading method flow is that steps S11 to S13 are connected with steps S18 to S21.
The encoder control right conversion is realized by a selector in the FPGA, and Verilog codes comprise the following components:
Figure BDA0002210970260000061
Figure BDA0002210970260000071
the generated functional block diagram is shown in fig. 6, where the input signals include a clock signal clk, an ARM reply signal ANS read by the FPGA terminal, an encoder control word transmission enable signal RQ _ Start _ ARM controlled by the ARM, and an encoder control word transmission enable signal RQ _ Start _ FPGA controlled by the FPGA; the output signals include an encoder control word send enable signal RQ _ Start and an encoder control word Data _ ID.
Example 5
As shown in fig. 7, on the basis of embodiment 1, this embodiment provides an apparatus for reading data from an encoder, which includes an ARM and an FPGA, and a storage program, where the ARM and the FPGA are configured to read the program and execute steps in a method flow in each embodiment of the present invention.
The FPGA sends command words to the SRQ line, and then receives the return data of the encoder from the SDAT line. The operation of the encoder is completed by the FPGA sending a corresponding command word to the encoder. The reset operation has a reset command word and the read position value has a read position command word. Typically, the power-up phase requires resetting the encoder, and the real-time position value is read after the reset is completed. Command word sending: and on the rising edge of the sending clock, the FPGA sends the command words from low order to high order to the SRQ line in sequence to finish serial sending. The transmit clock is typically 2.5M. After receiving the command word, the encoder responds according to the command word and returns data on the SDAT line. Data reception: and on the rising edge of the receiving clock, the FPGA sequentially reads in the serial data on the SDAT line, and converts the serial data into multi-bit data to complete serial receiving. The receive clock is typically the same clock as the transmit clock.
Example 6
As shown in fig. 8, the present embodiment relates to a data reading apparatus of an encoder, including: the analysis module is used for controlling the FPGA to analyze a reset feedback signal from the encoder; the sending module is used for controlling the FPGA to send a reset success signal to the ARM after the encoder is determined to be reset according to the analysis result; and the control module is used for controlling the ARM to control an enabling signal after receiving the reset success signal. The FPGA controlled by the analysis module analyzes the reset feedback signal from the encoder into a level pulse on an output data line of the encoder; and the sending module controls the reset success signal sent by the FPGA to the ARM to be high-level effective. The analysis module includes: the counting module is used for controlling the FPGA to count the level pulse, and a counting variable is set as CNT; a signal setting 0 module, configured to set the reset success signal to 0 by the FPGA before the count variable CNT does not reach a preset threshold N; and the signal setting 1 module is used for setting the reset success signal to be 1 by the FPGA when the counting variable CNT reaches a preset threshold value N. The control module includes: the alarm module is used for waiting for the reset success signal to be effective all the time when the ARM is powered on, and sending an abnormal alarm when the waiting time exceeds a preset first waiting time; and the response module is used for sending a response signal to the FPGA after the ARM receives the reset success signal.
The reader should understand that in the description of this specification, reference to the description of the terms "one embodiment," "some embodiments," "an example," "a specific example," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above are not necessarily intended to refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, various embodiments or examples and features of different embodiments or examples described in this specification can be combined and combined by one skilled in the art without contradiction.
Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention, and that variations, modifications, substitutions and alterations can be made to the above embodiments by those of ordinary skill in the art within the scope of the present invention.

Claims (10)

1. A data reading method of an encoder, comprising: when the power is on, the power supply is started,
s1, the FPGA analyzes a reset feedback signal from the encoder;
s2, according to the analysis result, after the encoder is determined to be reset, the FPGA sends a reset success signal to the ARM;
s3, if the ARM receives the reset success signal, controlling an enabling signal;
wherein analyzing the reset feedback signal from the encoder comprises: the FPGA counts the level pulse, and a counting variable is set as CNT; before the counting variable CNT does not reach a preset threshold value N, the FPGA sets the reset success signal to be 0; and when the counting variable CNT reaches a preset threshold value N, the FPGA sets the reset success signal to be 1.
2. A data reading method of an encoder according to claim 1, characterized by:
the reset feedback signal in S1 is a level pulse on an encoder output data line;
the reset success signal in S2 is active high.
3. A data reading method for an encoder according to claim 2, wherein the analyzing comprises:
the FPGA counts the level pulse, and a counting variable is set to be CNT;
before the counting variable CNT does not reach a preset threshold value N, the FPGA sets the reset success signal to be 0;
and when the counting variable CNT reaches a preset threshold value N, the FPGA sets the reset success signal to be 1.
4. The data reading method of an encoder according to claim 1, further comprising:
and when the power is on, the ARM waits for the success of resetting signal to be effective, and if the waiting time exceeds the preset first waiting time, an abnormal alarm is sent out.
5. The data reading method of an encoder according to claim 1, wherein the S3 further comprises:
and after receiving the reset success signal, the ARM sends a response signal to the FPGA.
6. A device for reading data from an encoder comprises an ARM (advanced RISC machine) and an FPGA (field programmable gate array) and a storage program, and is characterized in that:
the ARM and the FPGA are used for reading the program and executing the steps of the method of any one of the claims 1 to 5.
7. A data reading apparatus of an encoder, comprising:
the analysis module is used for controlling the FPGA to analyze a reset feedback signal from the encoder;
the sending module is used for controlling the FPGA to send a reset success signal to the ARM after the encoder is determined to be reset according to an analysis result;
the control module is used for controlling the ARM to control an enabling signal after receiving the reset success signal;
wherein analyzing the reset feedback signal from the encoder comprises: the FPGA counts the level pulse, and a counting variable is set as CNT; before the counting variable CNT does not reach a preset threshold value N, the FPGA sets the reset success signal to be 0; and when the counting variable CNT reaches a preset threshold value N, the FPGA sets the reset success signal to be 1.
8. A data reading apparatus of an encoder according to claim 7, wherein:
the FPGA controlled by the analysis module analyzes the reset feedback signal from the encoder into a level pulse on an output data line of the encoder;
and the sending module controls the reset success signal sent by the FPGA to the ARM to be high-level effective.
9. A data reading apparatus of an encoder according to claim 8, wherein:
the analysis module includes:
the counting module is used for controlling the FPGA to count the level pulse, and a counting variable is set as CNT;
a signal setting 0 module, configured to set the reset success signal to 0 by the FPGA before the count variable CNT does not reach a preset threshold N;
and the signal setting 1 module is used for setting the reset success signal to be 1 by the FPGA when the counting variable CNT reaches a preset threshold value N.
10. The data reading apparatus of an encoder according to claim 7, wherein the control module comprises: the alarm module is used for waiting for the reset success signal to be effective all the time when the ARM is powered on, and sending an abnormal alarm when the waiting time exceeds a preset first waiting time; and the response module is used for sending a response signal to the FPGA after the ARM receives the reset success signal.
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