CN116795764B - Control method and device for SPI master device to read data in slave device - Google Patents
Control method and device for SPI master device to read data in slave device Download PDFInfo
- Publication number
- CN116795764B CN116795764B CN202311064358.6A CN202311064358A CN116795764B CN 116795764 B CN116795764 B CN 116795764B CN 202311064358 A CN202311064358 A CN 202311064358A CN 116795764 B CN116795764 B CN 116795764B
- Authority
- CN
- China
- Prior art keywords
- level
- target
- clock signal
- slave device
- data
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000000034 method Methods 0.000 title claims abstract description 36
- 238000012545 processing Methods 0.000 claims abstract description 36
- 238000012544 monitoring process Methods 0.000 claims abstract description 15
- 230000001052 transient effect Effects 0.000 claims description 34
- 230000000630 rising effect Effects 0.000 claims description 10
- 238000010586 diagram Methods 0.000 description 13
- 238000005070 sampling Methods 0.000 description 7
- 230000005540 biological transmission Effects 0.000 description 5
- 239000003990 capacitor Substances 0.000 description 2
- 230000006870 function Effects 0.000 description 2
- 230000001360 synchronised effect Effects 0.000 description 2
- 230000001960 triggered effect Effects 0.000 description 2
- 208000033748 Device issues Diseases 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 230000000750 progressive effect Effects 0.000 description 1
Classifications
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Landscapes
- Information Transfer Systems (AREA)
Abstract
The application discloses a control method and equipment for SPI master equipment to read data in slave equipment, wherein the method is applied to the slave equipment and comprises the following steps: monitoring whether the processing of target data on the slave device is completed or not; controlling a clock signal between the master device and the slave device to remain at a first level in the event that the target data processing is not complete; and controlling the clock signal to be restored to a second level for instructing the master device to read the target data in the case where the data reading condition is satisfied.
Description
Technical Field
The application relates to the technical field of intelligent customer service, in particular to a control method and equipment for SPI master equipment to read data in slave equipment.
Background
SPI (Serial Peripheral Interface) transmission typically uses two shift registers of a given word length, one in the master and one in the slave, connected as a virtual ring buffer. A SCLK (SimplifiedCLocK) pin is provided by the master to provide a clock signal to the slave.
The master device receives data bits sent by the slave device from the data bus at the trailing edges of the clock signal, but if the slave device does not timely transmit the data to the data bus, the master device can be caused to sample invalid data at each trailing edge of the clock signal, so that the data processing flow on the master device is increased.
Therefore, there is a need for a control that can read data from a slave device by a master device that is convenient, and that avoids the master device from sampling excessive invalid data.
Disclosure of Invention
In view of this, the present application provides a control method and device for a master device of an SPI to read data from a slave device, so as to solve the technical defect that the master device samples excessive invalid data in the prior art, as follows:
a control method for a master device of an SPI to read data in a slave device, applied to the slave device, the method comprising:
monitoring whether the processing of target data on the slave device is completed or not;
controlling a clock signal between the master device and the slave device to remain at a first level in the event that the target data processing is not complete;
and controlling the clock signal to be restored to a second level for instructing the master device to read the target data in the case where the data reading condition is satisfied.
The above method, preferably, the data reading condition includes any one of the following:
the target data is completely written on a data reading bus between the master device and the slave device, and the second level is used for indicating the master device to read the target data from the data reading bus;
or alternatively, the first and second heat exchangers may be,
the duration of the clock signal kept at the first level reaches a preset target duration, and the target duration comprises at least one clock cycle of the clock signal.
In the above method, preferably, a monostable trigger is provided in the slave device, the monostable trigger is connected with a MOS tube, the MOS tube is connected with a first pin of the slave device, the first pin is connected with a second pin in the master device, and the second pin is used for providing the clock signal;
wherein said controlling the clock signal between the master device and the slave device to remain at a first level comprises:
and sending a target level to the monostable trigger to enable the monostable trigger to enter a transient state, wherein the monostable trigger under the transient state can output a high level so that the MOS tube clamps the clock signal to a first level.
In the above method, preferably, in a case that the master device and the slave device are in a first working mode, the MOS transistor is an NMOS transistor; the first working mode is a mode that the main equipment collects data when the clock signal enters a rising edge;
wherein the NMOS transistor clamps the clock signal to a first level, the first level being a low level, upon receiving a high level of the monostable flip-flop output.
In the above method, preferably, in a case that the master device and the slave device are in the second working mode, the MOS transistor is a PMOS transistor; the second working mode is a mode that the main equipment collects data when the clock signal enters a rising edge;
wherein the PMOS transistor clamps the clock signal to a first level, the first level being a high level, upon receiving a high level of the monostable flip-flop output.
In the above method, preferably, the monostable trigger at least includes a plurality of standby resistors, and the slave device is configured with a register, where the register is used to store the target duration;
wherein the method further comprises:
and determining a target resistance in the plurality of standby resistances according to the target duration in the register, wherein the target resistance enables the monostable trigger to enter the transient state when the target level is received, the monostable trigger is restored to a steady state after the transient state is maintained for the target duration, and the monostable trigger in the steady state can output a low level so that the MOS tube stops clamping the clock signal at the first level.
In the above method, preferably, the slave device is configured with an enable bit;
wherein before monitoring whether processing of the target data on the slave device is complete, the method further comprises:
judging whether the enabling bit is in a target state, and if so, executing the following steps: and monitoring whether the processing of the target data on the slave device is finished.
A slave device of an SPI, comprising:
the flow controller is used for monitoring whether the processing of the target data on the slave equipment is finished or not; controlling a clock signal between the master device and the slave device to remain at a first level in the event that the target data processing is not complete; and controlling the clock signal to be restored to a second level for instructing the master device to read the target data in the case where the data reading condition is satisfied.
The above-mentioned SPI slave device preferably further comprises:
a monostable trigger;
the MOS tube is connected with the monostable trigger, the MOS tube is connected with a first pin of the slave equipment, the first pin is connected with a second pin in the master equipment, and the second pin is used for providing the clock signal;
the current controller is specifically configured to send a target level to the monostable trigger, so that the monostable trigger enters a transient state, and the monostable trigger under the transient state can output a high level, so that the MOS transistor clamps the clock signal to a first level.
Preferably, the slave device of the SPI further includes a monostable flip-flop including at least a plurality of standby resistors, and a register configured in the slave device, where the register is configured to store the target duration;
wherein, the flow controller is further used for: and determining a target resistance in the plurality of standby resistances according to the target duration in the register, wherein the target resistance enables the monostable trigger to enter the transient state when the target level is received, the monostable trigger is restored to a steady state after the transient state is maintained for the target duration, and the monostable trigger in the steady state can output a low level so that the MOS tube stops clamping the clock signal at the first level.
According to the control method and the device for the SPI master device to read the data in the slave device, whether the target data is processed or not is monitored on the slave device, when the target data on the slave device is not processed, the clock signal is kept at the first level, so that the master device does not read the target data, and when the data condition is met, the clock signal is restored to the second level, so that the master device can read the target data. Therefore, in the time period from the time when the data of the monitoring slave device is not processed to the time when the data reading condition is met, the clock signal is kept at the first level, the master device cannot read the target data in the time period, the master device is prevented from reading invalid data in the time period, the data processing flow on the master device cannot be increased, and the data processing efficiency is improved.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the description of the embodiments will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a flowchart of a control method for an SPI master device to read data from a slave device according to an embodiment of the present application;
FIG. 2 is a schematic diagram of data transmission between SPI master and slave;
FIG. 3 is an exemplary diagram of configuring a monostable flip-flop in a slave device in an embodiment of the present application;
FIG. 4 is a schematic diagram of clock signal synchronization between SPI master and slave;
FIG. 5 is an exemplary diagram of a monostable flip-flop;
FIG. 6 is an exemplary diagram of slave device clocking in a first mode of operation according to an embodiment of the present application;
FIG. 7 is an exemplary diagram of slave device clocking in a second mode of operation according to an embodiment of the present application;
FIG. 8 is an exemplary diagram of a monostable flip-flop in an embodiment of the present application;
fig. 9 is another flowchart of a control method for an SPI master device to read data from a slave device according to an embodiment of the present application;
fig. 10 is a schematic structural diagram of an SPI slave device according to a second embodiment of the present disclosure;
fig. 11, fig. 12, fig. 13, fig. 14, and fig. 15 are respectively another schematic structural diagrams of an SPI slave device according to a second embodiment of the present application;
fig. 16 is a diagram illustrating clock signals with cpol=1 as an example in the embodiment of the present application;
fig. 17 is an exemplary diagram of a slave device taking cpol=1 as an example in the embodiment of the present application;
fig. 18 is an exemplary diagram of a slave device taking cpol=0 as an example in the embodiment of the present application.
Detailed Description
The following description of the embodiments of the present application will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are only some, but not all, of the embodiments of the present application. All other embodiments, which can be made by one of ordinary skill in the art without undue burden from the present disclosure, are within the scope of the present disclosure.
Referring to fig. 1, a flowchart of a control method for an SPI master device to read data in a slave device according to an embodiment of the present application is shown, where the method is applicable to the slave device. As shown in fig. 2, SPI transmission is performed between the master device and the slave device, the master device generates a clock signal through the baud rate generator, the clock signal is provided to the slave device, and data transmission is performed between the master device and the slave device based on the synchronized clock signal. The technical scheme in the embodiment is mainly used for avoiding the master device from reading excessive invalid data when the master device reads the data of the slave device.
Specifically, the method in this embodiment may include:
step 101: it is monitored whether the processing of the target data on the slave device is complete, and in case the processing of the target data is not complete, step 102 is performed.
The target data is data which needs to be provided for the main device to sample, namely: the master device needs to read the target data in the slave device. The target data processing completion can be understood as: the target data is written entirely onto the data read bus MISO (Master Input Slave Output) between the master and the slave. If the target data is not processed, it indicates that no data has been provided to the master device for sampling on the MISO, at which point step 102 is performed.
Specifically, in this embodiment, it may be monitored whether the processing of the target data on the slave device is completed by reading the data status bit on the slave device. For example, in the case of a data status bit of 1, this indicates that the processing of the target data on the slave device is complete, and in the case of a data status bit of 0, this indicates that the processing of the target data on the slave device is not complete.
It should be noted that, in this embodiment, after the clock signal enters the first level, monitoring is started to determine whether the processing of the target data on the slave device is completed.
Step 102: the clock signal between the master device and the slave device is controlled to be maintained at a first level.
The clock signal is synchronized between the master device and the slave device, and in this embodiment, the clock signal is controlled to be kept at the first level, so that the clock signal on the master device and the clock signal on the slave device are both at the first level.
It should be noted that there are multiple operation modes between the master device and the slave device, such as a first operation mode in which the master device collects data when the clock signal enters a rising edge, and a second operation mode in which the master device collects data when the clock signal enters a falling edge. Based on this, in the case where the master device and the slave device are in the first operation mode, the first level is a low level; in the case where the master device and the slave device are in the second operation mode, the first level is a high level, and the first level makes the master device not read the target data.
Step 103: whether the data reading condition is satisfied is monitored, and if the data reading condition is satisfied, step 104 is executed.
In this embodiment, whether the data reading condition is satisfied may be monitored by software or hardware.
Specifically, the data reading conditions are: conditions such that the master device reads the target data, such as completion of target data processing, etc.
Step 104: the control clock signal is restored to a second level for instructing the master device to read the target data.
Wherein the second level is a level different from the first level. For example, in the case where the first level is a low level, the second level is a high level; in the case where the first level is a high level, the second level is a low level.
In one implementation, the data read conditions include: the target data is written entirely onto the data read bus between the master and slave. At this time, the second level is used to instruct the host device to read the target data from the data read bus. For example, in this embodiment, when the target data is all written to the MISO, the clock signal is restored to the second level, so that the master device samples the target data from the MISO, thereby avoiding the master device from sampling invalid data in the data transmission scenario from the slave device to the master device.
In another implementation, the data read conditions include: the duration of the clock signal maintained at the first level reaches a preset target duration comprising at least one clock cycle of the clock signal. The clock period may be the sum of the durations of adjacent ones of the high and low levels in the clock signal. For example, in this embodiment, the target duration is preconfigured, and when the duration of the clock signal kept at the first level reaches the target duration, the clock signal is restored to the second level, so that the master device samples the target data from the MISO, which can avoid that the master device samples too much invalid data, and also avoid that the master device cannot sample the data all the time due to the fact that the clock signal is kept at the first level for too long.
In another implementation, the data read conditions include: the target data is written entirely on the data read bus between the master and slave, or the duration of the clock signal maintained at the first level reaches a preset target duration. That is, when any of the above is satisfied, the clock signal is restored to the second level in this embodiment, so that the master device samples the target data from the MISO, thereby enabling the master device to sample as little as possible to excessive invalid data, and also avoiding the situation that the master device cannot sample the data all the time.
According to the control method for the SPI master device to read the data in the slave device, whether the target data is processed is monitored on the slave device, when the target data on the slave device is not processed, the clock signal is kept at the first level, so that the master device does not read the target data, and when the data condition is met, the clock signal is restored to the second level, so that the master device can read the target data. Therefore, in this embodiment, the clock signal is maintained at the first level in the period from when the data of the slave device is not processed to when the data reading condition is satisfied, and the master device will not read the target data in this period, so that the master device will not read the invalid data in this period, and the data processing flow on the master device will not be increased, thereby improving the data processing efficiency.
In one implementation, a monostable trigger is provided in the slave device, as shown in fig. 3, and is connected to a MOS transistor, which is connected to a first pin of the slave device, such as the SCLK pin, which is connected to a second pin in the master device, which is used to provide the clock signal.
For example, as shown in fig. 4, a clock signal is generated in the master device by a baud rate generator, the clock signal is transmitted to an SCLK Pin (PAD) in the master device after being subjected to level conversion, IO multi-stage driving, and the like, the SCLK pin in the master device is connected with an SCLK pin of the slave device, the master device obtains the clock signal from the own SCLK pin, and the slave device also obtains the clock signal from the own SCLK pin, thereby achieving synchronization of the clock signals between the master device and the slave device.
Based on this, in this embodiment, when the clock signal between the master device and the slave device is controlled to be maintained at the first level in step 102, this is specifically achieved by:
and sending a target level such as a low level to the monostable trigger, so that the monostable trigger enters a transient state, and the monostable trigger under the transient state can output a high level, so that the MOS tube clamps a clock signal to a first level.
The monostable flip-flop in this embodiment may be a CMOS integrated monostableA state trigger, as shown in FIG. 5, V DD Providing power for monostable flip-flop, left side V I Is the input end of the monostable trigger, the right side V O The monostable trigger also comprises a resistor R and a capacitor C, wherein the size of the resistor R and the capacitor C determines the transient state time of the monostable trigger.
In one case, in the case where the master device and the slave device are in the first operation mode, the MOS transistor is an NMOS transistor, as shown in fig. 6; the first working mode is a mode that the main equipment collects data when the clock signal enters a rising edge.
Wherein the NMOS transistor clamps the clock signal to a first level, which is a low level, upon receiving a high level of the monostable flip-flop output.
For example, in the first working mode of CPOL (clock POLarity) =1, when it is detected that the target data is not processed, the low level is sent to the input end of the monostable flip-flop, so that the monostable flip-flop outputs a high level to trigger the NMOS transistor to be turned on, i.e. grounded, so as to clamp the clock signal on the SCLK pin to the ground, i.e. to low level, and the master device does not sample data from the MISO at the low level, thereby avoiding the master device from sampling excessive invalid data when the target data is not processed.
In another case, in the case where the master device and the slave device are in the second operation mode, the MOS transistor is a PMOS transistor, as shown in fig. 7; the second working mode is a mode that the main equipment collects data when the clock signal enters a rising edge;
wherein the PMOS transistor clamps the clock signal to a first level, which is a high level, upon receiving a high level of the monostable flip-flop output.
For example, in cpol=0, that is, in the second operation mode, when it is monitored that the target data is not processed, in this embodiment, a low level is sent to the input end of the monostable flip-flop, so that the monostable flip-flop outputs a high level, the PMOS transistor is turned on after the inversion, and further, the clock signal on the SCLK pin is clamped to a high level, and the master device does not sample data from the MISO under the high level, thereby avoiding the master device from sampling excessive invalid data when the target data is not processed.
In one implementation, the monostable flip-flop includes at least a plurality of standby resistors, such as R0, R1, R2, etc., and the slave device is configured with a register, where the register is used to store a target duration, such as a duration of N clock cycles, as shown in fig. 8.
Based on this, the following processing may be further included in the present embodiment:
according to the target duration in the register, determining a target resistance in a plurality of standby resistances contained in the monostable trigger, wherein the target resistance enables the monostable trigger to enter a transient state when receiving the target level, and the monostable trigger is restored to a steady state after the target duration is maintained by the transient state, and the monostable trigger in the steady state can output a low level so that the MOS tube stops clamping the clock signal at a first level.
That is, in this embodiment, according to a target duration preset in the register, a corresponding target resistor is selected, so that the duration of the transient state of the monostable trigger can be restored to the steady state when the target duration is reached.
Specifically, each standby resistor in the monostable trigger is correspondingly provided with a switch, and the switch is connected with the standby resistor in series. Based on this, in this embodiment, the resistance value may be calculated according to the target duration in the register and the capacitance in the monostable trigger, a target resistor with a matched resistance value is selected in the monostable trigger according to the calculated resistance value, a switch corresponding to the target resistor is closed, the duration of the monostable trigger in a transient state is made to be the target duration through the target resistor and the capacitance, when the duration of the monostable trigger in the transient state reaches the target duration, the monostable trigger is restored to a steady state, that is, a low level is output, so that the MOS tube stops clamping the clock signal at the first level, that is, the clock signal is restored to the second level, so as to instruct the main device to read the target data.
In one implementation, the slave device is configured with an enable bit that indicates whether to execute the control flow in this embodiment. In particular, the enable bit may be written in a register of the slave device.
Based on this, before monitoring whether the processing of the target data on the slave device is completed in step 101, the following steps may be performed in this embodiment, as shown in fig. 9:
step 100: it is determined whether the enable bit is in the target state, if the enable bit is 1, if yes, step 101 is performed, i.e. it is monitored whether the processing of the target data on the slave device is completed.
If the enable bit is not in the target state, e.g., 0, then step 101 is not performed.
That is, in the present embodiment, it is determined whether the enable bit in the register is 1, and if it is 1, the control flow shown in fig. 1 is executed in the present embodiment, and if it is 0, it is indicated that no flow control is required on the slave device, that is, the control flow shown in fig. 1 is not executed.
Referring to fig. 10, a schematic structural diagram of an SPI slave device according to a second embodiment of the present application is shown in fig. 2. The technical scheme in the embodiment is mainly used for avoiding the master device from reading excessive invalid data when the master device reads the data of the slave device.
Specifically, the slave device in this embodiment may include the following structure:
the flow controller 1001, the flow controller 1001 may be implemented as a control chip, etc. for monitoring whether the processing of the target data on the slave device is completed; controlling a clock signal between the master device and the slave device to remain at a first level in the event that the target data processing is not complete; and controlling the clock signal to be restored to a second level for instructing the master device to read the target data in the case where the data reading condition is satisfied.
Wherein the data reading condition includes any one of the following:
the target data is completely written on a data reading bus between the master device and the slave device, and the second level is used for indicating the master device to read the target data from the data reading bus;
or alternatively, the first and second heat exchangers may be,
the duration of the clock signal kept at the first level reaches a preset target duration, and the target duration comprises at least one clock cycle of the clock signal.
As can be seen from the above technical solution, in the slave device of the SPI provided in the second embodiment of the present application, by monitoring whether the target data is processed on the slave device, when the target data on the slave device is not processed, the clock signal is maintained at the first level, so that the master device does not read the target data, and when the data condition is satisfied, the clock signal is restored to the second level, so that the master device reads the target data. Therefore, in this embodiment, the clock signal is maintained at the first level in the period from when the data of the slave device is not processed to when the data reading condition is satisfied, and the master device will not read the target data in this period, so that the master device will not read the invalid data in this period, and the data processing flow on the master device will not be increased, thereby improving the data processing efficiency.
In one implementation, the slave device in this embodiment may further include the following structure, as shown in fig. 11:
monostable flip-flop 1002;
the MOS tube 1003, the monostable trigger 1002 is connected with the MOS tube 1003, the MOS tube 1003 is connected with a first pin 1004 of the slave device, the first pin 1004 is connected with a second pin 1005 in the master device, and the second pin 1005 is used for providing the clock signal;
the current controller 1001 is specifically configured to send a target level to the monostable flip-flop 1002, so that the monostable flip-flop 1002 enters a transient state, and the monostable flip-flop 1002 under the transient state can output a high level, so that the MOS transistor 1003 clamps the clock signal to a first level.
Specifically, in the case where the master device and the slave device are in the first operation mode, the MOS transistor 1003 is an NMOS transistor 1031, as shown in fig. 12; the first working mode is a mode that the main equipment collects data when the clock signal enters a rising edge;
wherein, the NMOS transistor 1031 clamps the clock signal to a first level, which is a low level, upon receiving a high level output by the monostable flip-flop 1002.
In the case where the master device and the slave device are in the second operation mode, the MOS transistor 1003 is a PMOS transistor 1032, as shown in fig. 13; the second working mode is a mode that the main equipment collects data when the clock signal enters a rising edge;
wherein, the PMOS transistor 1032 clamps the clock signal to a first level, which is a high level, upon receiving a high level output from the monostable flip-flop 1002.
In one implementation manner, the monostable 1002 includes at least a plurality of standby resistors R, such as R0, R1, R2, etc., and the slave device is configured with a register 1006, where the register 1006 is used to store the target duration, as shown in fig. 14 or fig. 15;
wherein, the flow controller 1001 is further configured to: a target resistance is determined in the plurality of standby resistances R according to the target duration in the register 1006, the target resistance causing the monostable flip-flop 1002 to enter the transient state upon receiving the target level, and the monostable flip-flop 1002 returns to a steady state after the transient state is maintained for the target duration, the monostable flip-flop 1002 in the steady state being able to output a low level to cause the MOS transistor 1003 (NMOS transistor 1031 or PMOS transistor 1032) to stop clamping the clock signal at the first level.
In addition, the register 1006 is further configured with an enable bit, and before the flow controller 1001 monitors whether the processing of the target data on the slave device is completed, the enable bit is further used for: and judging whether the enabling bit is in a target state, and if so, monitoring whether the target data on the slave equipment is processed.
In a specific implementation, the SPI slave device can delay the edge of the data sample by one or more periods to realize flow control. If the slave device is not ready to send data after the SCLK leading edge is triggered, the flow control is ended by clamping the SCLK at the current level for a period of time (one or more clock cycles), i.e. suppressing subsequent edge generation, and releasing the clamp of the SCLK after the data is ready and sent.
Whichever of the four modes the SPI operates in is that the leading edge changes data (transmits data) and the trailing edge samples data (captures data).
Taking cpha=1 and cpol=1 (high level when the clock is idle) as an example, as shown in fig. 16, when there is no flow control, the data is sent after the leading edge (falling edge) is triggered; trailing (rising) edges sample the data.
If the slave device is not ready for data after the leading edge (falling edge) trigger, clamp SCLK low, i.e., flow control begins; after the data is sent to the MISO, the clamp of SCLK is released, i.e. the flow control is ended.
The flow control time from the beginning to the end of the flow control (from SCLK block at current level-release SCLK block), shown in fig. 16 is one cycle, which may be multiple cycles.
Specifically, the SPI slave uses the clock provided by the master, and in this application, a CMOS integrated monostable flip-flop is used to implement the delay of the clock signal, as shown in fig. 5.
Further, the flow control time of different working frequencies can be matched by adjusting the value of R in the present application, as shown in fig. 17.
The specific scheme is as follows:
firstly, the implementation of the control flow control function in the register 1 is written in by the initialization of the main device, and the implementation comprises the following contents:
fluidic period (ns): the transient time length (delay time size) used to configure the monostable trigger is the target duration.
And a flow control enable bit for controlling whether flow control is enabled.
Secondly, the flow controller is used for realizing the flow control function as follows:
according to the flow control period configured by the register 1, whether the switches before R0, R1 and R2 are closed or not is selected, so that the delay time matched with the working frequency is set.
After flow control is enabled, after SCLK leading edge (falling edge) triggers, if the data is not ready and flow control needs to be started:
the flow controller monitors the data processing state of the slave device, and if the data is not processed, the monostable circuit is activated to enter a transient state by inputting a low level into the input end of the monostable trigger.
When in transient state, the monostable trigger outputs high level, the NMOS transistor is turned on, and SCLK is clamped to ground.
After the data is ready and sent to the MISO, and at the same time, the data read conditions (data all sent to the MISO or flow control period arrives) are met, the monostable flip-flop resumes steady state, NMOS transistor turns off, flow control ends, SCLK resumes high, and the master samples the data from the MISO.
Cpol=0, i.e., trailing edge (falling edge) data sampling, as shown in fig. 18, the monostable flip-flop outputs a high level at transient, the PMOS transistor turns on after inversion, clamping SCLK to a high level, so that the master device pauses sampling data, and after the monostable flip-flop resumes steady state, the master device samples data from MISO.
Therefore, in the application, the SCLK is clamped at the current level at the transient state of the monostable trigger to realize the flow control, and the duration of the transient state is changed by changing the resistance and the capacitance resistance. The master device issues SCLK, and the slave device clamps SCLK at the current level during the flow control corresponds to a clock extension that is deliberately recognized by the SPI master device and synchronously extended, thereby meeting the scenario application requirements.
In the present specification, each embodiment is described in a progressive manner, and each embodiment is mainly described in a different point from other embodiments, and identical and similar parts between the embodiments are all enough to refer to each other. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant points refer to the description of the method section.
Those of skill would further appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, computer software, or combinations of both, and that the various illustrative elements and steps are described above generally in terms of functionality in order to clearly illustrate the interchangeability of hardware and software. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the solution. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.
The steps of a method or algorithm described in connection with the embodiments disclosed herein may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. The software modules may be disposed in Random Access Memory (RAM), memory, read Only Memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the application. Thus, the present application is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (8)
1. A control method for a master device of an SPI to read data in a slave device, the method being applied to the slave device, the method comprising:
monitoring whether the processing of target data on the slave device is completed or not;
controlling a clock signal between the master device and the slave device to remain at a first level in the event that the target data processing is not complete;
controlling the clock signal to be restored to a second level for instructing the master device to read the target data in the case where a data reading condition is satisfied;
the slave device is provided with a monostable trigger, the monostable trigger is connected with an MOS tube, the MOS tube is connected with a first pin of the slave device, the first pin is connected with a second pin in the master device, and the second pin is used for providing the clock signal;
wherein said controlling the clock signal between the master device and the slave device to remain at a first level comprises:
and sending a target level to the monostable trigger to enable the monostable trigger to enter a transient state, wherein the monostable trigger under the transient state can output a high level so that the MOS tube clamps the clock signal to a first level.
2. The method of claim 1, wherein the data reading conditions comprise any one of:
the target data is completely written on a data reading bus between the master device and the slave device, and the second level is used for indicating the master device to read the target data from the data reading bus;
or alternatively, the first and second heat exchangers may be,
the duration of the clock signal kept at the first level reaches a preset target duration, and the target duration comprises at least one clock cycle of the clock signal.
3. The method of claim 1, wherein the MOS transistor is an NMOS transistor if the master device and the slave device are in a first mode of operation; the first working mode is a mode that the main equipment collects data when the clock signal enters a rising edge;
wherein the NMOS transistor clamps the clock signal to a first level, the first level being a low level, upon receiving a high level of the monostable flip-flop output.
4. The method of claim 1, wherein the MOS transistor is a PMOS transistor if the master device and the slave device are in a second mode of operation; the second working mode is a mode that the main equipment collects data when the clock signal enters a rising edge;
wherein the PMOS transistor clamps the clock signal to a first level, the first level being a high level, upon receiving a high level of the monostable flip-flop output.
5. The method of claim 1, wherein the monostable trigger comprises at least a plurality of standby resistors, and the slave device is configured with a register, and the register is used for storing a target duration;
wherein the method further comprises:
and determining a target resistance in the plurality of standby resistances according to the target duration in the register, wherein the target resistance enables the monostable trigger to enter the transient state when the target level is received, the monostable trigger is restored to a steady state after the transient state is maintained for the target duration, and the monostable trigger in the steady state can output a low level so that the MOS tube stops clamping the clock signal at the first level.
6. The method of claim 1, wherein the slave device is configured with an enable bit;
wherein before monitoring whether processing of the target data on the slave device is complete, the method further comprises:
judging whether the enabling bit is in a target state, and if so, executing the following steps: and monitoring whether the processing of the target data on the slave device is finished.
7. A slave device for SPI, comprising:
the flow controller is used for monitoring whether the processing of the target data on the slave equipment is finished or not; controlling a clock signal between a master device and the slave device to be maintained at a first level in a case where the target data processing is not completed; controlling the clock signal to be restored to a second level for instructing the master device to read the target data in the case where a data reading condition is satisfied;
wherein, still include:
a monostable trigger;
the MOS tube is connected with the monostable trigger, the MOS tube is connected with a first pin of the slave equipment, the first pin is connected with a second pin in the master equipment, and the second pin is used for providing the clock signal;
the current controller is specifically configured to send a target level to the monostable trigger, so that the monostable trigger enters a transient state, and the monostable trigger under the transient state can output a high level, so that the MOS transistor clamps the clock signal to a first level.
8. The SPI slave device according to claim 7, wherein the monostable trigger includes at least a plurality of standby resistors, and a register is configured in the slave device, the register being configured to store a target time length;
wherein, the flow controller is further used for: and determining a target resistance in the plurality of standby resistances according to the target duration in the register, wherein the target resistance enables the monostable trigger to enter the transient state when the target level is received, the monostable trigger is restored to a steady state after the transient state is maintained for the target duration, and the monostable trigger in the steady state can output a low level so that the MOS tube stops clamping the clock signal at the first level.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311064358.6A CN116795764B (en) | 2023-08-23 | 2023-08-23 | Control method and device for SPI master device to read data in slave device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311064358.6A CN116795764B (en) | 2023-08-23 | 2023-08-23 | Control method and device for SPI master device to read data in slave device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN116795764A CN116795764A (en) | 2023-09-22 |
| CN116795764B true CN116795764B (en) | 2024-01-02 |
Family
ID=88046215
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202311064358.6A Active CN116795764B (en) | 2023-08-23 | 2023-08-23 | Control method and device for SPI master device to read data in slave device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN116795764B (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111427828A (en) * | 2020-03-02 | 2020-07-17 | 深圳震有科技股份有限公司 | SPI flow control method, system, master device, slave device and storage medium |
| CN111490920A (en) * | 2019-01-29 | 2020-08-04 | 杭州海康汽车技术有限公司 | SPI-based data transmission method, system and device |
| CN116049054A (en) * | 2022-12-30 | 2023-05-02 | 成都电科星拓科技有限公司 | Data read-write method and system of SPI slave device in cross-clock domain |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8156274B2 (en) * | 2009-02-02 | 2012-04-10 | Standard Microsystems Corporation | Direct slave-to-slave data transfer on a master-slave bus |
-
2023
- 2023-08-23 CN CN202311064358.6A patent/CN116795764B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111490920A (en) * | 2019-01-29 | 2020-08-04 | 杭州海康汽车技术有限公司 | SPI-based data transmission method, system and device |
| CN111427828A (en) * | 2020-03-02 | 2020-07-17 | 深圳震有科技股份有限公司 | SPI flow control method, system, master device, slave device and storage medium |
| CN116049054A (en) * | 2022-12-30 | 2023-05-02 | 成都电科星拓科技有限公司 | Data read-write method and system of SPI slave device in cross-clock domain |
Also Published As
| Publication number | Publication date |
|---|---|
| CN116795764A (en) | 2023-09-22 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US20020108011A1 (en) | Dual interface serial bus | |
| EP1979822A1 (en) | Data bus interface with interruptible clock | |
| US20170104607A1 (en) | Methods to avoid i2c void message in i3c | |
| EP4116836A1 (en) | Equalization time configuration method, chip, and communications system | |
| US20180173665A1 (en) | Hard reset over i3c bus | |
| US8639851B2 (en) | Serial bit processor | |
| WO2018112242A1 (en) | Hard reset over i3c bus | |
| CN102253910A (en) | Inter-integrated circuit (I2C) transmission method and device | |
| US7500042B2 (en) | Access control device for bus bridge circuit and method for controlling the same | |
| JPS6239580B2 (en) | ||
| CN110647486A (en) | PCIe link training method, end equipment and communication system | |
| CN116795764B (en) | Control method and device for SPI master device to read data in slave device | |
| US20170371830A1 (en) | Accelerated i3c master stop | |
| CN116541329A (en) | Data transmission method, device, equipment and medium | |
| CN110750478A (en) | Multi-serial port communication method and system | |
| CN106982156B (en) | Priority setting method, device, communication system, equipment and readable storage medium storing program for executing | |
| US20140333344A1 (en) | Adaptive interface for coupling fpga modules | |
| JP2958601B2 (en) | Data communication method | |
| US6772360B2 (en) | Extension signal generator coupled to an extension timer and an extension register to generate an initialization extension signal | |
| CN112947287A (en) | Control method, controller and electronic equipment | |
| JP7092612B2 (en) | Electronic control device | |
| EP2637105A1 (en) | Communication device, method and system | |
| US20190101592A1 (en) | Systems and methods for bypass testing | |
| JPS639337A (en) | Communication control system for system using serial interface | |
| CN117707868A (en) | SPI slave enabling method, system and device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |