CN110726884A - Remote phase checking instrument based on charged indicator and phase checking method - Google Patents
Remote phase checking instrument based on charged indicator and phase checking method Download PDFInfo
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Abstract
The invention relates to a remote phase checking instrument based on a charged indicator and a phase checking method, wherein the remote phase checking instrument comprises a battery module, an AD conversion module, an FPGA main chip, an internal clock module, a storage module, an LCD display screen, a trigger button and an acquisition signal connecting hole; the phase checking method adopts an internal algorithm to eliminate the influence caused by clock errors and acquisition errors, thereby reducing the number of satellite time setting modules, simplifying the modules, reducing the equipment cost, greatly facilitating the use and avoiding finding an open place to acquire satellite signals.
Description
Technical Field
The invention relates to the technical field of remote phase checking of power distribution network cable construction, in particular to a remote phase checking instrument and a phase checking method based on a charged indicator.
Background
The problem of phase change of the distribution network cable feeder in the construction process causes the situation that phases at two ends of a line are inconsistent. The loop closing operation of the feeder line under the condition of inconsistent phase sequence can cause interphase short circuit and even three-phase short circuit fault, and the result is not imaginable. In order to ensure that the phases of the two feeders at a disconnection point are consistent after construction, remote phase checking is usually performed on the two feeders before construction, and site cable construction is guided by a remote phase checking result. Therefore, correctly and effectively performing remote phase checking is an important task in the safe operation of the power system.
The traditional remote phase checking equipment is used for timing handheld terminals in two different places by means of a GPS satellite, the cable phase information is collected at the same time in an appointed mode, the collected results are compared in a manual communication mode, people in different places are required to be accurately matched, and the traditional remote phase checking equipment is abandoned in practical application due to the fact that the traditional remote phase checking equipment is not suitable for many occasions.
Disclosure of Invention
In view of the above, the present invention provides a remote phase checking instrument and a phase checking method based on a charged indicator, which are small, flexible, safe and reliable, and can be used by a single person without environmental limitation, thereby effectively improving the phase checking efficiency.
The invention is realized by adopting the following scheme: a remote nuclear phase method comprising the steps of:
step S1: acquiring voltage signals of two cycles of ABC three phases at a position A, and respectively acquiring corresponding moments of rising edge zero-crossing points of ABC three-phase values, namely T1 moments, T2 moments and T3 moments;
step S2: acquiring voltage signals of two cycles of an abc three-phase at a position B, and respectively acquiring moments corresponding to rising edge zero-crossing points of the abc three-phase values, namely t1, t2 and t3 moments;
step S3: under the condition of not considering clock errors and acquisition errors, the following judgment is carried out to obtain the phase relation among the phases:
judging whether T1= (T1+ N0.02 s) is true, if true, indicating that the phase a is the same as the phase A;
judging whether T1= (T2+ N0.02 s) is true, and if true, indicating that the phase a is the same as the phase B;
judging whether T1= (T3+ N0.02 s) is true, and if true, indicating that the phase a is the same as the phase C;
judging whether T2= (T1+ N0.02 s) is true, if true, indicating that the phase b is the same as the phase A;
judging whether T2= (T2+ N0.02 s) is true, if true, indicating that the phase B is the same as the phase B;
judging whether T2= (T3+ N0.02 s) is true, and if true, indicating that the phase b is the same as the phase C;
judging whether T3= (T1+ N0.02 s) is true, if true, indicating that the phase c is the same as the phase A;
judging whether T3= (T2+ N0.02 s) is true, and if true, indicating that the phase c is the same as the phase B;
judging whether T3= (T3+ N0.02 s) is true, and if true, indicating that the phase C is the same as the phase C;
wherein N is an integer.
Further, the method also includes step S4: in the case of considering only clock errors, the following calculations are made:
t1=(T1+N*0.02s)+△1；t1=(T2+N*0.02s)+△2；t1=(T3+N*0.02s)+△3；
t2=(T1+N*0.02s)+△4；t2=(T2+N*0.02s)+△5；t2=(T3+N*0.02s)+△6；
t3=(T1+N*0.02s)+△7；t3=(T2+N*0.02s)+△8；t3=(T3+N*0.02s)+△9；
wherein △ 1, △ 2, △ 3, △ 4, △ 5, △ 6, △ 7, △ 8 and △ 9 are time error values, and are all less than 0.02 s;
and performing difference on △ 1, △ 2, △ 3, △ 4, △ 5, △ 6, △ 7, △ 8 and △ 9 in pairs, and if three groups of difference results are zero and the rest difference results are not zero, Ti in the three groups is the same as that of Ti, wherein i =1,2 and 3.
Further, the method also includes step S5: taking into account clock errors and acquisition errors, the following calculations are performed:
t1=(T1+N*0.02s)+△1；t1=(T2+N*0.02s)+△2；t1=(T3+N*0.02s)+△3；
t2=(T1+N*0.02s)+△4；t2=(T2+N*0.02s)+△5；t2=(T3+N*0.02s)+△6；
t3=(T1+N*0.02s)+△7；t3=(T2+N*0.02s)+△8；t3=(T3+N*0.02s)+△9；
wherein △ 1, △ 2, △ 3, △ 4, △ 5, △ 6, △ 7, △ 8 and △ 9 are time error values and are all less than 0.02s, and the threshold g is set to be 0.02 s/5%;
making differences between △ 1, △ 2, △ 3, △ 4, △ 5, △ 6, △ 7, △ 8 and △ 9 in pairs, and if three groups of differences are smaller than a threshold g and the rest differences are larger than the threshold g, Ti in the three groups is the same as that of Ti, wherein i =1,2 and 3.
The invention also provides a remote phase checking instrument based on the charged indicator, which comprises an insulating shell, a battery module, an AD conversion module, an FPGA main chip, an internal clock module and a storage module, wherein the battery module, the AD conversion module, the FPGA main chip, the internal clock module and the storage module are arranged in the insulating shell;
the AD conversion module, the internal clock module, the battery module, the trigger key, the LCD display screen and the storage module are electrically connected with the FPGA main chip; the input end of the AD conversion module is electrically connected with the acquisition signal connecting hole and is used for receiving an input signal of a voltage signal acquisition terminal accessed from the acquisition signal connecting hole;
the storage module stores a program instruction, and when the FPGA main chip runs the program instruction, the nuclear phase method steps are realized.
Further, the chip model adopted by the internal clock module is HYM 8025.
Furthermore, the number of the acquisition signal connecting holes is 3, and different phases are respectively marked by different colors; the voltage signal acquisition terminal group comprises 3, and when the voltage signal acquisition terminal group is used, 3 of the voltage signal acquisition terminal group are correspondingly inserted into the signal acquisition connecting holes.
Furthermore, the voltage signal acquisition terminal adopts a banana head structure to ensure good contact with the acquisition signal connecting hole.
The present invention also provides a computer readable storage medium having stored thereon program instructions executable by a processor, the processor, when executing the program instructions, performing the nuclear phase method steps as described above.
Compared with the prior art, the invention has the following beneficial effects: the phase checking method adopts an internal algorithm to eliminate the influence caused by clock errors and acquisition errors, thereby reducing the number of satellite time setting modules, simplifying the modules, reducing the equipment cost, greatly facilitating the use and avoiding finding an open place to acquire satellite signals.
Drawings
Fig. 1 is a schematic circuit diagram according to an embodiment of the present invention.
Fig. 2 is a schematic structural diagram of an embodiment of the present invention.
Fig. 3 is a schematic diagram je illustrating the key and display according to an embodiment of the invention.
Fig. 4 is a diagram illustrating a phase checking result without considering clock errors according to an embodiment of the present invention.
FIG. 5 is a diagram illustrating a phase checking result considering only clock errors according to an embodiment of the present invention.
Fig. 6 is a schematic diagram of a phase checking result in consideration of a clock error and a sampling error according to an embodiment of the present invention.
Detailed Description
The invention is further explained below with reference to the drawings and the embodiments.
It should be noted that the following detailed description is exemplary and is intended to provide further explanation of the disclosure. Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs.
It is noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of example embodiments according to the present application. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, and it should be understood that when the terms "comprises" and/or "comprising" are used in this specification, they specify the presence of stated features, steps, operations, devices, components, and/or combinations thereof, unless the context clearly indicates otherwise.
The embodiment provides a remote phase checking method, which comprises the following steps:
step S1: acquiring voltage signals of two cycles of ABC three phases at a position A, and respectively acquiring corresponding moments of rising edge zero-crossing points of ABC three-phase values, namely T1 moments, T2 moments and T3 moments;
step S2: acquiring voltage signals of two cycles of an abc three-phase at a position B, and respectively acquiring moments corresponding to rising edge zero-crossing points of the abc three-phase values, namely t1, t2 and t3 moments;
step S3: under the condition of not considering clock errors and acquisition errors, the following judgment is carried out to obtain the phase relation among the phases:
judging whether T1= (T1+ N0.02 s) is true, if true, indicating that the phase a is the same as the phase A;
judging whether T1= (T2+ N0.02 s) is true, and if true, indicating that the phase a is the same as the phase B;
judging whether T1= (T3+ N0.02 s) is true, and if true, indicating that the phase a is the same as the phase C;
judging whether T2= (T1+ N0.02 s) is true, if true, indicating that the phase b is the same as the phase A;
judging whether T2= (T2+ N0.02 s) is true, if true, indicating that the phase B is the same as the phase B;
judging whether T2= (T3+ N0.02 s) is true, and if true, indicating that the phase b is the same as the phase C;
judging whether T3= (T1+ N0.02 s) is true, if true, indicating that the phase c is the same as the phase A;
judging whether T3= (T2+ N0.02 s) is true, and if true, indicating that the phase c is the same as the phase B;
judging whether T3= (T3+ N0.02 s) is true, and if true, indicating that the phase C is the same as the phase C;
in the formula, N is an integer to find the same phase, and the schematic diagram of the determination result is shown in fig. 4.
In this embodiment, the method further includes step S4: in the case of only considering the clock error, the clock error is when a high-precision crystal oscillator inside the device is used as a clock, and due to the existence of the temperature drift, the clock error is most likely to be caused in the using process, that is, the time difference between the second place and the first place calculated by the device is not consistent with the actual standard time, but for a 3-phase voltage waveform, the existing error value is consistent, so the following calculation is performed:
t1=(T1+N*0.02s)+△1；t1=(T2+N*0.02s)+△2；t1=(T3+N*0.02s)+△3；
t2=(T1+N*0.02s)+△4；t2=(T2+N*0.02s)+△5；t2=(T3+N*0.02s)+△6；
t3=(T1+N*0.02s)+△7；t3=(T2+N*0.02s)+△8；t3=(T3+N*0.02s)+△9；
wherein △ 1, △ 2, △ 3, △ 4, △ 5, △ 6, △ 7, △ 8 and △ 9 are time error values, and are all less than 0.02 s;
△ 1, △ 2, △ 03, △ 14, △ 25, △ 36, △ 47, △ 58, △ 69 are differenced in pairs, if there are three groups of differencing results which are zero and the rest differencing results are not zero, Ti in the three groups is in the same phase as Ti, wherein i =1,2,3, assuming that the results are △ 71- △ 5=0, △ 1- △ 9=0, △ 5- △ 9=0, i.e. △ 1= △ 5= △ 9 and the other time error values are different from 0, then it indicates that T1 and T1 are in phase, T2 and T2 are in phase, and T3 and T3 are in phase, because the time error values are equal and are also internal high-precision crystal oscillator temperature drift errors.
In this embodiment, the method further includes step S5: under the condition of considering clock errors and acquisition errors (the acquisition errors are errors existing in an acquisition loop and hardware in the process of acquiring 3-phase voltage signals by equipment, and the following algorithm is designed for the condition that the two errors exist at the same time), the following calculation is carried out:
t1=(T1+N*0.02s)+△1；t1=(T2+N*0.02s)+△2；t1=(T3+N*0.02s)+△3；
t2=(T1+N*0.02s)+△4；t2=(T2+N*0.02s)+△5；t2=(T3+N*0.02s)+△6；
t3=(T1+N*0.02s)+△7；t3=(T2+N*0.02s)+△8；t3=(T3+N*0.02s)+△9；
wherein △ 1, △ 2, △ 3, △ 4, △ 5, △ 6, △ 7, △ 8 and △ 9 are time error values and are all less than 0.02s, and the threshold g is set to be 0.02 s/5%;
△ 1, △ 2, △ 03, △ 14, △ 25, △ 36, △ 47, △ 8, △ 9 are differenced in pairs, if three groups of differenced results are smaller than a threshold g, and the other differenced results are larger than the threshold g, Ti in the three groups is the same phase as Ti, wherein i =1,2,3, and if △ 1- △ 5<0.02s 5%, △ 1- △ 9<0.02s 5%, △ 5- △ 9<0.02s 5%, and the other time error values are differenced results larger than 0.02s 5%, it is indicated that T1 and T1 are the same phase, T2 and T2 are the same phase, and T3 and T3 are the same phase.
As shown in fig. 1 and fig. 2, the present embodiment further provides a remote phase detector based on a charged indicator, which includes an insulating housing, a battery module, an AD conversion module, an FPGA main chip, an internal clock module, and a storage module, which are disposed in the insulating housing, and further includes an LCD display screen, a trigger button, and a signal collecting connection hole, which are disposed outside the insulating housing;
the AD conversion module, the internal clock module, the battery module, the trigger key, the LCD display screen and the storage module are electrically connected with the FPGA main chip; the input end of the AD conversion module is electrically connected with the acquisition signal connecting hole and is used for receiving an input signal of a voltage signal acquisition terminal accessed from the acquisition signal connecting hole;
the storage module stores a program instruction, and when the FPGA main chip runs the program instruction, the nuclear phase method steps are realized.
Preferably, the voltage signal acquisition terminal is inserted into a nuclear phase hole (acquisition signal connection hole) of the electric indicator to acquire the voltage phase sequence information of the current nuclear phase point, the voltage signal acquisition terminals form a group, and the group is inserted into the nuclear phase hole of the electric indicator during use, wherein each voltage signal acquisition terminal adopts a banana head design mode, so that good contact with a metal hole of the electric indicator can be ensured, and in addition, the voltage signal acquisition terminals adopt yellow green red 3 different phase color marks to ensure correct hole position insertion.
Preferably, the AD conversion module is used for converting an analog signal into a digital signal, the AD conversion module is used for receiving the analog signal from the voltage signal acquisition terminal, the input range value of the analog signal is required to reach 0 ~ 380V, and the converted digital signal is transmitted to the FPGA main chip.
Preferably, the whole phase checking instrument adopts a battery module to supply power, does not need an external power supply, and can be charged when the electric quantity is insufficient. This nuclear phase appearance is provided with trigger button and LCD and shows, and wherein trigger button includes: the keys of up, down, left, right, affirmation, cancel and on/off are matched with the trigger key by the LCD display to provide a friendly man-machine interface. This nuclear phase appearance adopts FPGA main chip as core processor, and the FPGA chip has extremely strong data parallel processing ability, can accomplish the parallel processing of multichannel data, accords with the data required precision of novel long-range nuclear phase ware to 3 looks voltage sampling.
In this embodiment, the internal clock module adopts a chip model of HYM 8025.
In this embodiment, the number of the acquisition signal connection holes includes 3, and different phases are respectively identified by different colors; the voltage signal acquisition terminal group comprises 3, and when the voltage signal acquisition terminal group is used, 3 of the voltage signal acquisition terminal group are correspondingly inserted into the signal acquisition connecting holes.
In this embodiment, the voltage signal acquisition terminal adopts a banana head structure for ensuring good contact with the acquisition signal connection hole.
The present embodiment also provides a computer readable storage medium having stored thereon program instructions executable by a processor, the processor implementing the nuclear phase method steps as described above when executing the program instructions.
Particularly, the key and the display interface are as shown in fig. 3, the operation of the nuclear phase instrument of the embodiment can be completed by only one person, and the specific steps are as follows:
(1) after reaching the first nuclear phase point, the power supply of the equipment is turned on by triggering the on/off of the key.
(2) At a core phase point at the first position, 3 contact heads of a voltage signal acquisition terminal are correspondingly connected with 3 core phase holes of a charge indicator, and the function of receiving voltage waveform at the position 1 is selected by triggering the functions of 'up', 'down', 'left', 'right', 'determining' and 'canceling' in a key, so that a 3-phase voltage signal at the first position is correctly acquired.
(3) And (4) evacuating the place at the first place, and keeping the equipment continuously running without shutting down the equipment after evacuation.
(4) At a core phase point B, 3 contact heads of a voltage signal acquisition terminal are correspondingly connected with 3 core phase holes of the charge indicator, and the function of receiving voltage waveform at the site 2 is selected by triggering the functions of 'up', 'down', 'left', 'right', 'determining' and 'canceling' in a key, so that a 3-phase voltage signal at the B site is correctly acquired.
(5) After voltage signals of the first place and the second place are acquired, the function of phase comparison is selected by triggering the upper, the lower, the left, the right, the confirmation and the cancellation in the keys, the phase conditions of the first place and the second place can be automatically acquired through an internal algorithm of the phase checking instrument, and the display result is displayed on an LCD.
(6) The 'storage' function is selected by triggering 'up', 'down', 'left', 'right', 'determination' and 'cancellation' in the key, the phase checking result is stored in the internal memory of the equipment, and the subsequent checking can be carried out through the 'checking' function.
The nuclear phase instrument of the embodiment adopts the voltage signal acquisition terminal to acquire the voltage waveform at the nuclear phase point, and acquires the 3-phase voltage waveform at one time. Meanwhile, because the internal clock provides a clock signal for the measurement process, the influence caused by clock errors and acquisition errors is eliminated through an internal algorithm. Simultaneously, the nuclear phase appearance of this embodiment passes through insulating casing encapsulation, avoids taking place the electric shock accident, and uses the battery module design to make equipment more small and exquisite, portable uses. In addition, the nuclear phase instrument of this embodiment obtains voltage signal through the electrified indicator in the use, and the voltage level is 380V and below, belongs to the low pressure operation, and the security level is high, and only need alone accomplish signal acquisition to two nuclear phase points respectively and can learn the phase place condition automatically, convenient and fast.
The foregoing is directed to preferred embodiments of the present invention, other and further embodiments of the invention may be devised without departing from the basic scope thereof, and the scope thereof is determined by the claims that follow. However, any simple modification, equivalent change and modification of the above embodiments according to the technical essence of the present invention are within the protection scope of the technical solution of the present invention.
Claims (8)
1. A remote nuclear phase method, comprising the steps of:
step S1: acquiring voltage signals of two cycles of ABC three phases at a position A, and respectively acquiring corresponding moments of rising edge zero-crossing points of ABC three-phase values, namely T1 moments, T2 moments and T3 moments;
step S2: acquiring voltage signals of two cycles of an abc three-phase at a position B, and respectively acquiring moments corresponding to rising edge zero-crossing points of the abc three-phase values, namely t1, t2 and t3 moments;
step S3: under the condition of not considering clock errors and acquisition errors, the following judgment is carried out to obtain the phase relation among the phases:
judging whether T1= (T1+ N0.02 s) is true, if true, indicating that the phase a is the same as the phase A;
judging whether T1= (T2+ N0.02 s) is true, and if true, indicating that the phase a is the same as the phase B;
judging whether T1= (T3+ N0.02 s) is true, and if true, indicating that the phase a is the same as the phase C;
judging whether T2= (T1+ N0.02 s) is true, if true, indicating that the phase b is the same as the phase A;
judging whether T2= (T2+ N0.02 s) is true, if true, indicating that the phase B is the same as the phase B;
judging whether T2= (T3+ N0.02 s) is true, and if true, indicating that the phase b is the same as the phase C;
judging whether T3= (T1+ N0.02 s) is true, if true, indicating that the phase c is the same as the phase A;
judging whether T3= (T2+ N0.02 s) is true, and if true, indicating that the phase c is the same as the phase B;
judging whether T3= (T3+ N0.02 s) is true, and if true, indicating that the phase C is the same as the phase C;
wherein N is an integer.
2. The remote nuclear phase method according to claim 1, further comprising step S4: in the case of considering only clock errors, the following calculations are made:
t1=(T1+N*0.02s)+△1；t1=(T2+N*0.02s)+△2；t1=(T3+N*0.02s)+△3；
t2=(T1+N*0.02s)+△4；t2=(T2+N*0.02s)+△5；t2=(T3+N*0.02s)+△6；
t3=(T1+N*0.02s)+△7；t3=(T2+N*0.02s)+△8；t3=(T3+N*0.02s)+△9；
wherein △ 1, △ 2, △ 3, △ 4, △ 5, △ 6, △ 7, △ 8 and △ 9 are time error values, and are all less than 0.02 s;
and performing difference on △ 1, △ 2, △ 3, △ 4, △ 5, △ 6, △ 7, △ 8 and △ 9 in pairs, and if three groups of difference results are zero and the rest difference results are not zero, Ti in the three groups is the same as that of Ti, wherein i =1,2 and 3.
3. The remote nuclear phase method according to claim 1, further comprising step S5: taking into account clock errors and acquisition errors, the following calculations are performed:
t1=(T1+N*0.02s)+△1；t1=(T2+N*0.02s)+△2；t1=(T3+N*0.02s)+△3；
t2=(T1+N*0.02s)+△4；t2=(T2+N*0.02s)+△5；t2=(T3+N*0.02s)+△6；
t3=(T1+N*0.02s)+△7；t3=(T2+N*0.02s)+△8；t3=(T3+N*0.02s)+△9；
wherein △ 1, △ 2, △ 3, △ 4, △ 5, △ 6, △ 7, △ 8 and △ 9 are time error values and are all less than 0.02s, and the threshold g is set to be 0.02 s/5%;
making differences between △ 1, △ 2, △ 3, △ 4, △ 5, △ 6, △ 7, △ 8 and △ 9 in pairs, and if three groups of differences are smaller than a threshold g and the rest differences are larger than the threshold g, Ti in the three groups is the same as that of Ti, wherein i =1,2 and 3.
4. A remote phase checking instrument based on a charged indicator is characterized by comprising an insulating shell, a battery module, an AD conversion module, an FPGA main chip, an internal clock module and a storage module, wherein the battery module, the AD conversion module, the FPGA main chip, the internal clock module and the storage module are arranged in the insulating shell;
the AD conversion module, the internal clock module, the battery module, the trigger key, the LCD display screen and the storage module are electrically connected with the FPGA main chip; the input end of the AD conversion module is electrically connected with the acquisition signal connecting hole and is used for receiving an input signal of a voltage signal acquisition terminal accessed from the acquisition signal connecting hole;
the memory module has stored therein program instructions which, when executed by the FPGA master chip, carry out the method steps of any one of claims 1 to 3.
5. The remote phase detector based on the charged indicator as claimed in claim 4, wherein the internal clock module adopts a chip model of HYM 8025.
6. The remote phase checking instrument based on the charged indicator as claimed in claim 4, wherein the number of the collected signal connecting holes comprises 3, and different phases are respectively marked by different colors; the voltage signal acquisition terminal group comprises 3, and when the voltage signal acquisition terminal group is used, 3 of the voltage signal acquisition terminal group are correspondingly inserted into the signal acquisition connecting holes.
7. The remote phase checking instrument based on the charged indicator as claimed in claim 6, wherein the voltage signal collecting terminal is of a banana head structure to ensure good contact with the signal collecting connection hole.
8. A computer-readable storage medium, on which program instructions are stored that can be executed by a processor, characterized in that the processor, when executing the program instructions, carries out the method steps according to any of claims 1-3.
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