CN110719100A - Fractional frequency all-digital phase-locked loop and control method thereof - Google Patents
Fractional frequency all-digital phase-locked loop and control method thereof Download PDFInfo
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- H—ELECTRICITY
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- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
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- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
- H03L7/0991—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator being a digital oscillator, e.g. composed of a fixed oscillator followed by a variable frequency divider
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Abstract
The invention provides a fractional frequency all-digital phase-locked loop and a control method of the fractional frequency all-digital phase-locked loop. The method comprises the following steps: s1, the fractional frequency controller generates a delay control word, a frequency dividing ratio control word, an integer frequency control word and a fractional frequency control word according to the external fractional frequency control word; s2, the clock generation and control circuit generates a clock signal ckr according to the reference clock and the frequency control word; s3, generating a low-frequency clock signal by the digital time converter according to the ckr and the delay control word; s4, the feedback signal generating circuit outputs a feedback signal fb according to the high-frequency clock signal ckv generated by the frequency dividing ratio control digital and controlled oscillator; s5, the phase discriminator generates phase error digital signals phe of ckr and fb; s6, the auxiliary frequency locking loop outputs a control signal ftl according to the integer frequency control word, the fractional frequency control word and the low frequency clock signal, and the numerical control oscillator updates ckv according to the sum of ftl and phe.
Description
Technical Field
The invention relates to the technical field of integrated circuit design, in particular to a fractional frequency all-digital phase-locked loop and a control method thereof.
Background
The all-digital phase-locked loop adopts a digital circuit to realize loop control, so that the all-digital phase-locked loop has high design and realization flexibility, is convenient to integrate with other systems on a chip, can obtain better performance along with the development of an integrated circuit manufacturing process, and has very wide application. However, in the fractional frequency all-digital phase-locked loop with the traditional structure, due to the existence of fractional quantization error, the phase error change range between clock signals input by the phase discriminator is very large, and the requirements on the design complexity, power consumption and error control of the time-to-digital converter are very high. In order to reduce the input phase error range of the time-to-digital converter, a delay can be added on the reference clock or the feedback clock to compensate the delay of the fractional quantization error. The design difficulty of the digital-to-time converter is lower than that of a time-to-digital converter, high precision is easy to realize, and the method is widely applied to a fractional digital phase-locked loop.
The control of delay compensation is typically based on a delta-sigma modulator (DSM) and a digital-to-time converter (DTC), where the output delay time range of the digital-to-time converter is typically determined by the structure of the delta-sigma modulator. If a higher order modulator is used to improve randomness and suppress the fractional spurs at the output of the pll due to quantization errors and digital-to-time converter non-linearities, the delay time range of the output of the dac will also increase. Typically, if a first order modulator is used, the time-to-digital modulator requires an output delay time in the range of Tckv, where Tckv is the target period of the oscillator output clock; if a second order modulator is used, the output delay time range becomes (2 Tckv). The larger output delay time range puts higher requirements on the design difficulty, power consumption, area, linearity and noise of the digital-to-time converter, and limits the energy efficiency and performance of the phase-locked loop.
In order to alleviate the design requirement of the output delay time range on the digital-to-time converter, a circuit designer usually has to adopt a compromise method, such as adopting a modulator with a low order number, even not using the modulator, and sacrificing the fractional spurious performance; a digital time converter with higher resolution is used so as to obtain output delay time in a larger range, and the linearity is sacrificed to cause a serious fractional spurious problem; jitter (diter) is added to the output of the digital-to-time converter with poor linearity to convert the fractional spur of a particular frequency into noise distributed over the entire spectral range, which degrades the noise performance of the phase-locked loop. Recent researchers have reduced the required delay time range of the digital-to-time converter output by using the clock falling edge, but this method requires the clock signal to strictly satisfy 50% duty cycle, so a precise duty cycle correction circuit is required, the design complexity and power consumption are increased, and extra phase noise or error may be introduced into the loops operating simultaneously in the phase-locked loop, which results in unstable loop operation.
Disclosure of Invention
The invention aims to provide a fractional frequency all-digital phase-locked loop and a control method thereof, aiming at the requirement of the traditional fractional frequency all-digital phase-locked loop on the output delay time range of a digital time converter, and controlling the fractional frequency all-digital phase-locked loop by using the digital time converter in a narrow range according to the self working characteristic of the phase-locked loop. The present invention reduces the digital-to-time converter output delay range to a single Tckv (dco target output clock period) without regard to the order of the particular modulator by adjusting the digital-to-time converter input delay control word (dcw) and the phase locked loop frequency control word (fcw _ frac, fcw _ int).
In order to achieve the above object, the present invention provides a fractional-frequency all-digital phase-locked loop, comprising:
the clock generation and control circuit CTRL is used for generating a clock signal ckr required by the correct work of the phase-locked loop according to an input reference clock ref, an integer frequency control word fcw _ int and a fractional frequency control word fcw _ frac;
a fractional frequency controller FRAC CTRL for generating a delay control word dcw, a division ratio control word div, an integer frequency control word fcw _ int, and a fractional frequency control word fcw _ FRAC from an input outer fractional frequency control word fcwin _ FRAC;
a digital time converter DTC, an input end of which is connected to an output end of the clock generation and control circuit CTRL and an output end of the fractional frequency controller FRAC CTRL, and configured to generate a low-frequency clock signal ckr _ dly according to the clock signal ckr and the delay control word dcw;
a digitally controlled oscillator DCO for generating a high frequency clock signal ckv;
a feedback signal generating circuit FB GEN, the input end of which is connected to the output end of the digital controlled oscillator DCO and the output end of the fractional frequency controller FRAC CTRL, and configured to generate a feedback signal FB carrying ckv phase information according to the division ratio control word div;
the input end of the phase discriminator PD is connected with the output end of a digital time converter DTC, the output end of a feedback signal generating circuit FB GEN and the output end of a digital controlled oscillator DCO, and is used for generating a phase error digital signal phe of the low-frequency clock signal ckr and the feedback signal FB;
an auxiliary frequency locking loop FTL, an input end of which is connected to the digital-to-time converter DTC and the fractional-frequency controller FRAC CTRL, and outputs a control signal FTL according to the integer-frequency control word fcw _ int, the fractional-frequency control word fcw _ FRAC, and the low-frequency clock signal ckr _ dly;
the input end of the DCO is connected to the output end of the FTL and the output end of the phase detector PD, and adjusts the output high-frequency clock signal ckv according to the phase error digital signal phe and the control signal FTL.
The fractional frequency all-digital phase-locked loop further comprises: the input end of the digital loop filter DLF is connected with the output end of the phase discriminator PD and the output end of the numerical control oscillator DCO; a digital loop filter DLF filters out unnecessary frequency components in the phase error digital signal phe to obtain a digital signal otw 0; the DCO outputs the high frequency clock signal ckv according to the summation of the control signal ftl and the digital signal otw 0.
The fractional frequency controller FRAC CTRL comprises:
a delta-sigma modulator DSM, configured to randomize an input outer digital frequency control word fcwin _ frac, and generate a modulation signal dsmout according to the randomized fcwin _ frac;
a subtractor SUB, an input end of which is connected to an output end of the Δ Σ modulator, for calculating a difference between the external fractional-frequency control word fcwin _ frac and the modulation signal dsmout, where the difference is a frequency quantization error value frac _ q;
the input end of the accumulator ACC is connected with the output end of the subtracter and used for accumulating the frequency quantization error value frac _ q output by the subtracter to generate a phase error value frac _ qacc;
a complementation unit MOD having an input end connected to an output end of the accumulator ACC, and configured to solve the integer quotient frac _ quo and the remainder frac _ res of the phase error value frac _ qacc; and the modulus of the complementation unit is a delay control word corresponding to the target output clock period of the digital controlled oscillator DCO.
The fractional-frequency controller further comprises a calculation unit CALC; the input end of the computing unit CALC is connected with the output end of the complementation unit, and the fractional frequency control word fcw _ frac is generated by computing according to the integer quotient frac _ quo and the input outer fractional frequency control word fcwin _ frac.
The fractional-frequency controller FRAC CTRL further comprises a Gain correction unit Gain Corrector and a multiplier MX; the Gain Corrector is used for generating a Gain coefficient dcw _ Gain; the input end of the multiplier MX is connected with the output end of the Gain Corrector and the output end of the complementation unit MOD, and the multiplier MX generates a delay control word dcw according to a Gain coefficient dcw _ Gain and a remainder frac _ res; and adjusting the weight of the remainder frac _ res by the gain coefficient dcw _ gain to make the conversion gain of the remainder frac _ res consistent with that of the digital time converter DTC, and meeting the requirement that the maximum output value 2^ W-1 of the frac _ res corresponds to the target output clock period of the digital controlled oscillator DCO, wherein W is the word length of the external fractional frequency control word fcwin _ frac.
The fractional-frequency controller FRAC CTRL further comprises a word length adjustment Δ Σ modulator bit width DSM, the input of which is connected to the output of the multiplier, for adjusting the word length of the control word dcw to a set length.
The fractional-frequency controller FRAC CTRL further comprises a first adder ADD1, an input terminal of which is connected to the output terminal of the clock generation and control circuit CTRL, an output terminal of the fractional-frequency controller FRAC CTRL, and an output terminal of which is connected to the feedback signal generation circuit FB GEN; the modulation signal dsmout is summed with the external integer frequency control word fcwin int by means of said first adder ADD1 to generate the division ratio control word div of the feedback signal generating circuit FB GEN.
The fractional-frequency controller FRAC CTRL further comprises a second adder ADD2, the input of which is connected to the output of the word-length-adjusting delta-sigma modulator bit width DSM, and dcw is summed with 2^ W by means of said second adder ADD2, ensuring that dcw is non-negative.
The invention discloses a control method of a fractional frequency all-digital phase-locked loop, which is realized by the fractional frequency all-digital phase-locked loop and comprises the following steps:
s1, the fractional frequency controller FRAC CTRL generates a delay control word dcw, a division ratio control word div, an integer frequency control word fcw _ int, and a fractional frequency control word fcw _ FRAC from the input outer fractional frequency control word fcwin _ FRAC;
s2, the clock generation and control circuit CTRL generates a clock signal ckr required by the correct work of the phase-locked loop according to the input reference clock ref and the frequency control word fcw;
s3, generating a low-frequency clock signal ckr _ dly by the digital time converter DTC according to the clock signal ckr and the delay control word dcw;
s4, the feedback signal generating circuit FB GEN outputs a feedback signal FB carrying ckv phase information according to the frequency dividing ratio control word div and the high-frequency clock signal ckv generated by the numerical control oscillator;
s5, the phase discriminator PD generates a phase error digital signal phe of the low-frequency clock signal ckr and the feedback signal fb;
s6, the auxiliary frequency locking loop outputs a control signal ftl according to the integer frequency control word fcw _ int, the fraction frequency control word fcw _ frac and the low-frequency clock signal ckr _ dly; the dco updates the high frequency clock signal based on the addition of the output control signal ftl and the phase error digital signal phe.
The step S1 includes:
s11, generating a modulation signal dsmout through the delta-sigma modulator DSM;
s12, adjusting the weight of dsmout to dsmout & 2^ W according to the word length W of fcwin _ frac, and obtaining the difference value of the external fractional frequency control word fcwin _ frac and the modulation signal dsmout after adjusting the weight through a subtracter SUB, wherein the difference value is a frequency quantization error value frac _ q & ltfcwin _ frac-dsmout & 2^ W;
s13, accumulating the frequency quantization error value frac _ q by an accumulator ACC to generate a phase error value frac _ qacc;
s14, generating a Gain coefficient dcw _ Gain through a Gain Corrector; performing complementation operation on the phase error value frac _ qacc, wherein the modulus is a delay control word corresponding to the target output clock period of the digital controlled oscillator DCO; multiplying the remainder frac _ res of the complementation operation and the gain coefficient dcw _ gain to obtain a delay control word dcw, and ensuring that the dcw is a non-negative number;
s15, calculating a fractional frequency control word fcw _ frac according to the integer quotient frac _ quo of the complementation operation; if the whole quotient frac _ quo is 0, fcw _ frac ═ fcwin _ frac; if the whole quotient is not 0, the fractional-frequency control word fcw _ frac (t) in the current period fcwin _ frac (t) -frac _ quo (t), the fractional-frequency control word fcw _ frac (t +1) in the next period fcwin _ frac (t +1) + frac _ quo (t); where t represents the period.
Compared with the prior art, the invention has the advantages that: the invention can reduce the delay range of the low-frequency clock signal ckr _ dly output by the digital time converter to a single Tckv only by adjusting and adjusting the delay control word dcw input to the digital time converter, the fractional frequency control word fcw _ frac and the integer frequency control word fcw _ int input to the auxiliary frequency locking loop through the fractional frequency controller without considering the order of the signal modulator for controlling the delay control word, thereby reducing the requirement of the fractional frequency phase-locked loop on the output delay time range of the digital time converter and further reducing the design difficulty and the power consumption of the digital time converter. The invention is realized by using a digital logic circuit for operation, has simple theory, requires very little extra hardware overhead and is easy to realize.
Drawings
In order to more clearly illustrate the technical solution of the present invention, the drawings used in the description will be briefly introduced, and it is obvious that the drawings in the following description are an embodiment of the present invention, and other drawings can be obtained by those skilled in the art without creative efforts according to the drawings:
fig. 1 is a schematic structural diagram of a fractional-frequency all-digital phase-locked loop according to the present invention.
Fig. 2 is a schematic diagram of the implementation principle of the fractional-frequency all-digital phase-locked loop according to the present invention.
Fig. 3 is a schematic diagram of a fractional-n controller according to the present invention.
Fig. 4 is a block diagram of an implementation of a fractional frequency controller in an embodiment of the invention.
Fig. 5 is a timing diagram of various signals internally generated by the fractional frequency controller according to an embodiment of the present invention.
Fig. 6A is a schematic diagram of a relationship between a delay control word and a fractional-frequency control word of a fractional-frequency all-digital phase-locked loop in the prior art.
Fig. 6B is a schematic diagram of the relationship between the delay control word and the fractional-frequency control word of the fractional-frequency all-digital phase-locked loop according to the present invention.
Fig. 7 is a flowchart illustrating the operation steps of the fractional-n adpll according to the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The invention provides a fractional frequency all-digital phase-locked loop, as shown in fig. 1, comprising:
the clock generation and control circuit CTRL is used for generating a clock signal ckr required by the correct work of the phase-locked loop according to an input reference clock ref, an integer frequency control word fcw _ int and a fractional frequency control word fcw _ frac;
a fractional frequency controller FRAC CTRL for generating a delay control word dcw, a division ratio control word div, an integer frequency control word fcw _ int, and a fractional frequency control word fcw _ FRAC from an input outer fractional frequency control word fcwin _ FRAC;
a digital time converter DTC, an input end of which is connected to an output end of the clock generation and control circuit CTRL and an output end of the fractional frequency controller FRAC CTRL, and configured to generate a low-frequency clock signal ckr _ dly according to the clock signal ckr and the delay control word dcw;
a digitally controlled oscillator DCO for generating a high frequency clock signal ckv;
a feedback signal generating circuit FB GEN, the input end of which is connected to the output end of the digital controlled oscillator DCO and the output end of the fractional frequency controller FRAC CTRL, and configured to generate a feedback signal FB carrying ckv phase information according to the division ratio control word div; in the embodiment of the present invention, a conventional frequency divider may be used as the feedback signal generating circuit FB GEN, i.e., the feedback signal FB is the output of the frequency divider. In another embodiment of the present invention, the feedback signal FB is obtained by using a sub-sampling manner, i.e. a snapshot circuit or a sub-sampling flip-flop is used as the feedback signal generating circuit FB GEN.
The input end of the phase discriminator PD is connected with the output end of a digital time converter DTC, the output end of a feedback signal generating circuit FB GEN and the output end of a digital controlled oscillator DCO, and is used for generating a phase error digital signal phe of the low-frequency clock signal ckr and the feedback signal FB;
an auxiliary frequency locking loop FTL, an input end of which is connected to the digital-to-time converter DTC and the fractional-frequency controller FRAC CTRL, and outputs a control signal FTL according to the integer-frequency control word fcw _ int, the fractional-frequency control word fcw _ FRAC, and the low-frequency clock signal ckr _ dly;
the input end of the DCO is connected to the output end of the FTL and the output end of the phase detector PD, and adjusts the output high-frequency clock signal ckv according to the phase error digital signal phe and the control signal FTL.
The fractional frequency all-digital phase-locked loop further comprises: the input end of the digital loop filter DLF is connected with the output end of the phase discriminator PD and the output end of the numerical control oscillator DCO; a digital loop filter DLF filters out unnecessary frequency components in the phase error digital signal phe to obtain a digital signal otw 0; the DCO outputs the high frequency clock signal ckv according to the summation of the control signal ftl and the digital signal otw 0.
As shown in fig. 3, the fractional-frequency controller FRAC CTRL comprises: the delta-sigma modulator DSM comprises a subtracter SUB, an accumulator ACC, a complementation unit MOD, a calculation unit CALC, a Gain correction unit Gain Corrector, a multiplier MX, a word length adjustment delta-sigma modulator bit width DSM, a first adder ADD1 and a second adder ADD 2.
The delta-sigma modulator DSM is configured to randomize the input outer digital frequency control word fcwin _ frac and generate a modulated signal dsmout according to the randomized fcwin _ frac;
the input end of the subtractor SUB is connected with the output end of the delta-sigma modulator and is used for calculating a difference value between the external fractional-frequency control word fcwin _ frac and the modulation signal dsmout, wherein the difference value is a frequency quantization error value frac _ q;
the input end of the accumulator ACC is connected with the output end of the subtracter SUB and is used for accumulating a frequency quantization error value frac _ q output by the subtracter to generate a phase error value frac _ qacc;
the input end of the complementation unit MOD is connected to the output end of the accumulator ACC, and is used for solving the integer quotient frac _ quo and the remainder frac _ res of the phase error value frac _ qacc; and the modulus of the complementation unit is a delay control word corresponding to the target output clock period of the digital controlled oscillator DCO. The complementation unit is not limited to general division or complementation operation in specific implementation, and can also be implemented by allocating logic operation based on shift and digit.
The input end of the computing unit CALC is connected with the output end of the complementation unit, and the fractional frequency control word fcw _ frac is generated by computing according to the integer quotient frac _ quo and the input outer fractional frequency control word fcwin _ frac.
The Gain Corrector is used for generating a Gain coefficient dcw _ Gain; the input end of the multiplier is connected with the output end of the Gain Corrector and the output end of the complementation unit MOD, and the multiplier generates a delay control word dcw according to a Gain coefficient dcw _ Gain and a remainder frac _ res; and adjusting the weight of the remainder frac _ res by the gain coefficient dcw _ gain to make the conversion gain of the remainder frac _ res consistent with that of the digital time converter DTC, and meeting the requirement that the maximum output value 2^ W-1 of the frac _ res corresponds to the target output clock period of the digital controlled oscillator DCO, wherein W is the word length of the external fractional frequency control word fcwin _ frac.
The input of the word length adjustment delta sigma modulator bit width DSM is connected to the output of the multiplier for adjusting the word length of the control word dcw to the actual control word length of the digital time converter DTC, so that the fractional frequency controller can also be used for digital time converters with control word lengths shorter than W.
The input end of the first adder is connected with the output end of the clock generation and control circuit CTRL and the output end of the fractional frequency controller FRAC CTRL, and the output end of the first adder is connected with the feedback signal generation circuit FB GEN; and adding the modulation signal dsmout and the external integer frequency control word fcwin _ int by the adder to generate the frequency division ratio control word div of the feedback signal generation circuit FB GEN.
In the first embodiment of the present invention, the input terminal of the second adder is connected to the output terminal of the word length adjusting Δ Σ modulator bit width DSM, and dcw is added to 2^ W by the second adder, so that dcw is guaranteed to be a non-negative number.
In the second embodiment of the present invention, the second adder may be further disposed between the accumulator ACC and the complementation unit MOD, and the dcw is guaranteed to be a non-negative number by adding frac _ qacc and 2^ W.
A control method of fractional frequency all-digital phase-locked loop, which is implemented by the fractional frequency all-digital phase-locked loop of the present invention, as shown in fig. 7, comprises the steps of:
s1, the fractional frequency controller FRAC CTRL generates a delay control word dcw, a division ratio control word div, an integer frequency control word fcw _ int, and a fractional frequency control word fcw _ FRAC from the input outer fractional frequency control word fcwin _ FRAC;
s2, the clock generation and control circuit CTRL generates a clock signal ckr required by the correct work of the phase-locked loop according to the input reference clock ref and the frequency control word fcw;
s3, generating a low-frequency clock signal ckr _ dly by the digital time converter DTC according to the clock signal ckr and the delay control word dcw;
s4, the feedback signal generating circuit FB GEN outputs a feedback signal FB carrying ckv phase information according to the frequency dividing ratio control word div and the high-frequency clock signal ckv generated by the numerical control oscillator;
s5, the phase discriminator PD generates a phase error digital signal phe of the low-frequency clock signal ckr and the feedback signal fb;
s6, the auxiliary frequency locking loop outputs a control signal ftl according to the integer frequency control word fcw _ int, the fraction frequency control word fcw _ frac and the low-frequency clock signal ckr _ dly; the dco updates the high frequency clock signal based on the addition of the output control signal ftl and the phase error digital signal phe.
The step S1 includes:
s11, generating a modulation signal dsmout through the delta-sigma modulator DSM;
s12, adjusting the weight of dsmout to dsmout & 2^ W according to the word length W of fcwin _ frac, and obtaining the difference value between the external fractional frequency control word fcwin _ frac and dsmout & 2^ W through a subtracter SUB, wherein the difference value is a frequency quantization error value frac _ q & ltfcwin _ frac-dsmout & 2^ W;
s13, accumulating the frequency quantization error value frac _ q by an accumulator ACC to generate a phase error value frac _ qacc;
s14, generating a Gain coefficient dcw _ Gain through a Gain Corrector; performing complementation operation on the phase error value frac _ qacc, wherein the modulus is a delay control word corresponding to the target output clock period of the digital controlled oscillator DCO; multiplying the remainder frac _ res of the complementation operation and the gain coefficient dcw _ gain to obtain a delay control word dcw, and ensuring that the dcw is a non-negative number;
s15, calculating a fractional frequency control word fcw _ frac according to the integer quotient frac _ quo of the complementation operation; if the whole quotient frac _ quo is 0, fcw _ frac ═ fcwin _ frac; if the whole quotient is not 0, the fractional-frequency control word fcw _ frac (t) in the current period fcwin _ frac (t) -frac _ quo (t), the fractional-frequency control word fcw _ frac (t +1) in the next period fcwin _ frac (t +1) + frac _ quo (t); where t represents the period.
As shown in fig. 2, the fractional-frequency adpll of the present invention is implemented by comparing the count ckv _ cnt of the DCO output ckv in one reference clock cycle with the frequency control word fcw of 2.5, and adjusting the frequency fckv of the DCO according to the difference between ckv _ cnt and fcw, that is, the target frequency fckv of 2.5 fckr. As shown in fig. 2, the error of the count ckv _ cnt and the frequency control word fcw is frac _ q. In cycle 1 and cycle 3, the ckr rising edge is aligned with the rising edge of ckv, when the phase error is 0; in cycle 2, the ckr rising edge is aligned with the falling edge of ckv, at which time the phase error is 0.5Tckv, where Tckv is the oscillator output clock period. It can be seen that, after the target frequency is locked, the residual phase error is not 0, and the phase-locked loop is not stable in locking. If the frequency error frac _ q is integrated into the phase dcw and the delay ckr is used to ckr _ dly, it can be seen that after the target frequency is locked, the reference ckr _ dly is aligned with the rising edge of the oscillator output ckv in each cycle, the remaining phase error is 0, and the phase-locked loop can operate stably.
In a first embodiment of the invention, as shown in fig. 4, the fractional-frequency controller FRAC CTRL is implemented in the form of: the order of the delta-sigma modulator DSM in the fractional-frequency controller FRAC CTRL is 2. The word length of input fcwin _ frac of the delta-sigma modulator DSM is W, the word length of output modulation signal dsmout is 3, dsmout is adjusted according to W to obtain dsmout & 2^ W, and the adjustment weight of dsmout is achieved through shifting. The subtractor outputs frac _ q ═ fcwin _ frac-dsmout · 2^ W. The accumulator input is frac _ q, the word size is W +2, the accumulator output is frac _ qacc, the word size is W + 2. The input of the complementation unit MOD is frac _ qacc, the complementation unit flags frac _ qacc to be less than 0 by the generated flag bit frac _ flag, if frac _ qacc is less than 0, frac _ flag is 1, the original delay control word dcw0 is frac _ qacc +2^ W is output, and if frac _ qacc is greater than or equal to 0, frac _ flag is 0, the original delay control word dcw0 is frac _ qacc is output. In this implementation, the equivalent function of the modulo unit is to complement frac _ qacc +2^ W, with the modulus 2^ W. The frac _ flag in fig. 4 represents the whole quotient frac _ quo, and dcw0 represents the remainder frac _ res. And outputting a fractional frequency control word fcw _ frac ═ fcwin _ frac-frac _ flag + frac _ flag _ last, wherein frac _ flag _ last is the value of frac _ flag in the last period. In fig. 4, the gain correction unit GainCorrector is configured to adjust the weight of the output frac _ res of the complementation unit according to the target output clock frequency of the DCO, so that dcw is dcw0 · dcw _ gain ═ frac _ res · dcw _ gain, and the dcw is guaranteed to be consistent with the conversion gain of the digital-to-time converter DTC, even if the maximum output value of the frac _ res corresponds to one clock cycle of the target output of the DCO.
FIG. 5 is a timing diagram of various signals internally generated by the fractional frequency controller according to an embodiment of the present invention. The specific implementation manner of performing the modulo operation on the phase error frac _ qacc is as follows: if frac _ qacc is less than 0, frac _ flag is equal to 1, and a delay control word dcw is output, wherein frac _ qacc +2^ W; if frac _ qacc is greater than or equal to 0, frac _ flag is equal to 0, and the delay control word dcw is equal to frac _ qacc. And outputting a fractional frequency control word fcw _ frac ═ fcwin _ frac-frac _ flag + frac _ flag _ last, wherein frac _ flag _ last is the value of frac _ flag in the last period.
Fig. 6A is a schematic diagram of a relation between a delay control word and a fractional frequency control word of a fractional frequency all-digital phase-locked loop in the prior art, and fig. 6B is a schematic diagram of a relation between a delay control word and a fractional frequency control word of a fractional frequency all-digital phase-locked loop in the prior art, it can be seen that, when the fractional frequency all-digital phase-locked loop in the prior art is compared with the fractional frequency all-digital phase-locked loop in the prior art, a range of an output frequency control word dcw is reduced, an output ckr _ dly of a digital time converter DTC is the same, an average value of the fractional frequency control word fcw _ frac is unchanged, only in two adjacent periods when a flag signal frac _ flag is changed, a value of fcw _ frac is changed, and a value changed in a previous period is restored in a next period. The operation of the phase locked loop frequency and phase locking remains stable.
In the fractional-frequency adpll, a higher order signal modulator is required to achieve better spur performance, but the delay at the output of the dac is increased. The invention aims to limit the output delay of a digital-time converter within a Tckv range by a mode of modulus operation and residue operation through a residue operation unit in a fractional frequency controller, so that the order of a signal modulator can be unlimited. Assuming that T is the period duration of the target output of the dco, the clock generation and control circuit generates the clock signal ckr, which is delayed by N · T + Δ T (N is an integer) through the digital-to-time converter in the prior art, so that the delayed low frequency clock signal ckr _ dly and the feedback signal fb can be aligned. Through the complementation operation in the fractional frequency controller, the ckr only needs to delay delta T, namely, the ckr _ dly only needs to delay delta T longer than the ckr, the delay of N.T is equivalently realized by adjusting the fractional frequency control word fcw _ frac of the adjacent period, the mean value of fcw _ frac is unchanged, and the loop can work correctly. On the other hand, the complementation implemented using digital circuits is accurate and does not introduce additional errors. When the modulus is an integer power of 2, the circuit is implemented by simple bit operations, requiring very little hardware overhead. The output delay range of the digital-to-time converter is reduced by the complementation operation, so that the error and noise generated in the delay process of the analog circuit can be reduced, and the complexity and the power consumption of the analog circuit are reduced.
Compared with the prior art, the invention has the advantages that: the invention can reduce the delay range of the low-frequency clock signal ckr _ dly output by the digital time converter to a single Tckv only by adjusting and adjusting the delay control word dcw input to the digital time converter, the fractional frequency control word fcw _ frac and the integer frequency control word fcw _ int input to the auxiliary frequency locking loop through the fractional frequency controller without considering the order of the signal modulator for controlling the delay control word, thereby reducing the requirement of the fractional frequency phase-locked loop on the output delay time range of the digital time converter and further reducing the design difficulty and the power consumption of the digital time converter. The invention is realized by using a digital logic circuit for operation, has simple theory, requires very little extra hardware overhead and is easy to realize.
While the invention has been described with reference to specific embodiments, the invention is not limited thereto, and various equivalent modifications and substitutions can be easily made by those skilled in the art within the technical scope of the invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.
Claims (10)
1. A fractional-frequency all-digital phase-locked loop, comprising:
the clock generation and control circuit CTRL is used for generating a clock signal ckr required by the correct work of the phase-locked loop according to an input reference clock ref, an integer frequency control word fcw _ int and a fractional frequency control word fcw _ frac;
a fractional frequency controller FRAC CTRL for generating a delay control word dcw, a division ratio control word div, an integer frequency control word fcw _ int, and a fractional frequency control word fcw _ FRAC from an input outer fractional frequency control word fcwin _ FRAC;
a digital time converter DTC, an input end of which is connected to an output end of the clock generation and control circuit CTRL and an output end of the fractional frequency controller FRAC CTRL, and configured to generate a low-frequency clock signal ckr _ dly according to the clock signal ckr and the delay control word dcw;
a digitally controlled oscillator DCO for generating a high frequency clock signal ckv;
the input end of the feedback signal generating circuit FB GEN is connected with the output end of the digital controlled oscillator DCO and the output end of the fractional frequency controller FRACCTRL, and the feedback signal FB generating circuit FB GEN carries ckv phase information according to the frequency dividing ratio control word div;
the input end of the phase discriminator PD is connected with the output end of a digital time converter DTC, the output end of a feedback signal generating circuit FB GEN and the output end of a digital controlled oscillator DCO, and is used for generating a phase error digital signal phe of the low-frequency clock signal ckr and the feedback signal FB;
an auxiliary frequency locking loop FTL, an input end of which is connected to the digital-to-time converter DTC and the fractional-frequency controller fractrl, and outputs a control signal FTL according to the integer-frequency control word fcw _ int, the fractional-frequency control word fcw _ frac, and the low-frequency clock signal ckr _ dly;
the input end of the DCO is connected to the output end of the FTL and the output end of the phase detector PD, and adjusts the output high-frequency clock signal ckv according to the phase error digital signal phe and the control signal FTL.
2. The fractional-frequency all-digital phase-locked loop of claim 1, further comprising: the input end of the digital loop filter DLF is connected with the output end of the phase discriminator PD and the output end of the numerical control oscillator DCO; a digital loop filter DLF filters out unnecessary frequency components in the phase error digital signal phe to obtain a digital signal otw 0; the DCO outputs the high frequency clock signal ckv according to the summation of the control signal ftl and the digital signal otw 0.
3. The fractional-frequency all-digital phase-locked loop of claim 1, wherein the fractional-frequency controller fractrl comprises:
a delta-sigma modulator DSM, configured to randomize an input outer digital frequency control word fcwin _ frac, and generate a modulation signal dsmout according to the randomized fcwin _ frac;
a subtractor SUB, an input end of which is connected to an output end of the Δ Σ modulator, for calculating a difference between the external fractional-frequency control word fcwin _ frac and the modulation signal dsmout, where the difference is a frequency quantization error value frac _ q;
the input end of the accumulator ACC is connected with the output end of the subtracter and used for accumulating the frequency quantization error value frac _ q output by the subtracter to generate a phase error value frac _ qacc;
a complementation unit MOD having an input end connected to an output end of the accumulator ACC, and configured to solve the integer quotient frac _ quo and the remainder frac _ res of the phase error value frac _ qacc; and the modulus of the complementation unit is a delay control word corresponding to the target output clock period of the digital controlled oscillator DCO.
4. The fractional-frequency all-digital phase-locked loop of claim 3 wherein the fractional-frequency controller further comprises a calculation unit CALC; the input end of the computing unit CALC is connected with the output end of the complementation unit, and the fractional frequency control word fcw _ frac is generated by computing according to the integer quotient frac _ quo and the input outer fractional frequency control word fcwin _ frac.
5. The fractional-frequency all-digital phase-locked loop of claim 3, wherein the fractional-frequency controller FRACCTRL further comprises a Gain correction unit Gain Corrector and a multiplier MX; the Gain Corrector is used for generating a Gain coefficient dcw _ Gain; the input end of the multiplier MX is connected with the output end of the Gain Corrector and the output end of the complementation unit MOD, and the multiplier MX generates a delay control word dcw according to a Gain coefficient dcw _ Gain and a remainder frac _ res; and adjusting the weight of the remainder frac _ res by the gain coefficient dcw _ gain to make the conversion gain of the remainder frac _ res consistent with that of the digital time converter DTC, and meeting the requirement that the maximum output value 2^ W-1 of the frac _ res corresponds to the target output clock period of the digital controlled oscillator DCO, wherein W is the word length of the external fractional frequency control word fcwin _ frac.
6. The fractional-frequency all-digital phase-locked loop of claim 5, wherein the fractional-frequency controller FRACCTRL further comprises a word length adjusting Δ Σ modulator bit width DSM having an input connected to an output of the multiplier for adjusting the word length of the control word dcw to a set length.
7. A fractional-frequency all-digital phase-locked loop as claimed in claim 3, wherein the fractional-frequency controller fractrl further comprises a first adder ADD1 having an input connected to the output of the clock generation and control circuit CTRL, an output of the fractional-frequency controller FRAC CTRL, and an output connected to the feedback signal generation circuit FB GEN; the modulation signal dsmout is summed with the external integer frequency control word fcwin int by means of said first adder ADD1 to generate the division ratio control word div of the feedback signal generating circuit FBGEN.
8. The fractional-frequency all-digital phase-locked loop of claim 6, wherein the fractional-frequency controller FRACCTRL further comprises a second adder ADD2 having an input connected to an output of the word length adjusting Δ Σ modulator bit width DSM, and the dcw is guaranteed to be non-negative by summing dcw with 2^ W by said second adder ADD 2.
9. A method for controlling a fractional-frequency all-digital phase-locked loop, which is implemented by the fractional-frequency all-digital phase-locked loop according to any one of claims 1 to 8, comprising the steps of:
s1, the fractional frequency controller FRAC CTRL generates a delay control word dcw, a division ratio control word div, an integer frequency control word fcw _ int, and a fractional frequency control word fcw _ FRAC from the input outer fractional frequency control word fcwin _ FRAC;
s2, the clock generation and control circuit CTRL generates a clock signal ckr required by the correct work of the phase-locked loop according to the input reference clock ref and the frequency control word fcw;
s3, generating a low-frequency clock signal ckr _ dly by the digital time converter DTC according to the clock signal ckr and the delay control word dcw;
s4, the feedback signal generating circuit FB GEN outputs a feedback signal FB carrying ckv phase information according to the frequency dividing ratio control word div and the high-frequency clock signal ckv generated by the numerical control oscillator;
s5, the phase discriminator PD generates a phase error digital signal phe of the low-frequency clock signal ckr and the feedback signal fb;
s6, the auxiliary frequency locking loop outputs a control signal ftl according to the integer frequency control word fcw _ int, the fraction frequency control word fcw _ frac and the low-frequency clock signal ckr _ dly; the dco updates the high frequency clock signal based on the addition of the output control signal ftl and the phase error digital signal phe.
10. The method for controlling the fractional-frequency all-digital phase-locked loop according to claim 9, wherein the step S1 comprises:
s11, generating a modulation signal dsmout through the delta-sigma modulator DSM;
s12, adjusting the weight of dsmout to dsmout & 2^ W according to the word length W of fcwin _ frac, and obtaining the difference value of the external fractional frequency control word fcwin _ frac and the modulation signal dsmout after adjusting the weight through a subtracter SUB, wherein the difference value is a frequency quantization error value frac _ q & ltfcwin _ frac-dsmout & 2^ W;
s13, accumulating the frequency quantization error value frac _ q by an accumulator ACC to generate a phase error value frac _ qacc;
s14, generating a Gain coefficient dcw _ Gain through a Gain Corrector; performing complementation operation on the phase error value frac _ qacc, wherein the modulus is a delay control word corresponding to the target output clock period of the digital controlled oscillator DCO; multiplying the remainder frac _ res of the complementation operation and the gain coefficient dcw _ gain to obtain a delay control word dcw, and ensuring that the dcw is a non-negative number;
s15, calculating a fractional frequency control word fcw _ frac according to the integer quotient frac _ quo of the complementation operation; if the whole quotient frac _ quo is 0, fcw _ frac ═ fcwin _ frac; if the whole quotient is not 0, the fractional-frequency control word fcw _ frac (t) in the current period fcwin _ frac (t) -frac _ quo (t), the fractional-frequency control word fcw _ frac (t +1) in the next period fcwin _ frac (t +1) + frac _ quo (t); where t represents the period.
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