CN110718624A - Peltier effect cooling device and method for TDC chip - Google Patents

Peltier effect cooling device and method for TDC chip Download PDF

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CN110718624A
CN110718624A CN201910797688.3A CN201910797688A CN110718624A CN 110718624 A CN110718624 A CN 110718624A CN 201910797688 A CN201910797688 A CN 201910797688A CN 110718624 A CN110718624 A CN 110718624A
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type semiconductor
ring
chip
circular ring
tdc
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叶茂
戴庆达
赵毅强
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Tianjin University
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N19/00—Integrated devices, or assemblies of multiple devices, comprising at least one thermoelectric or thermomagnetic element covered by groups H10N10/00 - H10N15/00
    • H10N19/101—Multiple thermocouples connected in a cascade arrangement
    • F—MECHANICAL ENGINEERING; LIGHTING; HEATING; WEAPONS; BLASTING
    • F25—REFRIGERATION OR COOLING; COMBINED HEATING AND REFRIGERATION SYSTEMS; HEAT PUMP SYSTEMS; MANUFACTURE OR STORAGE OF ICE; LIQUEFACTION SOLIDIFICATION OF GASES
    • F25B—REFRIGERATION MACHINES, PLANTS OR SYSTEMS; COMBINED HEATING AND REFRIGERATION SYSTEMS; HEAT PUMP SYSTEMS
    • F25B21/00—Machines, plants or systems, using electric or magnetic effects
    • F25B21/02—Machines, plants or systems, using electric or magnetic effects using Peltier effect; using Nernst-Ettinghausen effect
    • F—MECHANICAL ENGINEERING; LIGHTING; HEATING; WEAPONS; BLASTING
    • F25—REFRIGERATION OR COOLING; COMBINED HEATING AND REFRIGERATION SYSTEMS; HEAT PUMP SYSTEMS; MANUFACTURE OR STORAGE OF ICE; LIQUEFACTION SOLIDIFICATION OF GASES
    • F25B—REFRIGERATION MACHINES, PLANTS OR SYSTEMS; COMBINED HEATING AND REFRIGERATION SYSTEMS; HEAT PUMP SYSTEMS
    • F25B49/00—Arrangement or mounting of control or safety devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N10/00—Thermoelectric devices comprising a junction of dissimilar materials, i.e. devices exhibiting Seebeck or Peltier effects
    • H10N10/10—Thermoelectric devices comprising a junction of dissimilar materials, i.e. devices exhibiting Seebeck or Peltier effects operating with only the Peltier or Seebeck effects
    • H10N10/17—Thermoelectric devices comprising a junction of dissimilar materials, i.e. devices exhibiting Seebeck or Peltier effects operating with only the Peltier or Seebeck effects characterised by the structure or configuration of the cell or thermocouple forming the device
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N10/00—Thermoelectric devices comprising a junction of dissimilar materials, i.e. devices exhibiting Seebeck or Peltier effects
    • H10N10/80—Constructional details
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N10/00—Thermoelectric devices comprising a junction of dissimilar materials, i.e. devices exhibiting Seebeck or Peltier effects
    • H10N10/80—Constructional details
    • H10N10/81—Structural details of the junction
    • F—MECHANICAL ENGINEERING; LIGHTING; HEATING; WEAPONS; BLASTING
    • F25—REFRIGERATION OR COOLING; COMBINED HEATING AND REFRIGERATION SYSTEMS; HEAT PUMP SYSTEMS; MANUFACTURE OR STORAGE OF ICE; LIQUEFACTION SOLIDIFICATION OF GASES
    • F25B—REFRIGERATION MACHINES, PLANTS OR SYSTEMS; COMBINED HEATING AND REFRIGERATION SYSTEMS; HEAT PUMP SYSTEMS
    • F25B2321/00—Details of machines, plants or systems, using electric or magnetic effects
    • F25B2321/02—Details of machines, plants or systems, using electric or magnetic effects using Peltier effects; using Nernst-Ettinghausen effects
    • F25B2321/021—Control thereof
    • F25B2321/0212—Control thereof of electric power, current or voltage

Abstract

The invention relates to a TDC circuit cooling technology, in order to provide a heat dissipation technical scheme, improve the heat dissipation efficiency and improve the heat dissipation uniformity, the invention provides a TDC chip Peltier effect cooling device, the center is a P-type semiconductor, the top of the P-type semiconductor and an external N-type semiconductor circular ring is a metal sheet which is connected through the metal sheet, the metal sheet is arranged at the hot end, an insulating medium layer is arranged between the P-type semiconductor and the N-type semiconductor ring, the outer part of the N-type semiconductor ring is the P-type semiconductor ring, an insulating layer is arranged between the N-type semiconductor ring and the P-type semiconductor ring, the bottom of the N-type semiconductor ring is a metal ring which is connected with the P-type semiconductor ring and the N-type semiconductor ring, the metal ring is arranged on the TDC chip, an insulating layer is arranged between the metal ring and the TDC chip, and the switch A and the switch B are used for controlling different control voltages to be applied between the upper end and the lower end of the P-type semiconductor ring. The invention is mainly applied to TDC circuit cooling occasions.

Description

Peltier effect cooling device and method for TDC chip
Technical Field
The invention relates to a TDC circuit cooling technology, in particular to a Peltier effect cooling method for a TDC chip.
Background
The Time-to-digital converter (TDC) circuit is used as a high-resolution Time measuring circuit and has wide application prospect in the fields of fluorescence microscope imaging, quantum communication, high-energy physical experiments and the like. TDCs can achieve picosecond resolution in Application Specific Integrated Circuits (ASICs) and FPGAs. ASIC based TDCs have good RMS accuracy and low non-linearity, but the solution is long and costly to develop and is suitable for large scale commercial products. FPGA-TDCs have shorter development cycles and greater flexibility.
The performance of the TDC chip itself is affected by temperature, and efficient cooling techniques are critical to system operation during design and operation. The technology aims to reduce the power density of the TDC chip, and the heat dissipation cost is increased sharply along with the increase of the power consumption. In the traditional structure, the heat radiator is composed of flat metal sheets, copper and aluminum belong to air and liquid convection cooling heat radiation preferred materials, and the high thermal conductivity of the materials reduces the diffusion resistance. The surface area of the radiating fins is increased, so that the radiating capacity of the radiator can be effectively improved, and the heat can be dissipated by the air convection of the fan.
Microchannel fluid heat dissipation is another common heat dissipation scheme. The peltier effect means that when current flows through a loop formed by different conductors, the current direction is different except for generating irreversible joule heat, heat absorption and heat release phenomena are respectively generated at joints of the different conductors, and the peltier effect can realize quantitative heat dissipation and cooling. The semiconductor heat dissipation scheme based on the Peltier effect can realize quantitative heat dissipation, so that the semiconductor heat dissipation scheme has a wide application prospect. Liquid cooling techniques are more complex and expensive than air cooling, the system uses a closed cooling loop and cooling pump that further increase costs, and liquid leaks in the cooling loop are highly likely to cause damage to the electronic system.
Researchers in all countries in the world propose various solutions for heat dissipation of chips. The Ho-Chiao Chuang and other scholars propose a double-layer copper wire wiring scheme based on a photoetching technology, a Chemical Mechanical Planarization (CMP) technology and an electroplating copper technology, and the unique heat increasing and dissipating copper block design can effectively conduct heat generated by an upper layer wire to a silicon substrate. Chao and Li adopt a novel enhanced ball grid array heat dissipation structure, and the packaging structure comprises a thermal plug and a foam metal heat sink. The micro-channel liquid heat dissipation device developed by researchers such as H.Y.Zhang has good parameter indexes, deionized water is used as a coolant in the device, a testing part comprises a plate-fin structure micro-channel heat dissipater and a flow management cover plate, a BGA flip chip is selected as a testing carrier, and the scheme fully considers the heat dissipation efficiency of a heat dissipation fin and the diffusion resistance from the chip to a heat dissipater base.
[ reference documents ]
[1]WEI Bo，YANG Mo，WANG Zhiyun，et al.Flow and thermal performance of awater-cooled periodic transversal elliptical microchannel heat sink for chipcooling[J]Journal of Nanoscience and Nanotechnology，2015，15(4):3061-3066.
[2] Two-phase flow technology research on cooling of high heat flux density power amplifier chip [ J ]. electronic mechanical engineering, 2016, 32(4):16-19
[3]SAEED M，KIM M H.Numerical study on thermal hydraulic performanceof water cooled mini－channel heat sinks[J].International Journal ofRefrigeration，2016，69:147-164.
[4] Lv Zhan bamboo, Zhao Fuling, Yangyong, mixed powder spark-erosion machining medium breakdown and discharge channel position research [ J ]. university of major organization, 2008, 48(3): 373)
[5]WANG P，BAR-COHEN A.On-chip hot spot cooling using siliconthermoelectric microcoolers[J].Journal of applied physics，2007，102(3)：023702-1002。
Disclosure of Invention
In order to overcome the defects of the prior art, the invention aims to provide a heat dissipation technical scheme, improve the heat efficiency of the fan and improve the uniformity of the heat efficiency of the fan. The technical scheme includes that the TDC chip Peltier effect cooling device is characterized in that a P-type semiconductor is arranged at the center, a metal sheet is arranged at the top of a P-type semiconductor and the top of an external N-type semiconductor circular ring and connected with the P-type semiconductor through the metal sheet, an insulating medium layer is arranged between the P-type semiconductor and the N-type semiconductor circular ring, the P-type semiconductor circular ring is arranged outside the N-type semiconductor circular ring, an insulating layer is arranged between the N-type semiconductor circular ring and the P-type semiconductor circular ring, a metal circular ring is arranged at the bottom of the N-type semiconductor circular ring and connected with the P-type semiconductor circular ring and the N-type semiconductor circular ring, the metal circular ring is arranged at the cold end and arranged on the TDC chip, the insulating layer is arranged between the metal circular ring and the TDC chip, and a switch A and a switch B are used for controlling different control voltages to be applied between the upper.
The temperature sensor is used for measuring the temperature of the TDC chip, the measurement result is output to the computer, the computer judges the temperature of the TDC chip to be reduced according to the set temperature threshold, different voltages are applied to the P-type semiconductor ring through the FPGA control switch A and the FPGA control switch B, and the temperature reduction in different degrees is carried out.
The Peltier effect cooling method of the TDC chip is realized by utilizing the cooling device, and comprises the following steps:
firstly, performing power consumption analysis on a working TDC circuit chip, calculating a power consumption central point (X, Y) of the TDC chip, recording P (X, Y) as chip power consumption surface density, and calculating the integral multiple P (X, Y) d sigma as the total power consumption of the TDC chip:
Figure RE-GDA0002299172190000021
to simplify the model, the circuit chip is divided into n × n squares, and a high-precision power consumption probe is used to measure the power consumption value P of each squareijConstructing a power consumption matrix V of
Figure RE-GDA0002299172190000022
Figure RE-GDA0002299172190000023
And the power consumption central point (X, Y) is used as the central point of the cooling device.
The current flows from the bottom metal lead into the P-type semiconductor, the two are in ohmic contact, and the valence band electrons of the semiconductor at least absorb EF-EVEnergy of (E) into the metal to form a current, EFAt a Fermi level, EVTo valence band energyElectrons leaving the valence band to form holes, which flow in the P-type semiconductor and require energy EαTotal energy absorbed at the contact surface is EF-EV+EαThe function of cooling is realized, current flows to the N-type semiconductor through the upper layer metal sheet, the top layer is the hot end, and then flows to the bottom layer metal ring through the N-type semiconductor, electrons flow to the N-type semiconductor from the metal ring, and the electrons at least absorb EC-EFEnergy of (E)CThe energy required for electrons to flow in the semiconductor is E at the conduction band levelβThe energy absorbed at this time is EC-EF+EβAnalyzing the heat absorption of the junction of the N-type semiconductor and the metal ring, and adopting a non-degenerate semiconductor, EC-EF>2k0T, the heat absorption and temperature reduction effects are determined by a Peltier coefficient piθDetermining, guiding the tape bottom EcDensity of states of Nc,n0As electron concentration:
qπθ＝Ec-EF+Eβ
Figure RE-GDA0002299172190000032
the invention has the characteristics and beneficial effects that:
the cooling device takes the TDC power consumption center as the center of the cooling device, so that the heat efficiency of the fan can be improved, and the uniformity of the heat of the fan can also be improved.
Description of the drawings:
FIG. 1 is a top view (top view) of a chip cooling structure based on Peltier effect;
FIG. 2 is a bottom view (bottom view) of a chip cooling structure based on Peltier effect;
FIG. 3 is a system diagram of a TDC chip and a temperature reduction device;
FIG. 4 is a metal to P-type semiconductor contact band diagram;
fig. 5 is a metal to N-type semiconductor contact band diagram.
FIG. 6 is a schematic view of the overall structure of the device of the present invention.
Detailed Description
Dividing the working TDC circuit chip into 20 × 20 grids, and measuring the power consumption value P of each grid by using a high-precision power consumption probeijAnd constructing a power consumption matrix V. And calculating the power consumption center (X, Y) of the chip according to the power consumption matrix. Based on the peltier effect, when a current passes through a loop formed by different conductors, in addition to irreversible joule heat, heat absorption and heat release phenomena occur at the joint of the different conductors respectively along with the difference of the current direction. And the annular radiation cooling structure is adopted to realize the cooling of the TDC chip, and the power consumption center (X, Y) is taken as the center of the cooling structure. The scheme can not only improve the heat efficiency of the fan, but also improve the uniformity of the heat efficiency of the fan.
The FPGA is connected with the control switch A and the control switch B, and therefore power control of the cooling device can be achieved. Setting a threshold temperature TθAnd TβAnd finishing progressive cooling. The working TDC chip is placed in a thermostat, the thermostat is heated and then cooled, and the total time of the whole process is micro TαRecording the chip temperature Tp (t) and the environmental temperature Te (t) in the incubator in real time, connecting the FPGA with a PC terminal through a serial port, recording the chip temperature Tp (t) and the environmental temperature Te (t) in real time by the PC terminal, and establishing a cooling evaluation coefficient CT
Setting a threshold coefficient CαIf C isT<CαThe cooling device meets the process requirements, if CT>CαIf the temperature reduction device belongs to a defective device, the PC end completes detection through numerical value calculation processing.
Firstly, power consumption analysis is carried out on a working TDC circuit chip, a power consumption central point (X, Y) of the TDC chip is calculated, P (X, Y) is recorded as chip power consumption surface density, and the integral multiple P (X, Y) d sigma is the total power consumption of the TDC chip.
Figure RE-GDA0002299172190000042
To simplify the model, the circuit chip may be divided into 20 × 20 squares, and a high-precision power consumption probe may be used to measure the power consumption value P of each squareijConstructing a power consumption matrix V of
Figure RE-GDA0002299172190000043
Figure RE-GDA0002299172190000044
Based on the peltier effect, when a current passes through a loop formed by different conductors, in addition to irreversible joule heat, heat absorption and heat release phenomena occur at the joint of the different conductors respectively along with the difference of the current direction. The annular radiation structure heat dissipation device is designed, and the power consumption central point (X, Y) is used as the central point of the annular radiation structure, so that the heat efficiency of the fan can be improved, and the uniformity of the heat of the fan can also be improved. As shown in fig. 1, 2 and 3, the heat dissipation device is different from the conventional heat dissipation device in that a ring design structure is adopted, a P-type semiconductor is arranged in the center of the ring, a metal sheet is arranged on the top of the P-type semiconductor and the top of an external N-type semiconductor ring and connected through the metal sheet, the metal sheet is positioned at a hot end, and an insulating medium layer is arranged between the P-type semiconductor and the N-type semiconductor ring. The outside of N type semiconductor ring is P type semiconductor ring, and the bottom is the metal ring, and P type semiconductor ring and N type semiconductor ring are connected to the metal ring, and this metal ring is in the cold junction, and then realizes the chip cooling, and figure 3 shows the current trend of radiating circuit.
A temperature sensor A is arranged at the bottom of the circuit board and corresponds to the TDC chip, the TDC chip has heat conduction, and the temperature value acquired by the sensor A is approximately equal to the temperature of the TDC chip. The temperature sensor A collects temperature signals, and the signals are subjected to noise reduction processing, analog amplification and analog-to-digital conversion and are transmitted to the FPGA. The measured value of the temperature signal exceeds a threshold temperature TθAnd meanwhile, the FPGA controls the cooling device to complete heat absorption and cooling.
As shown, the FPGA is connected to a control switch a and a control switch B. Controlled by a switchPower of temperature device when chip temperature rises to threshold temperature TθAnd when the temperature is reduced, the switch A is controlled to be conducted, so that primary temperature reduction is realized. If the temperature of the chip continuously rises, the value far exceeds the threshold temperature TθWhen the temperature reaches TβAnd when the control switch B is switched on, the system enters a high-power cooling mode, and progressive cooling can be realized by the scheme.
As shown in FIG. 4, current flows from the bottom metal lead into the P-type semiconductor, and the two are in ohmic contact and have a Fermi level EFEqual in height. At least one electron of valence band of semiconductor is absorbedF-EVCan enter the metal to form a current. The electrons leave the valence band to form holes, which flow in the P-type semiconductor and require energy EαTotal energy absorbed at the contact surface is EF-EV+EαAnd the function of cooling is realized. Current flows to the N-type semiconductor through the upper-layer metal sheet, the top layer is a hot end, and then flows to the bottom-layer metal ring through the N-type semiconductor. As shown in fig. 5, electrons flow from the metal ring into the N-type semiconductor, and in this process, the electrons absorb at least EC-EFThe energy required for the electrons to flow in the semiconductor is EβThe energy absorbed at this time is EC-EF+Eβ. We analyzed the endotherm of the junction of the N-type semiconductor with the metal ring, using a non-degenerate semiconductor, EC-EF>2k0And T. The heat absorption and temperature reduction effect is determined by a Peltier coefficient piθAnd (6) determining.
qπθ＝Ec-EF+Eβ
Figure RE-GDA0002299172190000051
And evaluating the performance of the cooling device.
The working TDC chip is placed in a thermostat, the thermostat is uniformly heated to 95 ℃ from normal temperature (25 ℃), and then is cooled to normal temperature (25 ℃), and the total time of the process isIs TαThe temperature sensor A at the bottom of the TDC chip can acquire a chip temperature signal in real time, the temperature signal is transmitted to the FPGA to record the chip temperature Tp (t) in real time, the FPGA is simultaneously connected with another temperature sensor B which records the internal environment temperature Te (t) of the incubator in real time, the FPGA is connected with the PC terminal through a serial port, and the PC terminal can record the chip temperature Tp (t) and the environment temperature Te (t) in real time. When the temperature of the chip rises with the ambient temperature and exceeds the threshold temperature TθIn the meantime, the chip cooling device starts to work immediately, and a cooling evaluation coefficient C is setT
Figure RE-GDA0002299172190000053
CTThe smaller the value of (A), the more ideal the effect of the chip cooling device is. Setting a threshold coefficient CαIf C isT<CαThe cooling device meets the process requirements, if CT>CαIf the temperature reduction device belongs to a defective device, the PC end completes detection through numerical value calculation processing.

Claims (3)

1. A Peltier effect cooling device for a TDC chip is characterized in that a P-type semiconductor is arranged at the center, a metal sheet is arranged at the top of an external N-type semiconductor circular ring and connected with the P-type semiconductor through the metal sheet, an insulating medium layer is arranged between the P-type semiconductor and the external N-type semiconductor circular ring, the P-type semiconductor circular ring is arranged outside the N-type semiconductor circular ring, an insulating layer is arranged between the N-type semiconductor circular ring and the P-type semiconductor circular ring, a metal circular ring is arranged at the bottom of the N-type semiconductor circular ring and connected with the P-type semiconductor circular ring and the N-type semiconductor circular ring, the metal circular ring is arranged at the cold end of the TDC chip, the insulating layer is arranged between the metal circular ring and the TDC chip, and a switch A and a switch B are used for controlling different control voltages to be applied between the upper end and the lower end of the.
2. The Peltier effect cooling device for TDC chip as claimed in claim 1, further comprising a temperature sensor and a computer, wherein the temperature sensor is used for measuring the temperature of the TDC chip, the measurement result is outputted to the computer, the computer judges the degree of cooling required by the temperature of the TDC chip according to the set temperature threshold, and the FPGA controls the switch A and the switch B to apply different voltages to the P-type semiconductor ring for cooling in different degrees.
3. A Peltier effect cooling method for a TDC chip is characterized by being realized by the cooling device and comprising the following steps:
firstly, performing power consumption analysis on a working TDC circuit chip, calculating a power consumption central point (X, Y) of the TDC chip, recording P (X, Y) as chip power consumption surface density, and calculating the integral multiple P (X, Y) d sigma as the total power consumption of the TDC chip:
Figure FDA0002181426870000011
to simplify the model, the circuit chip is divided into n × n squares, and a high-precision power consumption probe is used to measure the power consumption value P of each squareijConstructing a power consumption matrix V of
Figure FDA0002181426870000012
Figure FDA0002181426870000013
And the power consumption central point (X, Y) is used as the central point of the cooling device.
The current flows from the bottom metal lead into the P-type semiconductor, the two are in ohmic contact, and the valence band electrons of the semiconductor at least absorb EF-EVEnergy of (E) into the metal to form a current, EFAt a Fermi level, EVThe electrons leave the valence band to form holes at the valence band level, and the energy E is required for the holes to flow in the P-type semiconductorαTotal energy absorbed at the contact surface is EF-EV+EαThe function of cooling is realized, current flows to the N-type semiconductor through the upper layer metal sheet, the top layer is the hot end, and then flows to the bottom layer metal ring through the N-type semiconductor, electrons flow to the N-type semiconductor from the metal ring, and the electrons at least absorb EC-EFEnergy of (E)CThe energy required for electrons to flow in the semiconductor is E at the conduction band levelβThe energy absorbed at this time is EC-EF+EβAnalyzing the heat absorption of the junction of the N-type semiconductor and the metal ring, and adopting a non-degenerate semiconductor, EC-EF>2k0T, the heat absorption and temperature reduction effects are determined by a Peltier coefficient piθDetermining, guiding the tape bottom EcDensity of states of Nc,n0As electron concentration:
qπθ＝Ec-EF+Eβ
Figure FDA0002181426870000021
Figure FDA0002181426870000022
CN201910797688.3A 2019-08-27 2019-08-27 Peltier effect cooling device and method for TDC chip Pending CN110718624A (en)

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CN113192747B (en) * 2021-06-30 2021-09-21 江苏知行科技有限公司 Cold treatment method of amorphous magnetic powder core
WO2023282277A1 (en) * 2021-07-07 2023-01-12 ソニーグループ株式会社 Thermal electromotive force generation element, method for producing thermal electromotive force generation element, and image sensor
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