CN110718534B - Method for manufacturing positioning mark - Google Patents
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- CN110718534B CN110718534B CN201911001946.9A CN201911001946A CN110718534B CN 110718534 B CN110718534 B CN 110718534B CN 201911001946 A CN201911001946 A CN 201911001946A CN 110718534 B CN110718534 B CN 110718534B
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 24
- 238000000034 method Methods 0.000 title claims abstract description 16
- 239000000758 substrate Substances 0.000 claims description 43
- 238000000151 deposition Methods 0.000 claims description 10
- 239000004020 conductor Substances 0.000 claims description 9
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 5
- 229910052721 tungsten Inorganic materials 0.000 claims description 5
- 239000010937 tungsten Substances 0.000 claims description 5
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 3
- 229910052802 copper Inorganic materials 0.000 claims description 3
- 239000010949 copper Substances 0.000 claims description 3
- 238000005530 etching Methods 0.000 claims description 3
- 229910052710 silicon Inorganic materials 0.000 claims description 3
- 239000010703 silicon Substances 0.000 claims description 3
- 239000003550 marker Substances 0.000 claims 1
- 239000010408 film Substances 0.000 description 28
- 239000002184 metal Substances 0.000 description 4
- 229910052751 metal Inorganic materials 0.000 description 4
- 239000007769 metal material Substances 0.000 description 4
- 150000002500 ions Chemical class 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 238000010884 ion-beam technique Methods 0.000 description 2
- 238000005520 cutting process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 230000000750 progressive effect Effects 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 239000011265 semifinished product Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/544—Marks applied to semiconductor devices or parts
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/544—Marks applied to semiconductor devices or parts
- H01L2223/54426—Marks applied to semiconductor devices or parts for alignment
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
Abstract
The invention provides a method for manufacturing a positioning mark, which comprises the following steps: providing a sample, wherein the sample is a non-conductive sample; forming a conductive structure on the surface of the sample to be manufactured with the positioning mark, and grounding the conductive structure, wherein the conductive structure exposes a target area of the surface to be manufactured with the positioning mark; and manufacturing a positioning mark on a target area on the surface of the sample. Because the conductive structure is positioned on the surface of the non-conductive sample to be manufactured with the positioning mark and is grounded, the electric charge on the surface of the sample can be led out, the residue of electrons or electric charges on the surface of the sample is reduced, the quality of an image can be improved, the image drift is avoided, and the problem that the positioning mark cannot be accurately manufactured in a target area due to the image drift and the like can be solved when the positioning mark is manufactured in the target area on the surface of the sample.
Description
Technical Field
The invention relates to the technical field of semiconductor manufacturing, in particular to a manufacturing method of a positioning mark.
Background
In a three-dimensional memory (3D-NAND) manufacturing process, in order to monitor the process results of each ongoing link, it is generally necessary to perform a sample cutting analysis on a semi-finished product, such as a sample of an ONO (oxy-Nitrogen-oxy) structure of a three-dimensional memory.
In order to improve the accuracy of sample preparation in the case of cut sample analysis, it is necessary to form a positioning mark in a target region of a sample using FIB (Focused Ion beam). However, for a sample with poor insulation or conductivity, the positioning mark cannot be accurately manufactured in the target area, so that the positioning mark cannot be accurately positioned.
Disclosure of Invention
In view of this, the present invention provides a method for manufacturing a positioning identifier, so as to improve the accuracy of the manufactured positioning identifier and improve the positioning accuracy of the positioning identifier.
In order to achieve the purpose, the invention provides the following technical scheme:
a method for manufacturing a positioning mark comprises the following steps:
providing a sample, wherein the sample is a non-conductive sample;
forming a conductive structure on the surface of the sample to be manufactured with the positioning mark, and grounding the conductive structure, wherein the conductive structure exposes a target area of the surface to be manufactured with the positioning mark;
and manufacturing a positioning mark on a target area on the surface of the sample.
Optionally, the step of disposing the sample on a substrate, forming a conductive structure on a surface of the sample on which the positioning mark is to be made, and grounding the conductive structure includes:
and forming a conductive structure for connecting the surface of the sample and the substrate on the surface of the sample on which the positioning mark is to be manufactured, and grounding the substrate.
Optionally, the forming of the conductive structure connecting the sample surface and the substrate on the surface of the sample on which the positioning mark is to be made includes:
forming a first conductive film layer on the substrate, wherein the first conductive film layer is positioned on the side edge of the sample, the first conductive film layer is connected and fixed with the sample and the substrate, and the substrate is grounded;
and forming a second conductive film layer on the surface of the sample on which the positioning mark is to be manufactured, wherein the second conductive film layer is exposed out of the target area and is connected with the surface of the sample and the first conductive film layer.
Optionally, the forming the first conductive film layer includes:
depositing a conductive material on the substrate;
forming the second conductive film layer includes:
and depositing a conductive material on the surface of the sample on which the positioning mark is to be made.
Optionally, the target region is located in a middle region of the surface of the sample, and forming a conductive structure on the surface of the sample on which the positioning mark is to be made includes:
and forming a conductive structure in a non-target area of the surface of the sample on which the positioning mark is to be manufactured, wherein the non-target area is positioned at the periphery of the target area.
Optionally, the substrate is a copper substrate; alternatively, the substrate is a silicon substrate.
Optionally, the conductive material is a metal material.
Optionally, the metal material is tungsten.
Optionally, the step of making a positioning mark on the target area of the sample surface comprises:
and etching or depositing a film layer on the target area of the surface of the sample by using FIB equipment to manufacture the positioning mark.
Compared with the prior art, the technical scheme provided by the invention has the following advantages:
according to the manufacturing method of the positioning mark, the conductive structure is formed on the surface of the non-conductive sample where the positioning mark is to be manufactured, and is grounded, so that charges on the surface of the sample can be led out, the residue of electrons or charges on the surface of the sample is reduced, the quality of an image can be improved, the drift of the image is avoided, and the problem that the positioning mark cannot be accurately manufactured in a target area due to image drift and the like when the positioning mark is manufactured in the target area on the surface of the sample can be solved.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.
FIG. 1 is a schematic diagram of a FIB-fabricated positioning mark offset structure;
fig. 2 is a flowchart of a method for making a positioning identifier according to an embodiment of the present invention;
FIG. 3 is a schematic perspective view of a sample and a substrate provided by an embodiment of the present invention;
FIG. 4 is a schematic top view of the sample and substrate shown in FIG. 3;
fig. 5 is a schematic top-view structural diagram of a sample, a substrate and a first conductive film layer provided in an embodiment of the present invention;
FIG. 6 is a schematic top view of a sample, a substrate and a conductive structure according to an embodiment of the present invention;
fig. 7 is a schematic top view of another sample, a substrate and a conductive structure according to an embodiment of the present invention.
Detailed Description
As described in the background, for samples that are poorly insulated or conductive, the mark cannot be accurately made on the target area. The working principle of the FIB equipment is as follows: the ion beam generated by the ion source is accelerated and focused by the ion gun and then irradiates the surface of the sample, secondary electrons are generated after the ions and the material on the surface of the sample act, the electrons are captured by the electron detector, the surface of the sample can be imaged, and the surface of the sample can be imaged, simultaneously, a physical sputtering mode can be used for matching with chemical gas reaction, a metal layer is selectively etched or deposited, and the like, so that the manufacturing of the positioning mark is completed.
The inventor researches and discovers that the cause of the problem of inaccurate manufacture position of the positioning mark is mainly that, for a sample with poor insulation or conductivity, part of electrons can remain or accumulate on the surface of the sample, which causes the image quality to be reduced, and more importantly, the positioning mark 10 can not be accurately manufactured in the target area 11, as shown in fig. 1.
Based on this, the present invention provides a method for manufacturing a positioning mark, so as to overcome the above problems in the prior art, including:
providing a sample, wherein the sample is a non-conductive sample;
forming a conductive structure on the surface of the sample to be manufactured with the positioning mark, and grounding the conductive structure, wherein the conductive structure exposes a target area of the surface to be manufactured with the positioning mark;
and manufacturing a positioning mark on a target area on the surface of the sample.
According to the manufacturing method of the positioning mark, the conductive structure is formed on the surface of the non-conductive sample where the positioning mark is to be manufactured, and is grounded, so that charges on the surface of the sample can be led out, the residue of electrons or charges on the surface of the sample is reduced, the quality of an image can be improved, the image drift is avoided, and the problem that the positioning mark cannot be accurately manufactured in a target area due to image drift and the like when the positioning mark is manufactured in the target area on the surface of the sample can be solved.
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, so that the above is the core idea of the present invention, and the above objects, features and advantages of the present invention can be more clearly understood. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The embodiment of the invention provides a method for manufacturing a positioning identifier, which comprises the following steps as shown in fig. 2:
s101: providing a sample, wherein the sample is a non-conductive sample;
the sample in the embodiment of the present invention refers to a sample for which a FIB device is required to make a positioning mark, but the present invention is not limited thereto, and the method in the embodiment of the present invention may be used for any sample for which a surface residual charge needs to be derived. It should be noted that the samples in the examples of the present invention are necessarily non-conductive samples, which include samples that are completely insulated and samples that are poorly conductive. The sample may be a sample of an ONO structure of a three-dimensional memory, etc., although the present invention is not limited to the memory structure, and in other embodiments, the sample may also be other non-conductive devices.
S102: forming a conductive structure on the surface of the sample to be manufactured with the positioning mark, and grounding the conductive structure, wherein the conductive structure exposes a target area on the surface of the sample to be manufactured with the positioning mark;
in the embodiment of the present invention, as shown in fig. 3 and 4, the sample 20 is disposed on a substrate 21, and optionally, the substrate 21 is a copper substrate; alternatively, the substrate 21 is a silicon substrate or the like. The surface of the sample 20 facing upwards is a surface on which the positioning mark is to be made, in the embodiment of the present invention, a conductive structure may be directly formed on the surface on which the positioning mark is to be made, and the charge on the surface of the sample 20 is conducted away by grounding the conductive structure, although the present invention is not limited thereto, and in other embodiments, the charge may be conducted away by the conductive structure and other structures connected to and grounded to the conductive structure, such as the substrate 21 connected to and grounded to the conductive structure.
That is, forming a conductive structure on the surface of the sample on which the positioning mark is to be made, and grounding the conductive structure includes:
and forming a conductive structure for connecting the surface of the sample and the substrate on the surface of the sample on which the positioning mark is to be manufactured, and grounding the substrate.
The process of forming the conductive structure connecting the sample surface and the substrate is explained below. It should be noted that the conductive structure in the embodiment of the present invention may be a conductive thin film, a metal wire, a metal film layer deposited on the surface of the sample 20, and the like. In the embodiment of the present invention, only the conductive structure is taken as an example of the metal film layer deposited on the surface of the sample 20.
As shown in fig. 5, a first conductive film layer 220 is formed on the substrate 21, the first conductive film layer 220 is located at a side of the sample 20, and the first conductive film layer 220 is connected to fix the sample 20 and the substrate 21, wherein the substrate 21 is grounded.
Then, as shown in fig. 6, a second conductive film 221 is formed on the surface of the sample 20 where the positioning mark is to be made, the second conductive film 221 exposes the target area a, and the second conductive film 221 connects the surface of the sample 20 and the first conductive film 220.
Based on this, the charges on the surface of the sample 20 can be introduced into the first conductive film layer 220 through the second conductive film layer 221, then the charges are introduced into the substrate 21 through the first conductive film layer 220, and then the charges are introduced into the ground through the substrate 21, so that the residual of electrons or charges on the surface of the sample 20 can be reduced, the quality of an image can be improved, the image drift can be avoided, and further, when a positioning mark is manufactured in a target area a on the surface of the sample 20, the problem that the positioning mark cannot be accurately manufactured in the target area a due to the image drift and the like can be solved.
Wherein the forming the first conductive film layer 220 includes: a conductive material is deposited on the substrate 21. The forming of the second conductive film layer 221 includes: and depositing a conductive material on the surface of the sample 20 on which the positioning mark is to be made. Optionally, the conductive material is a metal material, and further optionally, the metal material is tungsten W.
Since the substrate 21 and the sample 20 are bonded and fixed by depositing tungsten on the substrate 21 when the positioning mark is fabricated on the three-dimensional storage, in the embodiment of the present invention, not only the first conductive film layer 220 for bonding and fixing the substrate 21 and the sample 20 can be formed by depositing tungsten, but also the conductive structure 22, that is, the first conductive film layer 220 and the second conductive film layer 221 can be formed.
It should be noted that the conductive structures 22 in the embodiment of the present invention may be located on one side or two sides of the target area a, as shown in fig. 6, and the conductive structures 22 are located on the left and right sides of the target area a, but preferably, the conductive structures 22 in the embodiment of the present invention are located on the periphery of the target area a, as shown in fig. 7, that is, on the basis of the structure shown in fig. 6, the conductive structures 22 are also formed on the upper and lower sides of the target area a. Moreover, the larger the area of the conductive structure 22 covering the surface of the sample 20 is, the better the image drift is improved, and the higher the accuracy of the positioning mark is. That is, when the target area a is located in the middle area of the surface of the sample 20, the forming of the conductive structure 22 on the surface of the sample 20 where the positioning mark is to be made includes:
the conductive structure 22 is formed on the non-target area of the surface of the sample 20 on which the positioning mark is to be made, and the non-target area is located at the periphery of the target area a.
S103: and manufacturing a positioning mark on a target area on the surface of the sample.
After forming the conductive structure 22 on the surface of the sample 20 and grounding the conductive structure 22, a positioning mark may be made on the surface of the sample 20, and making a positioning mark on the target area a on the surface of the sample 20 includes: and etching or depositing a film layer on the target area A on the surface of the sample 20 by using FIB equipment to manufacture the positioning mark.
According to the method for manufacturing the positioning mark, the conductive structure is formed on the surface of the non-conductive sample where the positioning mark is to be manufactured, and is grounded, so that charges on the surface of the sample can be led out, the residue of electrons or charges on the surface of the sample is reduced, the quality of an image can be improved, the drift of the image is avoided, and the problem that the positioning mark cannot be accurately manufactured in a target area due to image drift and the like when the positioning mark is manufactured in the target area on the surface of the sample can be solved.
In the present specification, the embodiments are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other. The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (4)
1. A method for manufacturing a positioning mark is characterized by comprising the following steps:
providing a sample, wherein the sample is a non-conductive sample, and the sample is an ONO structure of a three-dimensional memory;
forming a conductive structure on the surface and the side edge of the sample to be manufactured with the positioning mark, and grounding the conductive structure, wherein the conductive structure exposes a target area of the surface to be manufactured with the positioning mark;
manufacturing a positioning mark in a target area on the surface of the sample;
wherein, the sample sets up on the basement, and the surface and the side that wait to make the location sign in the sample form conductive structure to make conductive structure ground connection includes:
forming a first conductive film layer on the substrate, wherein the first conductive film layer is positioned on the side edge of the sample, the first conductive film layer is connected and fixed with the sample and the substrate, and the substrate is grounded;
forming a second conductive film layer on the surface of the sample where the positioning mark is to be made, wherein the second conductive film layer is exposed out of the target area and is connected with the surface of the sample and the first conductive film layer;
forming the first conductive film layer includes: depositing a conductive material on the substrate;
forming the second conductive film layer includes: depositing a conductive material on the surface of the sample to be manufactured with the positioning mark;
the conductive material is tungsten.
2. The method of claim 1, wherein the target region is located in a middle region of the surface of the sample, and forming the conductive structure on the surface of the sample on which the positioning mark is to be made comprises:
and forming a conductive structure in a non-target area of the surface of the sample on which the positioning mark is to be manufactured, wherein the non-target area is positioned at the periphery of the target area.
3. The method of claim 1, wherein the substrate is a copper substrate; alternatively, the substrate is a silicon substrate.
4. The method of claim 1, wherein creating a location marker in the target area of the sample surface comprises:
and etching or depositing a film layer on the target area of the surface of the sample by using FIB equipment to manufacture the positioning mark.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911001946.9A CN110718534B (en) | 2019-10-21 | 2019-10-21 | Method for manufacturing positioning mark |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911001946.9A CN110718534B (en) | 2019-10-21 | 2019-10-21 | Method for manufacturing positioning mark |
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| CN110718534A CN110718534A (en) | 2020-01-21 |
| CN110718534B true CN110718534B (en) | 2022-10-04 |
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| CN113189123B (en) * | 2021-04-30 | 2023-01-31 | 东南大学 | Observation micro-area positioning method based on internal standard substance microarray |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20100103583A1 (en) * | 2008-10-27 | 2010-04-29 | Hermes-Microvision, Inc. | Wafer grounding methodology |
| JP2013195192A (en) * | 2012-03-19 | 2013-09-30 | Sumitomo Metal Mining Co Ltd | Pretreatment method of insulating sample and surface analysis method |
| CN105865861A (en) * | 2015-01-23 | 2016-08-17 | 中芯国际集成电路制造(上海)有限公司 | Method for preparing sample for failure analysis |
| CN206193030U (en) * | 2016-10-11 | 2017-05-24 | 苏州阿特斯阳光电力科技有限公司 | Carry on one's shoulder or back electric guiding piece and be used for electron microscope's test platform |
| CN109585324A (en) * | 2018-11-30 | 2019-04-05 | 上海华力微电子有限公司 | A method of improving the pattern etching at substrate defects |
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2019
- 2019-10-21 CN CN201911001946.9A patent/CN110718534B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20100103583A1 (en) * | 2008-10-27 | 2010-04-29 | Hermes-Microvision, Inc. | Wafer grounding methodology |
| JP2013195192A (en) * | 2012-03-19 | 2013-09-30 | Sumitomo Metal Mining Co Ltd | Pretreatment method of insulating sample and surface analysis method |
| CN105865861A (en) * | 2015-01-23 | 2016-08-17 | 中芯国际集成电路制造(上海)有限公司 | Method for preparing sample for failure analysis |
| CN206193030U (en) * | 2016-10-11 | 2017-05-24 | 苏州阿特斯阳光电力科技有限公司 | Carry on one's shoulder or back electric guiding piece and be used for electron microscope's test platform |
| CN109585324A (en) * | 2018-11-30 | 2019-04-05 | 上海华力微电子有限公司 | A method of improving the pattern etching at substrate defects |
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