CN110718259B - Nonvolatile memory detection circuit and detection method - Google Patents
Nonvolatile memory detection circuit and detection method Download PDFInfo
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- CN110718259B CN110718259B CN201810772570.0A CN201810772570A CN110718259B CN 110718259 B CN110718259 B CN 110718259B CN 201810772570 A CN201810772570 A CN 201810772570A CN 110718259 B CN110718259 B CN 110718259B
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/30—Power supply circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
- G11C5/147—Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops
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Abstract
The embodiment of the invention provides a nonvolatile memory detection circuit and a detection method, wherein the circuit comprises: the compensation circuit is connected with the charging circuit and used for compensating the threshold deviation of the nonvolatile memory detection circuit; the charging circuit is connected with the storage unit selection circuit and used for initially charging the storage unit selection circuit; the charging circuit is connected with the comparison circuit and used for charging the comparison circuit after the storage unit selection circuit is stably charged, and finishing charging the comparison circuit and the storage unit selection circuit after the comparison circuit is stably charged; the storage unit selection circuit and the comparison circuit form a current loop through the charging circuit, so that the comparison circuit outputs high level or low level according to the current loop. According to the embodiment of the invention, partial threshold value deviation of the detection circuit can be compensated through the compensation circuit, so that the detection circuit can accurately detect the data state of each storage unit in the nonvolatile memory.
Description
Technical Field
The present invention relates to the field of memory processing technologies, and in particular, to a nonvolatile memory detection circuit and a nonvolatile memory detection method.
Background
With the development of various electronic devices, embedded systems, and the like, nonvolatile memory devices are widely used in electronic products. Taking a non-volatile Memory NAND Flash Memory (NAND Flash Memory) as an example, the NAND Memory is composed of a plurality of Memory cells (cells), and the Memory cells can be negative threshold Memory cells, that is, Memory cells with negative turn-on threshold voltage; or a positive threshold memory cell, i.e., a memory cell in which the turn-on threshold voltage is a positive value; the data state of the memory cell, such as an erased state, a programmed state, etc., can be read according to the on-current of the memory cell when it is operated.
In the related art nonvolatile memory detection circuit, the threshold voltage of the transistor may change with the variation of the integrated circuit process, the operating voltage or the operating temperature environment, etc., resulting in unstable current passing through the transistor, so that the detection circuit cannot accurately detect the data state of each memory cell in the nonvolatile memory.
Disclosure of Invention
In view of the foregoing problems, embodiments of the present invention provide a nonvolatile memory detection circuit and a detection method thereof to improve accuracy of data detection on a memory cell.
According to a first aspect of the invention, there is provided a non-volatile memory sensing circuit, the method comprising:
the device comprises a compensation circuit, a charging circuit, a comparison circuit and a storage unit selection circuit;
the compensation circuit is connected with the charging circuit and used for compensating the threshold deviation of the nonvolatile memory detection circuit;
the charging circuit is connected with the storage unit selection circuit and used for initially charging the storage unit selection circuit;
the charging circuit is connected with the comparison circuit and used for charging the comparison circuit after the charging of the storage unit selection circuit is stable, and finishing the charging of the comparison circuit and the storage unit selection circuit after the charging of the comparison circuit is stable;
the storage unit selection circuit and the comparison circuit form a current loop through the charging circuit, so that the comparison circuit outputs a high level or a low level according to the current loop;
and the output end of the comparison circuit is used as the output end of the nonvolatile memory detection circuit.
According to a second aspect of the present invention, there is provided a nonvolatile memory process detection method applied to the nonvolatile memory detection circuit, the detection method comprising:
determining a memory cell to be detected in the memory cell selection circuit;
charging the memory cell selection circuit by the charging circuit;
when the storage unit selection circuit is stably charged, the second input end of the comparison circuit is charged through the charging circuit; a first input end of the comparison circuit is provided with a comparison voltage VTH;
when the charging of the second input end of the comparison circuit is stable, the charging of the storage unit selection circuit and the comparison circuit is finished, and the storage unit selection circuit and the comparison circuit form a current loop by controlling the charging circuit;
and determining the data state of the memory cell to be detected according to the current loop.
In the embodiment of the invention, the compensation circuit is arranged, and partial threshold deviation of the detection circuit can be compensated through the compensation circuit, so that when the nonvolatile memory detection circuit detects the memory cells, current instability caused by transistor threshold deviation of the charging circuit is reduced, and the detection circuit can accurately detect the data state of each memory cell in the nonvolatile memory.
The foregoing description is only an overview of the technical solutions of the present invention, and the embodiments of the present invention are described below in order to make the technical means of the present invention more clearly understood and to make the above and other objects, features, and advantages of the present invention more clearly understandable.
Drawings
Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The drawings are only for purposes of illustrating the preferred embodiments and are not to be construed as limiting the invention. Also, like reference numerals are used to refer to like parts throughout the drawings. In the drawings:
FIG. 1 is a schematic structural diagram of a non-volatile memory detection circuit according to an embodiment of the present invention;
FIG. 2 is a schematic structural diagram of a memory cell determination module according to an embodiment of the present invention;
FIG. 3 is a timing diagram of a non-volatile memory process detection circuit according to an embodiment of the present invention;
FIG. 4 is a flowchart of a method for detecting a processing of a non-volatile memory according to an embodiment of the present invention.
Detailed Description
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in further detail below. It should be understood that the specific embodiments described herein are merely illustrative of the invention, but do not limit the invention to only some, but not all embodiments.
Example one
Referring to fig. 1, a nonvolatile memory detection circuit is shown, which may specifically include: the compensation circuit 100, the charging circuit 300, the comparison circuit 400, and the memory cell selection circuit 200.
The compensation circuit 100 is connected to the charging circuit 300, and is used for compensating the threshold deviation of the non-volatile memory detection circuit; the charging circuit 300 is connected to the memory cell selection circuit 200, and is used for initially charging the memory cell selection circuit 200; the charging circuit 300 is connected to the comparison circuit 400, and is configured to charge the comparison circuit 400 after the charging of the memory cell selection circuit 200 is stable, and to end the charging of the comparison circuit 400 and the memory cell selection circuit 200 after the charging of the comparison circuit 400 is stable; the memory cell selection circuit 200 forms a current loop with the comparison circuit 400 through the charging circuit 300, so that the comparison circuit 400 outputs a high level or a low level according to the current loop; the output terminal of the comparison circuit 400 is used as the output terminal of the nonvolatile memory detection circuit.
In the embodiment of the invention, when the detection circuit works, the SBUS is firstly pre-charged to a fixed voltage, then the discharge is carried out through a path from the SBUS to the memory cell, different memory cells can lead the SBUS to have different discharge capacities, so that the voltage delta V of the SBUS is different, and finally the numerical value stored in the memory cell is distinguished by comparing the voltage of the SBUS and the voltage of the VTH, wherein BUS < VTH is an erasing state '1', SBUS > VTH is a programming state '0'. The working principle of the nonvolatile memory detection circuit is as follows:
in the first stage, the Bit Line (BL) voltage of the memory cell selection circuit 200 is charged by the charging circuit 300, and in the memory cell selection circuit, the memory cell to be detected can be selected through logic control, except for the selected memory cell to be detected, other memory cells are all in a conducting state, and the threshold voltage of the memory cell to be detected determines the current magnitude of the memory cell selection circuit 200 flowing through the charging circuit 300.
In the second stage, after the BL voltage of the memory cell selection circuit 200 is charged stably, the second input terminal SBUS of the comparison circuit 400 is charged by the charging circuit 300, and the comparison voltage VTH is set at the first input terminal of the comparison circuit 400.
In the third stage, when the charge of the second input terminal SBUS of the comparison circuit 400 is stable, the charge of the memory cell selection circuit 200 and the comparison circuit 400 is ended, and the memory cell selection circuit 200 and the comparison circuit 400 form a current loop by controlling the charge circuit 300; at this time, the current of the memory cell to be tested is provided by the second input terminal SBUS of the comparison circuit 400, the conduction threshold voltages of different memory cells to be tested are different, and the states of the stored data are different, so that SBUS discharges differently, so that SBUS voltages are different, and further the numerical state of the memory cell can be distinguished by comparing the SBUS voltage at the second input terminal of the comparison circuit 400 with the VTH at the first input terminal of the comparison circuit 400, specifically: SBUS < VTH, for erased state "1", SBUS > VTH, for programmed state "0".
In the first to third stages, the threshold voltage of the components used in the charging circuit 300 may change with different working voltages, different working environments, etc., so that the voltage of the SBUS is unstable, and a phenomenon of error in distinguishing the numerical state of the memory cell is likely to occur; therefore, the compensation circuit 100 can be provided with a circuit structure for compensating the components of the charging circuit 300, so as to compensate the threshold deviation of the charging circuit 300, stabilize the voltage in the SBUS, and accurately detect the data state of each memory cell in the nonvolatile memory. In specific application, the compensation circuit 100 and the charging circuit 300 can be constructed by NMOS transistors, and the model of the NMOS transistor in the compensation circuit 100 can be matched with the model of the NMOS transistor in the charging circuit 300 to compensate the threshold deviation of the NMOS transistor in the charging circuit 300, so that the SBUS charging potential is stable.
Preferably, referring to fig. 1, the charging circuit 300 includes: NMOS transistors M1, M2, M3, a first power supply VDD; the drain of the M1 is connected with the first power supply VDD; the source of the M1 is connected with the drain of the M3 to serve as a connection end of the charging circuit and the comparison circuit for charging the comparison circuit; the drain of the M2 is connected with the first power supply VDD; the source of the M2 is connected to the source of the M3 to act as a connection for the charging circuit to the memory cell selection circuit to charge the memory cell selection circuit.
The compensation circuit 100 includes: an NMOS transistor M5, a second power supply VCC, a third power supply module VPRE; the gate of the M5, the drain of the M5, and the gate of the M1 are connected to the second power VCC; the source of the M5 is connected to the third power supply module VPRE.
The comparison circuit 400 includes: a comparator, a first input terminal of which inputs a comparison voltage VTH and a second input terminal of which is connected with the source of the M1 to receive the charging voltage of the charging circuit; a second input terminal of the comparator is connected with the drain of the M3 to form a current loop with the memory cell selection circuit through the M3; and the first end of the capacitor C is connected with the second input end of the comparator, and the second end of the capacitor C is grounded.
The memory cell selection circuit 200 includes: an NMOS transistor M4, a memory cell determination module; the drain of the M4 is connected with the source of the M3; the source of the M4 is connected to the output of the memory cell determination module.
In a specific application, the storage unit determining module may be a unit string (string) of a non-volatile memory, as shown in fig. 2, and includes: a drain terminal selection switch SGD of the array string, the SGD having a function similar to an NMOS transistor and having a source, a gate and a drain; a source end selection switch SGS of the array string, wherein the SGS has the similar function of an NMOS transistor and has a source electrode, a grid electrode and a drain electrode; memory cells WL0 to WLn, where n is a natural number, it will be appreciated that in practice the value of n may be set to 31 in combination with the performance requirements of the non-volatile memory; the drain electrode of the SGD is connected with the BL; the source of the SGS is connected with a source line SL, wherein the voltage of the SL can be adjusted according to different voltage thresholds of the memory cells; SGS, memory cells WL0 to WLn and SGD form a series circuit in a mode that a drain electrode is connected with a source electrode.
In the embodiment of the present invention, the operation timing of the non-volatile memory detection circuit is shown in FIG. 3, wherein PRES is the gate voltage timing of M1, COMC _ E/O is the gate voltage timing of M2, SENS is the gate voltage timing of M3, and BLC _ E/O is the gate voltage timing of M4; WLn is the memory cell to be detected, WL other is the non-detection memory cell.
The specific process is as follows:
stage T0: COMC _ E/O, BLC _ E/O high, M2, M4 are turned on, the first power supply VDD charges BL, SGD, SGS, WL _ other are turned on, the gate of WLn can be at a specific voltage (e.g. 0 or other value, when the gate voltage of WLn is 0, WLn is a negative threshold memory cell), the SL voltage is raised but less than the voltage of the first power supply VDD, so that the first power supply VDD to SL have a constant current path, and the cell VT (memory cell threshold voltage) of WLn determines the magnitude of this current.
And a stage T1, in which after the BL charging voltage is stabilized, PRES is set to high level, M1 is turned on, and the SBUS is charged by the first power supply VDD.
Stage T2: after the SBUS is charged stably, PRES is set to be low level, COMC _ E/O is set to be low level, SENS is set to be high level, M1 and M2 are turned off, M3 is turned on, the current of the memory cell is provided by SBUS, different conducting threshold voltages of different memory cells to be tested and different states of stored data cause different SBUS discharges, so that different voltages of SBUS can be distinguished, and the states of the memory cells can be distinguished.
And stage T3, SENS sets low level, M3 turns off, and detection ends.
In practical application, because the capacitance of the SBUS is relatively small due to the problem of circuit cost, and the change of the SBUS voltage is relatively sensitive, how to accurately control the SBUS initial precharge voltage is also a key for improving the effect of the detection circuit, the SBUS initial precharge voltage is obtained by subtracting the M1 threshold voltage VTm1 from the M1 gate voltage VPRES, and the threshold value VTm1 of the MOS transistor M1 is changed along with the integrated circuit process, the working voltage, the working temperature environment and the like, so that the SBUS precharge voltage is also changed along with the factors.
In the embodiment of the present invention, the compensation circuit 100 includes: an NMOS transistor M5, a second power supply VCC, a third power supply module VPRE; the gate of M5, the drain of M5 and the gate of M1 are connected with the second power supply VCC; the source of M5 is connected to the third power supply module VPRE. The second power supply VCC ensures normal operation of M5, the third power supply module VPRE has a more accurate reference voltage, M5 may be a device completely matched with M1 type, size and the like, M1 gate voltage VPREs minus M5 threshold voltage VTm5 is equal to the third voltage VPRE, so that M1 is substantially the same as M5 along with changes of working voltage, environment and other influencing factors, VSBUS becomes VPRE, VPRE is a more accurate reference voltage obtained by design, and thus, by increasing M5, SBUS precharge changes caused by M1 are compensated, so that a more accurate SBUS voltage can be obtained, and accuracy of the detection circuit is improved.
It is understood that similar circuits such as the compensation circuit 100 can be provided for the gates of other MOS transistors such as M2, M3, M4, etc., so as to obtain a more accurate BL voltage, and also improve the accuracy of the detection circuit.
In the embodiment of the invention, the compensation circuit is arranged, and partial threshold deviation of the detection circuit can be compensated through the compensation circuit, so that when the nonvolatile memory detection circuit detects the memory cells, current instability caused by transistor threshold deviation of the charging circuit is reduced, and the detection circuit can accurately detect the data state of each memory cell in the nonvolatile memory.
Preferably, for the comparison circuit, the SBUS also has corresponding MOS devices connected thereto, and an MOS device M6 corresponding to the MOS device connected to the SBUS in the comparison circuit may be provided to compensate for environmental deviation in the comparison circuit, so that the comparison detection of the SBUS can reduce the influence of environmental changes, so that the detection circuit can accurately detect the data state of each memory cell in the nonvolatile memory. Therefore, as shown in fig. 1, in the embodiment of the present invention, the compensation circuit further includes: an NMOS transistor M6; the gate of the M6 and the drain of the M5 are connected to the third power supply module VPRE.
In the embodiment of the invention, the compensation circuit can compensate the threshold deviation of the transistors of the charging circuit and the comparison circuit in the detection circuit, so that when the nonvolatile memory detection circuit detects the memory cells, the current instability caused by the threshold deviation of the transistors of the charging circuit is reduced, and the detection circuit can accurately detect the data state of each memory cell in the nonvolatile memory.
Example two
Referring to fig. 4, a nonvolatile memory detection method is shown, which is applied to any one of the nonvolatile memory detection circuits, and specifically includes:
step 401: and determining the memory cell to be detected in the memory cell selection circuit.
In the embodiment of the invention, the memory cell selection circuit can select the memory cell to be detected, and the corresponding source line voltage SL can be set in the memory cell selection circuit according to the difference of the threshold voltages of the memory cell to be detected.
Step 402: the memory cell selection circuit is charged by the charging circuit.
Step 403: when the storage unit selection circuit is stably charged, the second input end of the comparison circuit is charged through the charging circuit; wherein, a first input end of the comparison circuit is provided with a comparison voltage VTH.
Step 404: and when the second input end of the comparison circuit is stably charged, the storage unit selection circuit and the comparison circuit are charged, and the storage unit selection circuit and the comparison circuit form a current loop by controlling the charging circuit.
Step 405: and determining the data state of the memory cell to be detected according to the current loop.
Preferably, the charging circuit includes: an NMOS transistor M2;
the step of charging the memory cell selection circuit by the charging circuit includes:
and controlling M2 of the charging circuit to be conducted to charge the storage unit selection circuit.
Preferably, the charging circuit includes: an NMOS transistor M1;
the step of charging the second input terminal of the comparison circuit through the charging circuit after the charging of the memory cell selection circuit is stable comprises:
and when the charging of the storage unit selection circuit is stable, controlling the M1 of the charging circuit to be conducted, and charging the second input end of the comparison circuit.
Preferably, the charging circuit includes: an NMOS transistor M3;
the step of making the memory cell selection circuit and the comparison circuit constitute a current loop by controlling the charging circuit includes:
and controlling M3 of the charging circuit to be conducted, so that the storage unit selection circuit and the comparison circuit form a current loop.
In the embodiment of the invention, the compensation circuit is arranged, and partial threshold deviation of the detection circuit can be compensated through the compensation circuit, so that when the nonvolatile memory detection circuit detects the memory cells, current instability caused by transistor threshold deviation of the charging circuit is reduced, and the detection circuit can accurately detect the data state of each memory cell in the nonvolatile memory.
It should be noted that the foregoing method embodiments are described as a series of acts or combinations for simplicity in explanation, but it should be understood by those skilled in the art that the present invention is not limited by the order of acts or acts described, as some steps may occur in other orders or concurrently in accordance with the invention. Further, those skilled in the art will appreciate that the embodiments described in the specification are presently preferred and that no particular act is required to implement the invention.
As for the method embodiment, since it is basically similar to the apparatus embodiment, the description is simple, and the relevant points can be referred to the partial description of the method embodiment.
The embodiments in the present specification are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other.
As will be appreciated by one skilled in the art, embodiments of the present invention may be provided as a method, apparatus, or computer program product. Accordingly, embodiments of the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, embodiments of the present invention may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.
While preferred embodiments of the present invention have been described, additional variations and modifications of these embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. Therefore, it is intended that the appended claims be interpreted as including preferred embodiments and all such alterations and modifications as fall within the scope of the embodiments of the invention.
Finally, it should also be noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or terminal that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or terminal. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other like elements in a process, method, article, or terminal that comprises the element.
The present invention provides a nonvolatile memory detection circuit and a nonvolatile memory processing detection method, which are described in detail above, and the principle and the implementation of the present invention are explained in detail herein by applying specific examples, and the description of the above embodiments is only used to help understanding the method of the present invention and the core idea thereof; meanwhile, for a person skilled in the art, according to the idea of the present invention, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present invention.
Claims (9)
1. A non-volatile memory sensing circuit, the circuit comprising:
the device comprises a compensation circuit, a charging circuit, a comparison circuit and a storage unit selection circuit;
the compensation circuit is connected with the charging circuit and used for compensating the threshold deviation of the nonvolatile memory detection circuit;
the charging circuit is connected with the storage unit selection circuit and used for initially charging the storage unit selection circuit;
the charging circuit is connected with the comparison circuit and used for charging the comparison circuit after the charging of the storage unit selection circuit is stable, and finishing the charging of the comparison circuit and the storage unit selection circuit after the charging of the comparison circuit is stable;
the storage unit selection circuit and the comparison circuit form a current loop through the charging circuit, so that the comparison circuit outputs a high level or a low level according to the current loop;
the output end of the comparison circuit is used as the output end of the nonvolatile memory detection circuit;
the charging circuit includes:
NMOS transistors M1, M2, M3, a first power supply VDD;
the drain of the M1 is connected with the first power supply VDD;
the source of the M1 is connected with the drain of the M3 to serve as a connection end of the charging circuit and the comparison circuit for charging the comparison circuit;
the drain of the M2 is connected with the first power supply VDD;
the source of the M2 is connected to the source of the M3 to act as a connection for the charging circuit to the memory cell selection circuit to charge the memory cell selection circuit.
2. The circuit of claim 1, wherein the compensation circuit comprises:
an NMOS transistor M5, a second power supply VCC, a third power supply module VPRE;
the gate of the M5, the drain of the M5, and the gate of the M1 are connected to the second power VCC;
the source of the M5 is connected to the third power supply module VPRE.
3. The circuit of claim 2, wherein the compensation circuit further comprises:
an NMOS transistor M6; the gate of the M6 and the drain of the M5 are connected to the third power supply module VPRE.
4. The circuit of claim 3, wherein the comparison circuit comprises:
a comparator, a first input terminal of which is provided with a comparison voltage VTH, and a second input terminal of which is connected with the source of the M1 to receive the charging voltage of the charging circuit;
a second input terminal of the comparator is connected with the drain of the M3 to form a current loop with the memory cell selection circuit through the M3;
and the first end of the capacitor C is connected with the second input end of the comparator, and the second end of the capacitor C is grounded.
5. The circuit of claim 4, wherein the memory cell selection circuit comprises:
an NMOS transistor M4, a memory cell determination module;
the drain of the M4 is connected with the source of the M3;
the source of the M4 is connected to the output of the memory cell determination module.
6. A nonvolatile memory sensing method applied to the nonvolatile memory sensing circuit according to any one of claims 1 to 4, the method comprising:
determining a memory cell to be detected in the memory cell selection circuit;
charging the memory cell selection circuit by the charging circuit;
when the storage unit selection circuit is stably charged, the second input end of the comparison circuit is charged through the charging circuit; a first input end of the comparison circuit is provided with a comparison voltage VTH;
when the charging of the second input end of the comparison circuit is stable, the charging of the storage unit selection circuit and the comparison circuit is finished, and the storage unit selection circuit and the comparison circuit form a current loop by controlling the charging circuit;
and determining the data state of the memory cell to be detected according to the current loop.
7. The method of claim 6, wherein the charging circuit comprises: an NMOS transistor M2;
the step of charging the memory cell selection circuit by the charging circuit includes:
and controlling M2 of the charging circuit to be conducted to charge the storage unit selection circuit.
8. The method of claim 6, wherein the charging circuit comprises: an NMOS transistor M1;
the step of charging the second input terminal of the comparison circuit through the charging circuit after the charging of the memory cell selection circuit is stable comprises:
and when the charging of the storage unit selection circuit is stable, controlling the M1 of the charging circuit to be conducted, and charging the second input end of the comparison circuit.
9. The method of claim 6, wherein the charging circuit comprises: an NMOS transistor M3;
the step of making the memory cell selection circuit and the comparison circuit constitute a current loop by controlling the charging circuit includes:
and controlling M3 of the charging circuit to be conducted, so that the storage unit selection circuit and the comparison circuit form a current loop.
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| CN1271945A (en) * | 1999-04-26 | 2000-11-01 | 日本电气株式会社 | Non volatile semiconductor memory |
| CN1469392A (en) * | 2002-06-28 | 2004-01-21 | ���ǵ�����ʽ���� | Ternary content addressable memory |
| CN1484248A (en) * | 2002-08-07 | 2004-03-24 | ������������ʽ���� | Reading circuit and semiconductor memory device including same |
| CN1707696A (en) * | 2004-06-10 | 2005-12-14 | 富士通株式会社 | Memory device |
| CN1747062A (en) * | 2004-08-04 | 2006-03-15 | 松下电器产业株式会社 | Semiconductor memory device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| KR100559714B1 (en) * | 2004-04-19 | 2006-03-10 | 주식회사 하이닉스반도체 | NAND flash memory device and method of programming the same |
| JP4908149B2 (en) * | 2006-10-18 | 2012-04-04 | 株式会社東芝 | NAND flash memory |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN1271945A (en) * | 1999-04-26 | 2000-11-01 | 日本电气株式会社 | Non volatile semiconductor memory |
| CN1469392A (en) * | 2002-06-28 | 2004-01-21 | ���ǵ�����ʽ���� | Ternary content addressable memory |
| CN1484248A (en) * | 2002-08-07 | 2004-03-24 | ������������ʽ���� | Reading circuit and semiconductor memory device including same |
| CN1707696A (en) * | 2004-06-10 | 2005-12-14 | 富士通株式会社 | Memory device |
| CN1747062A (en) * | 2004-08-04 | 2006-03-15 | 松下电器产业株式会社 | Semiconductor memory device |
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