CN110716888A - Method for realizing AXI bus cache mechanism - Google Patents
Method for realizing AXI bus cache mechanism Download PDFInfo
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- CN110716888A CN110716888A CN201910924985.XA CN201910924985A CN110716888A CN 110716888 A CN110716888 A CN 110716888A CN 201910924985 A CN201910924985 A CN 201910924985A CN 110716888 A CN110716888 A CN 110716888A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1668—Details of memory controller
- G06F13/1673—Details of memory controller using buffers
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/382—Information transfer, e.g. on bus using universal interface adapter
- G06F13/385—Information transfer, e.g. on bus using universal interface adapter for adaptation of a particular data processing system to different peripheral devices
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4063—Device-to-bus coupling
- G06F13/4068—Electrical coupling
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Abstract
The invention discloses a method for realizing an AXI bus cache mechanism, which is characterized in that a cache is added at an AXI slave device end, the cache consists of a plurality of cache lines with the same size, each cache line comprises a cache address and cache data, a CFG module is arranged for configuring the cache and registering configuration information, and the cache address is provided with an address operation module for realizing the matching of a transmission address and data and judging whether all data which are transmitted once can be provided from the cache; when the CACHE CACHEs data, normal operation is not influenced, when the CACHE hits CACHE, the CACHE can directly reply the data from the CACHE without initiating operation to SLAVE, so that the reading efficiency of small-batch data is greatly improved, the transmission efficiency of an AXI bus is greatly improved, and the optimized transmission with high bandwidth and low response delay is realized.
Description
Technical Field
The invention relates to a method for realizing an AXI bus caching mechanism, belonging to the technical field of AXI buses.
Background
The AXI system bus is a controller in the AXI bus system, connects a plurality of AXI MASTER devices to a plurality of AXI slave devices, and realizes address and data transmission among a plurality of memory-mapped devices. At present, a system bus mostly adopts a single-address channel multi-data channel mode, MASTER MASTER equipment initiates a write transmission application, an address decoder determines that the write transmission application needs to be transmitted to a certain SLAVE SLAVE equipment, the SLAVE receives a write command and write data, and after data transmission is completed, a write response is returned. The MASTER MASTER device initiates a read transmission application, determines that the application needs to be transmitted to a certain SLAVE SLAVE device through an address decoder, and the SLAVE receives a read command and returns read data and a read response. In the method, read-write transmission in an AXI system bus can only be accessed one by one, and after one-time transmission is completed, the next-time transmission can be started, so that the defects of single mode, narrow application range, inflexibility and low data transmission efficiency exist. Especially, when the MASTER initiates multiple read-write transmission applications, and the access addresses are repeated or continuous, the transmission needs to be initiated again, the SLAVE access times are increased, and a large number of clock cycles are wasted.
Disclosure of Invention
The invention aims to solve the technical problem of providing an AXI bus cache mechanism, and the method adds a cache with configurable capacity and high access speed at a SLAVE end, can effectively reduce SLAVE access, improves the data transmission efficiency of the AXI bus, and does not influence normal transmission.
In order to solve the technical problem, the technical scheme adopted by the invention is as follows: a method for realizing an AXI bus cache mechanism comprises the steps that a cache is added at an AXI slave device end, the cache is composed of a plurality of cache lines with the same size, the cache lines are basic operation units of the cache, each cache line comprises a cache address at a high position and a cache data at a low position, the cache addresses are used for caching addresses, the cache data are used for caching data, a CFG module is arranged for configuring the cache and registering configuration information, the cache addresses are provided with address operation modules used for realizing matching of transmission addresses and the data, whether all data which are transmitted in one-time reading mode can be provided from the cache or not is judged, and cache hit signals are sent out; when the main device initiates write transmission, a write address channel and a write data channel which are sent to a slave machine are respectively introduced into a cache, for transmission meeting configuration conditions, address and data caching operation can be carried out, when the main device initiates read transmission, the read address channel is introduced into the cache, when the data of the operation cannot be completely provided by the cache, the cache cannot hit, the data is read from the slave machine, the address is operated according to an instruction format and then is registered, when the channel data to be read arrives, cache line is combined with the corresponding address to complete caching, if all the data of the operation can be provided by the cache, the cache hits, the cache immediately sends a hit signal, the read instruction is intercepted to be sent to the slave machine, under the condition of hit, the read instruction is provided by the read data cache, and the read response after the data reply is sent by the cache at the same time, and the read transmission is completed.
Further, the information configured by the CFG module for the cache includes a threshold of the cache, a width of a cache address in a cache line, a width of cache data, and a depth of the cache.
Further, the process of the address operation module for matching the transmission address and the data is as follows: according to an AXI protocol, sequentially calculating all address information in a transmission process according to an awburst/awsize signal or an arburst/arsize signal transmitted for one time, corresponding to transmission data, judging whether all data read for one time can be provided by a cache or not, introducing an instruction into a slave-facing module and introducing the instruction into an address operation module, simultaneously calculating all addresses related to the transmission process by the address operation module according to the arburst/arsize signal, when the addresses exist in the cache, the cache hits, the instruction sent to the slave-facing module is intercepted, the data and response are provided by the cache module, otherwise, the instruction normally enters the slave-facing module, and the cache monitors data returned by the slave from a bypass, so as to finish the cache of the corresponding address and data.
Further, when the master device initiates write transmission, the determination process of transmission that meets the configuration condition is as follows: the data volume of one-time transmission is less than or equal to the configured cache threshold.
Furthermore, the cache address takes bit as the minimum unit, and the cache data takes byte as the minimum unit.
Further, cache addresses correspond to cache data one to one.
Further, the size of the cache address is configured according to the bit width of an address bus of the interconnect, and the size of the cache data is configured according to the bit width of a data bus of the interconnect.
Further, the method is applied to BURST or WRAP transmission of the AXI bus.
Furthermore, each updating of the cache is carried out by taking the cache line as a basic operation unit, the updating of the cache line is circularly carried out according to a pointer mode, and the cache line with the longest storage time in the cache is always updated.
The invention has the beneficial effects that: the cache of the cache with configurable capacity and high access speed is added at the slave end of the bus controller, the design area is increased controllably, the access to the slave can be effectively reduced, and the data transmission efficiency of the AXI bus is improved; the size of the cache line can be matched, the size of the burst of the cache can be matched, and the customization requirements in practical application can be flexibly met; the cache operation does not interfere with normal transmission and does not influence the normal transmission; when the cache hits, the instruction interception can be immediately carried out, and the data are simultaneously replied, so that the additional clock overhead can not be increased. The working mode of the N-M system is further expanded, the MASTER MASTER device initiates reading operation of the same address for many times, data is directly read from the cache, the performance limit of repetitive transmission on a complex bus system is broken through, the transmission performance of the system bus is greatly improved, and the high-performance requirement of the system bus is met.
Drawings
FIG. 1 is a schematic diagram of an AXI bus N-M full interconnect caching mechanism with configurable functionality;
FIG. 2 is a schematic structural diagram of the cache;
FIG. 3 is a schematic diagram of cache operation during write transmission;
FIG. 4 is a diagram illustrating a read transfer miss cache operation;
FIG. 5 is a diagram illustrating a read transfer hit cache operation.
Detailed Description
The invention is further described with reference to the following figures and specific embodiments.
Example 1
In this embodiment, the method should be applied to an N-M mode of an AXI bus, as shown in fig. 1, where the N-M mode refers to connecting multiple (M) AXI master devices to multiple (N) AXI slave devices, and implementing address and data transmission between multiple memory-mapped devices.
The method is characterized in that a cache memory is added at a slave end of an AXI system bus, cache operation is not performed on all transmission, the maximum burst transmission of the cache is allowed to be configured according to actual requirements, the capacity of the cache can also be configured, a module CFG special for configuring the cache is arranged, and the CFG can register configuration information and is used from each interface facing the slave.
As shown in fig. 2, the cache of the cache memory uses the cache line as a basic operation unit, and each update is performed by using the cache line as a basic operation unit. For the same cache, the cache lines are the same in size, each cache line is composed of a cache address and cache data, the cache address is used for caching an address, bit is used as a minimum unit, the cache data is used for caching data, byte is used as a minimum unit, the cache address and the cache data are respectively matched in size, and the cache line size is determined by the cache address and the cache data. In practical application, the size of cache data is configured according to the bit width of a data bus of the INTERCONNECT, the size of cache address is configured according to the bit width of an address bus of an AXI bus control kernel, and the cache data and the address bus are in one-to-one correspondence. The Cache address is attached with an address operation module which is used for realizing address and data matching of BURST transmission and judging whether all data transmitted by reading BURST at one time can be provided by the Cache, so that a Cache hit signal is sent out.
In this embodiment, the information that the CFG module configures the cache includes a threshold of the cache, a width of a cache address in a cache line, a width of cache data, and a depth of the cache.
The address operation module calculates all address information in the transmission process in sequence according to an AxI protocol and awburst/awsize signal or arburst/arsize signal transmitted at one time, and corresponding to the transmission data, judges whether all data read and transmitted at one time can be provided by the cache as an instruction and is introduced into the address operation module when the instruction is introduced into the slave-facing module, the address operation module simultaneously calculates all addresses related to the transmission process according to the arburst/arssize signal, when the addresses exist in the cache, the cache hits, the instruction sent to the slave-facing module is intercepted, the data and response are provided by the cache module, otherwise, the instruction normally enters the slave-facing module, and the cache monitors the data returned from the slave side by the bypass, and completes the cache of the corresponding address and data.
When the master device initiates write transmission, the judgment process of the transmission meeting the configuration condition is as follows: the data volume of one-time transmission is less than or equal to the configured cache threshold.
When the MASTER device initiates write transfer, as shown in fig. 3, a write address channel and a write data channel that are sent to S are respectively introduced into the bypass cache, and for transfer that meets configuration conditions, cache operation of addresses and instructions is performed.
When the MASTER main equipment initiates read transmission, a read address channel is introduced into a bypass cache, when the data of the operation cannot be completely provided from the cache, the cache cannot hit, as shown in FIG. 4, in this case, the data is read from a slave according to a normal flow, the normal read transmission is not influenced, the address is simultaneously operated according to an instruction format and then is registered, and when the data of the channel to be read comes, the cache line is combined with the corresponding address to update, so that the cache is completed; when all data of the operation can be provided by the cache, the cache hits, as shown in fig. 5, the cache immediately sends a hit signal to intercept the sending of the read instruction, no additional clock overhead is introduced to the read address channel in the operation, in the case of the hit, read data is provided by the cache, and the read response after the data reply is completed is sent by the cache at the same time to complete the read transmission.
Updating of the Cache line is carried out circularly according to the form of the pointer, and the Cache line with the longest storage time in the Cache is always updated.
In the embodiment, the cache of the cache memory is arranged at the slave end, and the slave is provided with the arbitration module, so that the arbitration expense of the cache can be saved. And the cache is a RAM memory, and the access speed is far higher than that of a memory with large capacity but low speed.
In this embodiment, the address and the data are placed in the same cache line (cache line), and when accessing the same cache line, a high-order matching system is adopted, so that the pointer does not need to be traversed, and the access speed is higher.
The foregoing description is only for the basic principle and the preferred embodiments of the present invention, and modifications and substitutions by those skilled in the art are included in the scope of the present invention.
Claims (9)
1. A method for implementing an AXI bus caching mechanism, comprising: the method comprises the steps that a cache memory is added at an AXI slave device end, the cache memory consists of a plurality of cache lines with the same size, the cache lines are basic operation units of the cache memory, each cache line comprises a cache address at a high position and a cache data at a low position, the cache addresses are used for caching addresses, the cache data are used for caching data, a CFG (computational fluid dynamics) module is arranged for configuring the cache and registering configuration information, the cache addresses are provided with address operation modules used for realizing the matching of transmission addresses and data, and judging whether all data which are transmitted once can be provided from the cache, so that a cache hit signal is sent out; when the master device initiates write transmission, a write address channel and a write data channel which are sent to a slave device are respectively introduced into a cache, for transmission meeting configuration conditions, cache operation of addresses and data is carried out, when the master device initiates read transmission, the read address channel is introduced into the cache, when the data of the operation cannot be completely provided by the cache, the cache cannot hit, the data is read from the slave device, the addresses are operated according to an instruction format and then are registered, when the data of the channel to be read arrives, cache line is updated by combining with the corresponding addresses, cache is completed, if all the data of the operation can be provided by the cache, the cache hits, the cache immediately sends a hit signal, the read instruction is intercepted to the slave device, under the condition of hit, the read data is provided by the cache, and the read response after the data reply is sent by the cache at the same time, and the read transmission is completed.
2. The method of implementing an AXI bus caching mechanism as claimed in claim 1, wherein: the information for the CFG module to configure the cache comprises the threshold value of the cache, the width of the cache address in the cache line, the width of the cache data and the depth of the cache.
3. The method of implementing an AXI bus caching mechanism as claimed in claim 2, wherein: the process of the address operation module for realizing the matching of the transmission address and the data comprises the following steps: according to the AXI protocol, sequentially calculating all address information in the transmission process according to an awburst/awsize signal or an arbburst/arsize signal transmitted at one time, corresponding to transmission data, writing into a cache line, and judging whether all data read and transmitted at one time can be provided from the cache by the following steps: when the addresses exist in the cache, the cache hits, the instruction sent to the slave-oriented module is intercepted, data and response are provided by the cache module, otherwise, the instruction normally enters the slave-oriented module, the cache monitors the data replied by the slave from a bypass, and the cache corresponding to the address and the data is completed.
4. The method of implementing an AXI bus caching mechanism as claimed in claim 1, wherein: when the master device initiates write transmission, the judgment process of the transmission meeting the configuration condition is as follows: the data volume of one-time transmission is less than or equal to the configured cache threshold.
5. The method of implementing an AXI bus caching mechanism as claimed in claim 1, wherein: the cache address takes bit as the minimum unit, and the cache data takes byte as the minimum unit.
6. The method of implementing an AXI bus caching mechanism as claimed in claim 1, wherein: and the cache addresses correspond to the cache data one by one.
7. The method of implementing an AXI bus caching mechanism as claimed in claim 1 or 6, wherein: the size of the cacheaddress is configured according to the bit width of an address bus of an AXI bus controller kernel, and the size of the cache data is configured according to the bit width of a data bus of the AXI bus controller kernel.
8. The method of implementing an AXI bus caching mechanism as claimed in claim 1, wherein: the method is applied to BURST or WRAP transmission of the AXI bus.
9. The method of implementing an AXI bus caching mechanism as claimed in claim 1, wherein: and each updating of the cache is carried out by taking the cache line as a basic operation unit, the updating of the cache line is circularly carried out according to a pointer mode, and the cache line with the longest storage time in the cache is always updated.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN111241024A (en) * | 2020-02-20 | 2020-06-05 | 山东华芯半导体有限公司 | Cascade method of full-interconnection AXI bus |
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