CN110716399A

CN110716399A - Photoresist removing method

Info

Publication number: CN110716399A
Application number: CN201910628837.3A
Authority: CN
Inventors: 萧忠仁; 陈雅萍; 林建宏; 刘文斌; 陈志文
Original assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Current assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority date: 2018-07-12
Filing date: 2019-07-12
Publication date: 2020-01-21
Anticipated expiration: 2039-07-12
Also published as: TW202032295A; US20200016635A1; US11654461B2; US11020778B2; CN110716399B; TWI740179B; US20210268555A1

Abstract

The present disclosure provides some photoresist removal methods. The photoresist removal method includes analyzing a process state of each of a plurality of semiconductor substrate models being subjected to a test plasma ashing process by a residual gas analyzer. A test plasma ashing process for a semiconductor substrate model uses a plurality of test recipes; the photoresist removal method further includes selecting one of the test recipes as a process recipe based on the analysis result of the residual gas analyzer and at least one expected performance criterion. In addition, the photoresist removing method includes performing a plasma ashing process on the semiconductor substrate according to the process recipe to remove the photoresist layer from the semiconductor substrate.

Description

Photoresist removing method

Technical Field

The embodiment of the disclosure relates to a photoresist removing method.

Background

Semiconductor devices have been widely used in various electronic products such as personal computers, cellular phones, digital cameras, and other electronic devices. Semiconductor devices are typically fabricated by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor layers of materials on a semiconductor substrate, and patterning the various material layers using photolithographic techniques to form circuit elements and devices on the semiconductor substrate.

In a photolithography process, light of a given frequency is used to transfer a desired pattern onto a semiconductor substrate (e.g., a silicon wafer) subjected to a semiconductor process. A mask (also known as a mask or reticle) is used to allow and prevent light in a desired pattern from reaching over a material layer of the wafer (e.g., a Photoresist (PR) layer) that chemically reacts to the exposure to remove portions of the photoresist layer and leave other portions. The remaining photoresist layer is then used to pattern the underlying layers. Because the photoresist material remaining on the wafer may cause defects in the manufactured semiconductor devices (e.g., integrated circuits), it is desirable that the photoresist layer be completely removed from the wafer (after patterning of the underlying layers) during processing of the wafer.

While existing photoresist removal apparatus and methods have been generally adequate for their intended purposes, they have not been entirely satisfactory in all respects.

Disclosure of Invention

The present disclosure provides some embodiments of a photoresist removal method. The photoresist removal method includes analyzing a process state of each of a plurality of semiconductor substrate models being subjected to a test plasma ashing process by a residual gas analyzer. A test plasma ashing process for a semiconductor substrate model uses a plurality of test recipes; the photoresist removal method further includes selecting one of the test recipes as a process recipe based on the analysis result of the residual gas analyzer and at least one expected performance criterion. In addition, the photoresist removing method includes performing a plasma ashing process on the semiconductor substrate according to the process recipe to remove the photoresist layer from the semiconductor substrate.

The present disclosure provides further embodiments of a photoresist removal method. The photoresist removing method includes performing a plasma ashing process on a semiconductor substrate in a photoresist removing apparatus to remove a photoresist layer from the semiconductor substrate. The photoresist removal method further includes detecting, by a residual gas analyzer, an ion signal associated with a selected type of gas molecule in a byproduct gas exhausted from the photoresist removal apparatus in the plasma ashing process. The photoresist removal method also includes comparing the ion signal detected at the selected time point to an expected ion signal associated with the selected time point. In addition, the photoresist removal method includes an operation based on the comparison to issue an indication of an alarm condition when the difference between the detected ion signal and the expected ion signal exceeds a range of acceptable values associated with the selected point in time.

The present disclosure provides further embodiments of a photoresist removal method. The photoresist removing method includes performing a plasma ashing process on a semiconductor substrate in a photoresist removing apparatus to remove a photoresist layer from the semiconductor substrate. The photoresist removal method further includes detecting, by a residual gas analyzer, an ion signal associated with a selected type of gas molecule in a byproduct gas exhausted from the photoresist removal apparatus in the plasma ashing process. The photoresist removal method also includes comparing the ion signal detected at the selected time point to a desired ion signal associated with the selected time point. In addition, the photoresist removal method includes adjusting a process parameter of the plasma ashing process when a difference exists between the detected ion signal and a desired ion signal associated with the selected point in time to align the detected ion signal with the desired ion signal.

Drawings

For a more complete understanding of the present disclosure and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which:

fig. 1A is a cross-sectional view of a semiconductor substrate at an intermediate stage in processing the substrate according to some embodiments.

Fig. 1B is a cross-sectional view of a semiconductor substrate at an intermediate stage in processing the substrate according to some embodiments.

Fig. 1C is a cross-sectional view of a semiconductor substrate at an intermediate stage in processing the substrate according to some embodiments.

Fig. 1D is a cross-sectional view of a semiconductor substrate at an intermediate stage in processing the substrate according to some embodiments.

Fig. 1E is a cross-sectional view of a semiconductor substrate at an intermediate stage in processing the substrate according to some embodiments.

Fig. 1F is a cross-sectional view of a semiconductor substrate at an intermediate stage in processing the substrate according to some embodiments.

FIG. 2 is a schematic diagram of a photoresist removal apparatus according to some embodiments.

Fig. 3 is a graph illustrating detection results of a residual gas analyzer during a plasma ashing process according to some embodiments.

FIG. 4 is a simplified flow diagram of a photoresist removal method according to some embodiments.

Fig. 5 illustrates a graph of detection results of a residual gas analyzer during multiple plasma ashing processes having different test recipes for a model of a semiconductor substrate, according to some embodiments.

FIG. 6 is a simplified flow diagram of a photoresist removal method for real-time (real-time) monitoring of a process using a residual gas analyzer, in accordance with some embodiments.

Fig. 7 is a graph illustrating a comparison between detected ion signals and expected ion signals during a plasma ashing process according to some embodiments.

FIG. 8 is a simplified flow diagram of a method of photoresist removal for real-time process monitoring defense using a residual gas analyzer, according to some embodiments.

Fig. 9 is a graph illustrating real-time calibration of ion signals during a plasma ashing process according to some embodiments.

Description of reference numerals:

100 substrate

110 dielectric layer (material layer)

120 bottom anti-reflection coating (material layer)

130 photo resist layer (mask)

140 opening

150 feature (groove)

160 reaction ion etching process

170 hard shell layer

180. 190 photoresist stripping process

200 photoresist removing equipment

201 processing chamber

202 substrate supporting device

203 heater

204 air inlet (pipe)

205 radio frequency power supply

206 outlet (Pumping line)

207 residual gas analyzer

208 control unit

400. 600, 800 photoresist removing method

410. 420, 430, 440, 610, 620, 630, 640, 650, 810, 820, 830, 840, 850 operations

P plasma

W semiconductor substrate

Detailed Description

The following disclosure provides many different embodiments, or examples, for implementing different features of the disclosure. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, forming a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed therebetween. The first and second features such that the first and second features may not be in direct contact. Additionally, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Furthermore, spatially relative terms, such as "below," "lower," "above," "upper," and the like, may be used herein to describe one element or feature's relationship to another element or feature(s) as illustrated for ease of description and for various orientations of the device in use or operation and the orientation depicted in the figures. When the device is turned to a different orientation (rotated 90 degrees or otherwise), the spatially relative adjectives used herein will also be interpreted in terms of the turned orientation.

In general, the present disclosure provides exemplary embodiments related to a method of removing a Photoresist (PR) layer from a semiconductor substrate and a photoresist removing apparatus for implementing the method. The method utilizes a Residual Gas Analyzer (RGA) disposed in the photoresist removal apparatus to assist in adjusting a recipe (recipe) (including a plurality of process parameters) for the photoresist removal process to reduce the time required to remove the entire photoresist layer from the semiconductor substrate and to reduce defects generated during the photoresist removal process. In some embodiments, the residual gas analyzer is also used to monitor the status of the photoresist removal process in real time during the photoresist removal process. Thus, large impacts due to tool etch rate shift or photoresist strip component anomalies can be avoided. This specification describes some variations of the embodiments. Like reference numerals are used for like elements in the various figures and illustrative embodiments.

Reference is made to fig. 1A-1F, which are cross-sectional views of a semiconductor substrate at various successive stages in processing the substrate, in accordance with some embodiments. Beginning with fig. 1A, in some embodiments, the semiconductor substrate 100 is a silicon substrate (e.g., a silicon wafer). However, the substrate 100 may also be a germanium substrate or comprise any other suitable material. In addition, the substrate 100 may include a compound semiconductor such as silicon carbide, gallium arsenide, indium arsenide, or indium phosphide. In addition, semiconductor arrangements such as silicon-on-insulator (SOI) and/or epitaxial layers may also be provided. The substrate 100 may also contain various active or passive components (not shown) such as transistors, diodes, resistors, capacitors, and other suitable components for integrated circuits.

A dielectric layer 110 is formed over the substrate 100. In some embodiments, the dielectric layer 110 may be, for example, a low-k fluorine-doped silicate glass (FSG), where k is the dielectric constant. However, the dielectric layer 110 may also include polyimide (polyimide), Black

(products of applied materials, Santa Clara, Calif.), xerogels (Xerogel), aerogels (Aerogel), amorphous fluorinated carbons (Amorphous fluorinated carbon), and/or any other suitable porous low dielectric constant material. In some embodiments, the dielectric layer 110 is formed on the substrate 100 by a Chemical Vapor Deposition (CVD) process. Alternatively, the dielectric layer 110 may be formed by low-pressure chemical vapor deposition (LPCVD), plasma-enhanced chemical vapor deposition (PECVD), high-density plasma chemical vapor deposition (HDPCVD), spin-on coating (spin coating), or other suitable processes.

In some embodiments, the dielectric layer 110 may be used as an inter-metal dielectric (IMD) layer or an inter-layer dielectric (ILD) layer to form interconnects between devices in the substrate 100. For simplicity and clarity, an intermetal dielectric layer is described herein. However, it should be understood that the integrated circuit to be fabricated may also include more than one intermetal dielectric layer and other insulating and metal layers for interconnecting active and passive components in the substrate 100.

In some embodiments, a bottom anti-reflective coating (BARC) 120 is formed on the dielectric layer 110 by any of any method, such as spin-on coating or Chemical Vapor Deposition (CVD). For example, the BARC layer 120 may be made of SiON. However, in some embodiments, the BARC layer 120 may also include silicon oxycarbide, silicon nitride, tantalum nitride, or any other suitable material.

A photoresist (mask) layer 130 is formed on the bottom anti-reflective coating 120. The photoresist layer 130 has an opening 140 therein that is patterned by a photolithography process (not shown). The photoresist layer 130 is patterned by a photolithography process exposing the photoresist layer 130 to a radiation source through a mask (or a reticle). In some embodiments, the photoresist layer 130 comprises a positive photoresist. Alternatively, the photoresist layer 130 may comprise a negative photoresist or other suitable material. The radiation source is a suitable light source, for example an ultraviolet (ultra-violet UV), Deep Ultraviolet (DUV), or Extreme Ultraviolet (EUV) radiation source. For example, the radiation source may be, but is not limited to, a mercury lamp with a wavelength of 436nm (G-line) or 365nm (I-line); krypton fluoride (KrF) excimer laser (eximer laser) with a wavelength of 248 nm; an argon fluoride (ArF) excimer laser having a wavelength of 193 nm; fluorine (F) having a wavelength of 157nm₂) Excimer laser; or other light sources having wavelengths below about 100 nm. In some embodiments, the photoresist layer 130 is developed by an alkaline developer to remove the exposed portions of the photoresist layer 130 and leave openings 140 in the photoresist layer 130. It should be understood that various techniques may be used to pattern the photoresist layer 130, and photolithography is only one example.

Referring to fig. 1B and 1C, a photoresist (mask) layer 130 having an opening 140 is used to form a feature 150 (e.g., a trench, see fig. 1C) in the dielectric layer 110. The opening 140 exposes a portion of the BARC layer 120. In some embodiments, a dry etching process (not shown) is performed to remove the exposed portion of the BARC layer 120, thereby forming an etched BARC layer. However, the BARC layer 120 may also be etched by a wet etch process, a chemical etch process, or other suitable processes. The trench 150 is then formed by a Reactive Ion Etching (RIE) process 160 performed on the dielectric layer 110. Alternatively, the trench may continue to be etched after the process for etching the BARC layer 120 or some other suitable type of removal process.

During the reactive ion etching of the dielectric layer 110, ion bombardment (ion bombardment) of the photoresist layer 130 hardens the outermost layer of the photoresist layer 130 and forms a crust layer (crust layer) 170. The crust layer 170 is difficult to dissolve and requires the use of aggressive chemicals to remove the photoresist layer 130. Accordingly, in some embodiments, a plasma ashing process is then performed on the photoresist layer 130 including the crust layer 170 to remove the entire photoresist layer from the substrate 100. In some embodiments, a plasma source is used to generate reactive species to form ash (ash) in combination with the photoresist layer, and then a vacuum pump is used to remove the ash. For example, the plasma ashing process can include a first plasma ashing process step and a second plasma ashing process step.

Referring to fig. 1D, in some embodiments, a first plasma ashing process step is performed to remove the hardened crust layer 170 over the photoresist layer 130. The first plasma ashing process step, for example, includes a photoresist strip process 180. In some embodiments, the photoresist strip process 180 utilizes an etch chemistry (which may generate reactive species or etch species when converted to a plasma) and etch conditions suitable to soften and remove the crust layer 170. For example, the etch chemistry includes a fluorine-containing gas (e.g., CF)₄) Oxygen-containing gas (e.g. O)₂) Nitrogen-containing gas (e.g. N)₂H₂) Other suitable gases, or combinations thereof.

Referring to fig. 1E, in some embodiments, a second plasma ashing process step is performed to remove remaining portions of the photoresist layer. For example, the second plasma ashing process step removes the photoresist layer 130 and any remaining hardened crust layer 170. The second plasma ashing process step may include a photoresist strip process 190. In some embodiments, the photoresist strip process 190 utilizes an etch chemistry (which when converted to a plasma may generate reactive species or etch species) and etch conditions suitable to remove the remaining portions of the photoresist layer. For example, the etching chemistry includes an oxygen-containing gas (e.g., oxygen-containing gas)Such as O₂) Nitrogen-containing gas (e.g. N)₂H₂) Other suitable gases, or combinations thereof. In some embodiments, the photoresist strip process 180 and the photoresist strip process 190 implement different etch conditions (e.g., temperature, chamber pressure, and Radio Frequency (RF) power, etc.).

It should be understood that the plasma ashing process may also include additional plasma ashing process steps (not shown) after the first and second electrochemical ashing process steps. The additional plasma ashing process step serves to remove byproducts generated during the plasma ashing process from the substrate 100. The additional plasma ashing process step includes a photoresist strip process that utilizes an etch chemistry that can generate reactive species or etching species when converted to plasma and etch conditions suitable for the substrate 100 to remove byproducts generated during the plasma ashing process without damaging the low dielectric constant dielectric layer 110. For example, the etching chemistry includes an oxygen-containing gas (e.g., O)₂) Nitrogen-containing gas (e.g. N)₂) Other suitable gases, or combinations thereof. In some embodiments, the etch conditions (e.g., temperature, chamber pressure, and Radio Frequency (RF) power, etc.) for the additional plasma ashing process step are different from the etch conditions for the second plasma ashing process step.

The remaining patterned photoresist layer 130 is completely removed from the substrate 100 using the above-described plasma ashing process, as shown in fig. 1F. The substrate 100 may be subjected to subsequent processing steps (not shown) to complete the formation of the metal interconnects, such as filling the trenches 150 with a conductive copper layer and planarizing the conductive and dielectric layers 110.

Reference is made to fig. 2, which schematically illustrates some elements of a photoresist removal apparatus 200, in accordance with some embodiments. The photoresist removal apparatus 200 is configured to perform a plasma ashing process (e.g., the plasma ashing process described above) to remove the remaining patterned photoresist layer from the semiconductor substrate. It should be noted that some additional elements may be added to photoresist removal apparatus 200 in FIG. 2, and some elements described below may be replaced or eliminated in other embodiments of photoresist removal apparatus 200.

The photoresist removal apparatus 200 includes a process chamber 201 (also referred to as a plasma chamber) having a substrate support device 202 in the process chamber 201. The substrate support apparatus 202 is configured to support a semiconductor substrate W during a photoresist removal process (i.e., a plasma ashing process). For example, the semiconductor substrate W may include a substrate 100 and patterned material layers 110, 120, a patterned photoresist layer 130, and a crust layer 170 formed on the substrate 100, as shown in fig. 1C. In some embodiments, the substrate support apparatus 202 is an electrostatic chuck (ESC) that may use electrostatic force to hold the semiconductor substrate W. However, the substrate support apparatus 202 may also use mechanical, vacuum, or other clamping techniques to hold the semiconductor substrate W.

Further, the heater 203 is configured to heat the substrate support apparatus 202 so that the temperature of the semiconductor substrate W on the substrate support apparatus 202 is maintained within a range suitable for the plasma ashing process. In some embodiments, the temperature of the plasma ashing process is in a range from about 190 degrees to about 210 degrees.

Various process gases (e.g., CF) are introduced through one or more gas inlets 204 (e.g., conduits) as required by the plasma ashing process₄、O₂、N₂H₂、N₂Etc.) into the process chamber 201. Although not shown, each conduit 204 is connected to a gas source, and a (throttle) valve is provided on the respective conduit 204 to control the gas flow rate in the conduit 204. A plasma P including a plurality of ions is generated in the processing chamber 201 through a dissociation process (i.e., dissociating a process gas).

As shown in fig. 2, in some embodiments, a grounded chamber wall of the process chamber 201 serves as the first electrode. The substrate support apparatus 202 in the processing chamber 201 serves as a second electrode that is powered by a Radio Frequency (RF) power source 205. The first electrode and the second electrode form an electric field, and ions of the plasma P are accelerated by the electric field. During the plasma ashing process, the accelerated ions (also referred to as reactants or etch species) strike the unprotected surface of the semiconductor substrate W. Accordingly, atoms on the unprotected surface of the semiconductor substrate W are removed (dishedged) to remove a portion of the semiconductor substrate W (e.g., the crust layer 170 and/or the patterned photoresist layer 130 shown in fig. 1C-1E).

It should be noted that although fig. 2 illustrates a single radio frequency power source 205, in some embodiments the radio frequency power source 205 may include two separate radio frequency power sources, a high frequency radio frequency power source (high frequency RF source) and a low frequency radio frequency power source (low frequency RF source). A high frequency radio frequency power supply (not shown) is used to dissociate the process gas to generate the plasma P. On the other hand, a low frequency radio frequency power source (not shown) is mainly used to accelerate ions of the plasma P so that the ion bombardment energy of the plasma P can be adjusted to a level suitable for the etching process of different semiconductor layers. That is, to adjust the etch rate, the amplitude of the low frequency RF power supply may be adjusted accordingly.

The process chamber 201 may also include at least one gas outlet 206 (e.g., a pumping line). A large amount of by-product gas may be generated during the plasma ashing process. This by-product gas may be continuously removed by a vacuum pump (not shown) and through pumping line 206. Although not shown, in some embodiments, a (throttling) valve is disposed on the pumping line 206 to control the gas flow rate therein. By adjusting the gas flow rate in the gas inlet (conduit) 204 and the gas flow rate in the gas outlet (pumping line) 206, the chamber pressure within the process chamber 201 can be adjusted accordingly.

In the embodiment shown in fig. 2, the photoresist removal apparatus 200 further includes a Residual Gas Analyzer (RGA) 207. In some embodiments, a residual gas analyzer 207 may be installed on the pumping line 206 (e.g., on the pumping line 206 near the process chamber 201) and connected to and open to the process chamber 201 in order to monitor the status of the photoresist removal process in real time by analyzing the gas byproducts exhausted from the process chamber 201. In some embodiments, a qualitor Remote System (qualitor Remote System, based on a quadrupole mass spectrometer) is used as residual gas analyzer 207, but the present disclosure is not dependent on any particular type or design of mass spectrometer as long as it can operate successfully.

In general, quadrupole mass spectrometers are constructed with four conducting rods symmetrically distributed about a common axis. The pairs of opposing conductive rods are connected to Direct Current (DC) and rf voltage supplies. The gas to be analyzed is dissociated by standard means (e.g., a filament for dissociating the gas) in a dissociation region in front of the conductive rod, and the ions are then accelerated along a common axis of the conductive rod. For a given space between the centers of the conductive rods, the dc and rf voltages are selected to allow ions of a single mass (i.e., the E/M ratio (charge to mass ratio)) to oscillate in a stable trajectory to reach an ion detector located at the distal end of the conductive rods. While the trajectories of all other ions spiral outward and terminate at the surface of one of the conductive rods. The resolution of the ion mass is increased by increasing the frequency of the radio frequency. The sensitivity is controlled by varying the ratio of the dc to rf voltage. Ions are typically detected by electron multiplier tubes (electron multipliers) or Faraday cups (Faraday cups).

The ion detector of the residual gas analyzer 207 can detect an ion (current) signal of a gas molecule of a selected mass (in the byproduct gas from the process chamber 201) and convert the ion signal to a gas partial pressure through software processing. Accordingly, the residual gas analyzer 207 can be used to monitor the status of the photoresist removal process in real time during the plasma ashing process.

For example, referring to fig. 3, a graph illustrating detection results of the residual gas analyzer 207 during a plasma ashing process according to some embodiments. In this example, the residual gas analyzer 207 is operated to detect gas molecules (e.g., CO) of a selected mass in a byproduct gas generated during a plasma ashing process₂) The ion signal of (1). However, the selected and detected gas molecules in the by-product gas may be other suitable gases that may indicate the status of the photoresist removal process.

As can be seen from the detection results shown in fig. 3 (i.e., the change in the detected ion signal), the crust layer 170 (fig. 1D) is completely removed at point a (time) (also referred to as the crust opening point). It should be understood that when the process gas or plasma P removes the crust layer 170 and begins to become hardCO generated during the reaction of the photoresist layer 130 (FIGS. 1D-1E) under the shell 170₂The amount begins to gradually increase. Further, from the detection result shown in fig. 3, the (time) point B at which the remaining photoresist layer 130 is completely removed can be known. It is understood that when the remaining photoresist layer 130 is completely removed, CO is generated₂The amount will decrease or return to a relatively low level. Also, from the detection results shown in fig. 3, the period C of over-etching (or ashing), i.e., the time interval between the point B and the predetermined (plasma ashing) process endpoint, can be obtained.

It should be understood that the photoresist removal process is expected to have a short photoresist removal time and that defects generated during the photoresist removal process will be rare. The following embodiments provide a method for using the residual gas analyzer to assist in fine tuning the recipe (i.e., process parameters) of a photoresist removal process such that the time required for the photoresist removal process to remove an entire photoresist layer from a semiconductor substrate may be reduced and the resulting defects may be reduced.

Reference is made to fig. 4, which is a simplified flow diagram of a photoresist removal method 400 according to some embodiments. For illustration, this flow diagram will be described together with the schematic diagrams shown in fig. 2 and 5. Some of the operations described below may be replaced or eliminated in different embodiments. Or some operations may be added in different embodiments. The photoresist removal method 400 includes a number of operations (410, 420, 430, 440).

In operation 410, a plurality of semiconductor substrate models is first provided. The semiconductor substrate model (not shown) has the same structural configuration as the semiconductor substrate of the photoresist removal process (e.g., a semiconductor substrate W (fig. 2) including a substrate 100, patterned material layers 110, 120, a patterned photoresist layer 130, and a crust layer 170 formed on the substrate 100 as shown in fig. 1C). In some embodiments, in the case when a batch of semiconductor substrates formed by the same manufacturing method is to be subjected to a photoresist removal process, the first several semiconductor substrates are referred to as a semiconductor substrate model.

The semiconductor substrate models are then subjected to a "test" plasma ashing process as described above (e.g., as performed in the photoresist removal apparatus 200 shown in fig. 2) to remove the photoresist layer from each of the semiconductor substrate models. In some embodiments (as shown in fig. 5), the plasma ashing process includes a first plasma ashing process step, a second plasma ashing process step, and an additional plasma ashing process step. The functions of the first, second, and additional plasma ashing process steps have been previously described and are not described in detail herein.

In some embodiments, the recipe (including a set of process parameters, such as process gas type, gas flow rate, rf power, and chamber pressure, etc.) in the first plasma ashing process step is different from the recipe in the second plasma ashing process step. For example, the process gas provided in the first plasma ashing process step can include CF₄、O₂And N₂H₂And the process gas provided in the second plasma ashing process step can include O₂And N₂H₂. The gas flow rate in the first plasma ashing process step can be lower than the gas flow rate in the second plasma ashing process step. The rf power and chamber pressure in the first plasma ashing process step can be lower than the rf power and chamber pressure in the second plasma ashing process step.

In some embodiments, the recipe (including a set of process parameters, such as process gas type, gas flow rate, rf power, and chamber pressure, etc.) in the additional plasma ashing process step is different than the recipe in the second plasma ashing process step. For example, the process gas provided in the additional plasma ashing process step can include O₂And N₂And the process gas provided in the second plasma ashing process step can include O₂And N₂H₂. The gas flow rate in the additional plasma ashing process step can be lower than the gas flow rate in the second plasma ashing process step (but greater than the gas flow rate in the first plasma ashing process step). The rf power and chamber pressure in the additional plasma ashing process step may be lower than the second plasma ashing process stepRf power and chamber pressure during the step (but greater than the rf power and chamber pressure of the first plasma ashing process step).

A number of "test" plasma ashing processes for semiconductor substrate models use various "test" recipes. In some embodiments, the number of test recipes (e.g., three) corresponds to the number of semiconductor substrate models (e.g., three), i.e., one test recipe corresponds to one semiconductor substrate model. However, the number of test recipes may be less than the number of semiconductor substrate models, and each test recipe corresponds to several semiconductor substrate models. For example, some of the test recipes (each including a set of "test" process parameters) used in photoresist removal apparatus 200 (fig. 2) during a "test" plasma ashing process are shown in table 1.1 below.

TABLE 1.1

It should be noted that while the "test" plasma ashing processes described above having different test recipes for the semiconductor substrate model have the same length of processing time (associated with the first, second, and additional plasma ashing process steps (see fig. 5)), they are not so limited. For example, in various embodiments, the processing times of the first, second, and additional plasma ashing process steps of the plasma ashing process associated with the test recipe can be the same or different.

In operation 410, the process state of each semiconductor substrate model undergoing a "test" plasma ashing process using one of the test recipes (i.e., one set of test process parameters) shown in table 1.1 is analyzed using a residual gas analyzer (e.g., residual gas analyzer 207 shown in fig. 2). The residual gas analyzer 207 detects selected types of gas molecules (e.g., CO) in the byproduct gas generated during the "test" plasma ashing process with each semiconductor substrate model₂) Correlated ion signals to analyze in real time a semiconductor substrate during a photoresist removal processThe process state of the model. Referring back to fig. 2, the residual gas analyzer 207 is connected to a control unit 208 (e.g., a computer system). In some embodiments, the control unit 208 receives, stores, and displays the detection/analysis results from the residual gas analyzer 207 (see fig. 5) for the convenience of the operator.

From the detection results (i.e., the detected changes in ion signals) shown in fig. 5, it can be appreciated that each semiconductor substrate model is undergoing a process state for a "test" plasma ashing process using a test recipe (i.e., a set of test process parameters including process gas type, gas flow rate, rf power and chamber pressure, and processing time for each step in the plasma ashing process). The process states include a point of time (a1, a2, A3) at which the crust layer 170 over the patterned photoresist layer 130 is removed (also referred to as a crust opening point), a point of time (B1, B2, B3) at which the removal of the remaining patterned photoresist layer 130 is finished, and a period of over ashing (C1, C2, C3). Time point a1, time point B1, and period C1 correspond to formulation 1. Time point a2, time point B2, and period C2 correspond to formulation 2. Time point a3, time point B3, and period C3 correspond to formulation 3.

In operation 420, after the "test" plasma ashing process described above, each semiconductor substrate model is removed from the photoresist removal apparatus 200 for inspection (e.g., optical, electrical, or other type of inspection available) to account for defects that remain on the semiconductor substrate model during the "test" plasma ashing process. However, the inspection process may be performed in-situ (in-situ) by an inspection unit (not shown) provided with photoresist removal apparatus 200 to obtain the number of defects generated during the "test" plasma ashing process. The inspection unit may use optical, electrical or other available types of inspection mechanisms. The viewing results may be stored in a database (not shown) of the control unit 208. In some other embodiments, operation 420 may be omitted.

In operation 430, a test recipe is selected as the (expected) process recipe based on the detection/analysis results of the residual gas analyzer 207 and at least one expected performance criterion for the photoresist removal process. In some embodiments, the desired performance criteria include reducing the time required to remove the crust layer 170 (fig. 1D). In addition, the desired performance criteria include reducing the time required to remove the remaining patterned photoresist layer 130 (fig. 1D-1E). In addition, the desired performance criteria include a reduction in defects (e.g., unremoved debris of crust layer 170, photoresist layer 130, or other material layers, and over-etching) generated during the plasma ashing process. However, in some embodiments, the expected performance criteria may include one or both of the above expected performance criteria.

In some embodiments, the control unit 208 selects or decides a (desired) process recipe from the test recipes for the plasma ashing process by analyzing the results of the detection/analysis by the residue gas analyzer 207 during the plasma ashing process with various test recipes and the review results stored in the database. For example, in the embodiment illustrated in fig. 5, recipe 1 was selected as the (intended) process recipe for the subsequent plasma ashing process of the semiconductor substrate because time a1 precedes time a2 and A3, time B1 precedes time B2 and B3, and fewer defects are generated during the plasma ashing process using recipe 1 (not shown).

It should also be understood that the selected process recipe may include an appropriate length of processing time associated with each of the first, second, and additional plasma ashing steps to avoid overetching (e.g., during overetch C1 (fig. 5) is expected not to be too long).

In operation 440, a plasma ashing process is then performed on the semiconductor substrate (e.g., a later semiconductor substrate in the same batch as the semiconductor substrate model) according to the determined process recipe to remove the photoresist layer from the semiconductor substrate. Real-time monitoring with a residual gas analyzer, and a process recipe determined by the above operations, reduces the time required to remove the entire photoresist layer from the semiconductor substrate and generates fewer defects during the photoresist removal process (i.e., the plasma ashing process).

In addition, residual gas analyzer 207 (FIG. 2) can also be used for real-time monitoring of a defense (real-time monitor damage) during the plasma ashing process performed in photoresist removal apparatus 200 to avoid a large number of impacts caused by tool etch rate drift or abnormal photoresist conditions. FIG. 6 is a simplified flow diagram of a method 600 for photoresist removal using a residual gas analyzer for process real-time monitoring defense, according to some embodiments. For illustration, this flow diagram will be described with reference to the schematic diagrams shown in fig. 2 and 7. Some of the operations described below may be replaced or eliminated in different embodiments. Alternatively, some operations may be added in different embodiments. The photoresist removal method 600 includes a number of operations (610, 620, 630, 640, 650).

In operation 610, a (desired) process recipe for a plasma ashing process, including some plasma ashing process steps, is determined. In some embodiments, the process recipe for the plasma ashing process in the photoresist removal apparatus (e.g., photoresist removal apparatus 200 of fig. 2) is determined according to operations 410-430 (fig. 4) described above and will not be described herein.

Furthermore, in some embodiments, during a "test" plasma ashing process performed on the plurality of semiconductor substrate models described above (e.g., many semiconductor substrate models have been subjected to a "test" plasma ashing process with a (expected) process recipe) by the residual gas analyzer 207 when determining the (expected) process recipe for the plasma ashing process, data relating to ion signals associated with selected types of gas molecules in the byproduct gas exhausted from the photoresist removal apparatus is collected and stored in a database (not shown) of the control unit 208 (fig. 2). It should be understood that the data may be further processed prior to storing the data in the database. For example, an average of ion signals detected at each of a plurality of "test" plasma ashing processes for a plurality of semiconductor substrate models (note that, in a test plasma ashing process, the data for the ion signals are detected a plurality of times at regular time intervals (e.g., every 0.5 seconds)) can be calculated and stored in a database. Accordingly, an expected ion signal profile (e.g., see the profile shown in thin lines in fig. 7) representative of the ion signal profile/variation of a model of a semiconductor substrate during a "test" plasma ashing process utilizing a (expected) process recipe can be obtained from the database of the control unit 208.

Subsequently, in operation 620, a plasma ashing process is performed on the semiconductor substrate (which has the same structural configuration as the semiconductor substrate model described above) in the photoresist removal apparatus 200 to remove the photoresist layer from the semiconductor substrate. In some embodiments, this plasma ashing process uses the (desired) process recipe obtained in operation 610.

In operation 630, the residual gas analyzer 207 in the photoresist removal apparatus 200 is further configured to detect an ion signal associated with a selected type of gas molecules (the same as the selected type of gas molecules in operation 610) in the byproduct gas exhausted from the photoresist removal apparatus 200 during the plasma ashing process in operation 620. In some embodiments, the detection frequency (or time interval) of the residual gas analyzer 207 in operation 630 and operation 610 is the same. Accordingly, during the plasma ashing process in operation 620, an ion signal profile (e.g., the profile shown by the bold line in fig. 7) of the semiconductor substrate is detected and obtained by the residual gas analyzer 207 and then sent to the control unit 208 for further processing as described below.

In operation 640, the ion signal detected at the selected time point is compared to an expected ion signal associated with the selected time point. In some embodiments, a plurality of specific time points during the plasma ashing process are determined or selected prior to analyzing the detected ion signals obtained in operation 630. As shown in fig. 7, these time points include a time point a at which the crust layer 170 (fig. 1D) is expected to be removed, a time point B at which the residual photoresist layer 130 (fig. 1D to 1E) is expected to be removed, a time point CP after the time point a, and a time point CP' after the time point B.

It has been described previously how to determine time point a and time point B (e.g. by an operator or the control unit 208), and will not be described further herein. In some embodiments, point in time CP is a point in time at which the photoresist removal process may be negatively affected by delayed removal of crust layer 170. The point in time CP' is a point in time at which the photoresist removal process may be negatively affected by delayed removal of the photoresist layer 130. In some embodiments, the operator may decide the time interval between the time points a and CP and the time interval between the time points B and CP' based on experience or experimental results and set it into the control unit 208.

Next, a range of acceptable values associated with a selected point in time (e.g., point in time A, B, CP, or CP') of a difference between the detected ion signal and the expected ion signal during the plasma ashing process is determined. In some embodiments, the acceptable range of values may be a standard deviation of expected ion signals in each plasma ashing process for the plurality of semiconductor substrate models described above, which may be calculated by the control unit 208. Or in some embodiments, the operator may determine the range of acceptable values based on experience or experimental results and set it into the control unit 208.

After determining the particular point in time and determining the range of acceptable values associated with the selected point in time during the plasma ashing process, the control unit 208 compares the ion signal detected by the residual gas analyzer 207 in operation 630 with the expected ion signal associated with the selected point in time from the database to determine whether the difference therebetween is outside the range of acceptable values associated with the selected point in time.

After the comparison is made, if the difference between the detected ion signal and the expected ion signal is within the range of acceptable values, the method 600 repeats operations 620 through 640 until the plasma ashing process is complete. However, if the difference between the detected ion signal and the expected ion signal exceeds the range of acceptable values associated with the selected point in time, the method 600 proceeds to operation 650 where an indication of an alarm condition is issued. For example, as shown in fig. 7, at time point CP, the detected ion signal is less than the range of acceptable values (e.g., one or more standard deviations) of the expected ion signal, or at time point CP', the detected ion signal is greater than the range of acceptable values (e.g., one or more standard deviations) of the expected ion signal, i.e., the difference between the detected ion signal and the expected ion signal is outside the range of acceptable values.

In some embodiments, the control unit 208 triggers an alarm when the control unit 208 indicates that the detected ion signal has deviated from the expected ion signal (in other words, when the control unit 208 detects an abnormality in the plasma ashing process). In some embodiments, it has been found that anomalies in plasma ashing processes can be caused by tool etch rate drift (e.g., exhibiting behavior related to process gas leakage or to rf power drift) or abnormal photoresist conditions. Accordingly, to protect the photoresist removal apparatus 200 or the semiconductor substrate W from damage, the control unit 208 may trigger an alarm and notify an operator to stop the process performed by the photoresist removal apparatus 200, take other actions, or a combination thereof. Accordingly, any problems of the photoresist removing apparatus 200 or the semiconductor substrate W can be identified and repaired to avoid a reduction in the yield of the photoresist removing process.

FIG. 8 is a simplified flow diagram of another photoresist removal method 800 for real-time process monitoring defense using a residual gas analyzer, in accordance with some embodiments. The photoresist removal method 800 includes a number of operations (810, 820, 830, 840, 850). It should be understood that

operations

810, 820, 830 of method 800 are the same as or similar to

operations

610, 620, 630 of method 600 described above and will not be described again here.

In operation 840, the ion signal detected at the selected time point is compared to an expected ion signal associated with the selected time point. In some embodiments, the selected time point may be each time point detected by residual gas analyzer 207 (fig. 2). However, in some embodiments, the selected time points may also include a plurality of specific time points during the plasma ashing process, such as time points A, B, CP, and CP' shown in fig. 7.

In some embodiments, the control unit 208 compares the ion signal detected by the residual gas analyzer 207 in operation 830 with an expected ion signal from the database associated with a selected time point (e.g., each detected time point) to determine if the difference between them is outside of an acceptable range of values associated with the selected time point.

After the comparison, if there is no difference between the detected ion signal and the expected ion signal, the method 800 repeats operations 820-840 until the plasma ashing process is complete. If, however, there is a difference between the detected ion signal and the expected ion signal at a selected point in time (e.g., circled point P in fig. 9), the method 800 continues to operation 850 where a real-time correction process is performed.

A real-time calibration process is performed by adjusting the process recipe for the current ashing process step of the plasma ashing process to calibrate the detected ion signals to the desired ion signals in real time, i.e., to eliminate differences therebetween. In some embodiments, the adjustable process recipe includes a gas flow rate, a radio frequency power, and/or a chamber pressure used in the photoresist removal apparatus. For example, when the detected ion signal is lower than the expected ion signal (indicating that the etch rate may be lower than the expected value), the control unit 208 (fig. 2) may control and appropriately increase the at least one process parameter to increase the etch rate. When the detected ion signal is greater than the expected ion signal (indicating that the etch rate may be greater than the expected value), the control unit 208 may control and appropriately reduce at least one process parameter to decrease the etch rate. Accordingly, desired process conditions are maintained during the plasma ashing process, thereby improving the yield of the photoresist removal process.

It should be noted that the method 800 is merely an illustrative example, and some of the operations described above may be replaced or eliminated in different embodiments. Or some operations may be added in different embodiments. For example, if the difference between the detected ion signal and the expected ion signal is found to become larger and larger at several consecutive detection time points (i.e., the difference cannot be successfully calibrated), the control unit 208 may further trigger an alarm and notify the operator to stop the process performed by the photoresist removal apparatus 200, take other movements or combinations thereof to identify and repair any problems with the photoresist removal apparatus 200 or the semiconductor substrate W, thereby avoiding a reduction in the yield of the photoresist removal process.

Embodiments of the present disclosure have some advantageous features: by providing a Residual Gas Analyzer (RGA) in the photoresist removal apparatus to help adjust the process recipe for the photoresist removal process, the time required to remove the entire photoresist layer from the semiconductor substrate is reduced and defects generated during the photoresist removal process are reduced (i.e., yield and yield are improved). In addition, the residual gas analyzer may also be used to monitor the status of the photoresist removal process in real time during the photoresist removal process, thereby avoiding a large number of impacts caused by tool etch rate drift or photoresist strip component anomalies.

The present disclosure provides some embodiments of a photoresist removal method. The photoresist removal method includes analyzing a process state of a test plasma ashing process performed to each of the semiconductor substrate models using a residual gas analyzer. A test plasma ashing process for a semiconductor substrate model uses a plurality of test recipes. The photoresist removal method also includes selecting one of the test recipes as a process recipe based on results of an analysis operation derived from the residual gas analyzer and at least one expected performance criterion. In addition, the photoresist removing method includes performing a plasma ashing process on the semiconductor substrate according to the process recipe to remove the photoresist layer from the semiconductor substrate.

The present disclosure provides further embodiments of a photoresist removal method. The photoresist removing method includes performing a plasma ashing process on the semiconductor substrate in the photoresist removing apparatus to remove the photoresist layer from the semiconductor substrate. The photoresist removal method further includes detecting, by a residual gas analyzer, an ion signal associated with a selected morphology of gas molecules of a byproduct gas generated from the photoresist removal apparatus during the plasma ashing process. The photoresist removal method also includes comparing the ion signal detected at the selected time point to an expected ion signal associated with the selected time point. In addition, the photoresist removal method includes and based on the comparison operation, issuing an indication of an alarm condition when the difference between the detected ion signal and the expected ion signal exceeds a range of acceptable values associated with the selected point in time.

The present disclosure provides further embodiments of a photoresist removal method. The photoresist removing method includes performing a plasma ashing process on a semiconductor substrate in a photoresist removing apparatus to remove a photoresist layer from the semiconductor substrate. The photoresist removal method further includes detecting, by a residual gas analyzer, an ion signal associated with a selected morphology of gas molecules of a byproduct gas generated from the photoresist removal apparatus during the plasma ashing process. The photoresist removal method also includes comparing the ion signal detected at the selected time point to a desired ion signal associated with the selected time point. In addition, the photoresist removal method includes adjusting a process parameter of the plasma ashing process when a difference exists between the detected ion signal and a desired ion signal associated with the selected point in time to align the detected ion signal with the desired ion signal.

In the photoresist removal method according to some embodiments of the present disclosure, the analyzing includes detecting, by a residual gas analyzer, an ion signal associated with a selected type of gas molecule in a byproduct gas generated in the test plasma ashing process. In some embodiments, the process state includes a point in time to remove a crust layer over a photoresist layer on a semiconductor substrate model, a point in time to end the removal of the photoresist layer, and a period of excessive ashing. In some embodiments, the at least one expected performance criterion includes reducing a time required to remove a crust layer on the semiconductor substrate model. In some embodiments, the at least one desired performance criterion includes reducing a time required to remove a photoresist layer on the semiconductor substrate model. In some embodiments, the at least one desired performance criterion includes reducing defects generated on the semiconductor substrate module during the test plasma ashing process.

The photoresist removal method as described in some embodiments of the present disclosure, further comprising inspecting each of the semiconductor substrate models after the test plasma ashing process to determine a number of defects generated in the test plasma ashing process. In some embodiments, the process recipe includes a set of process parameters including process gas type, gas flow rate, rf power, chamber pressure, and processing time. In some embodiments, the plasma ashing process includes a first plasma ashing process step and a second plasma ashing process step, and the process recipe in the first plasma ashing process step is different from the process recipe in the second plasma ashing process step. In some embodiments, the plasma ashing process further includes an additional plasma ashing process step after the second plasma ashing process step, and the process recipe in the additional plasma ashing process step is different from the process recipe in the second plasma ashing process step.

The photoresist removal method according to some embodiments of the present disclosure, further comprising stopping operation of the photoresist removal apparatus upon an indication of an alarm condition. In some embodiments, the selected point in time is after a particular point in time, and the particular point in time is a point in time of a crust layer over the photoresist layer. In some embodiments, the selected point in time is after a particular point in time, and the particular point in time is a point in time at which the photoresist layer is expected to be removed. In some embodiments, the selected point in time is a point in time at which a crust layer on the photoresist layer is expected to be removed. In some embodiments, the selected time point is the time point at which the photoresist layer is expected to be removed. In some embodiments, the photoresist removal method further comprises collecting data relating to ion signals associated with selected types of gas molecules in the byproduct gas exhausted from the photoresist removal apparatus during the test plasma ashing process for the plurality of semiconductor substrate models, and storing the data in a database, wherein the desired ion signals are from the database.

In some embodiments of the photoresist removal method of the present disclosure, the process parameters include gas flow rate, rf power, and/or chamber pressure used in the photoresist removal apparatus. In some embodiments, the plasma ashing process includes a first plasma ashing process step and a second plasma ashing process step, and the selected point in time is in at least one of the first plasma ashing process step and the second plasma ashing process step.

Although the embodiments of the present disclosure and their advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the disclosure as defined by the appended claims. For example, one skilled in the art will readily appreciate that many of the features, functions, processes, and materials described herein may be varied while remaining within the scope of the present disclosure. Moreover, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, composition of matter, means, methods and steps described in the specification. As one of ordinary skill in the art will readily appreciate from the disclosure of the present disclosure, processes, machines, manufacture, compositions of matter, means, methods, or steps, presently existing or later to be developed that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein may be utilized according to the present invention. Or achieve substantially the same results as corresponding embodiments described herein according to the present disclosure. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods, or steps. In addition, each claim constitutes a separate embodiment, and combinations of various claims and embodiments are within the scope of the disclosure.

Claims

1. A photoresist removal method comprising:

analyzing, by a residual gas analyzer, a process status of each of a plurality of semiconductor substrate models undergoing a test plasma ashing process, wherein the test plasma ashing process for the semiconductor substrate models uses a plurality of test recipes;

selecting one of the test recipes as a process recipe based on the analysis results of the residual gas analyzer and at least one expected performance criterion; and

according to the process recipe, a plasma ashing process is performed on a semiconductor substrate to remove a photoresist layer from the semiconductor substrate.

2. The photoresist removal method of claim 1, wherein the analyzing comprises detecting, by the residual gas analyzer, an ion signal associated with a selected type of gas molecule in a byproduct gas generated in the test plasma ashing process.

3. The method of claim 1, wherein the process state comprises a point in time of removing a crust layer over the photoresist layer on the semiconductor substrate model, a point in time of ending the removal of the photoresist layer, and a period of over ashing.

4. The method of claim 1, wherein the process recipe comprises a set of process parameters including process gas type, gas flow rate, RF power, chamber pressure, and processing time.

5. The method of removing photoresist according to claim 4 wherein the plasma ashing process comprises a first plasma ashing process step and a second plasma ashing process step, and the process recipe in the first plasma ashing process step is different from the process recipe in the second plasma ashing process step.

6. A photoresist removal method comprising:

performing a plasma ashing process on a semiconductor substrate in a photoresist removal apparatus to remove a photoresist layer from the semiconductor substrate;

detecting, by a residual gas analyzer, an ion signal associated with a selected type of gas molecule in a byproduct gas exhausted from the photoresist removal apparatus during the plasma ashing process;

comparing the ion signal detected at a selected time point with a desired ion signal associated with the selected time point; and

based on the comparing, an indication of an alarm condition is issued when the difference between the detected ion signal and the expected ion signal exceeds a range of acceptable values associated with the selected time point.

7. The method of claim 6, wherein the selected time point is after a specified time point, and the specified time point is a time point at which a crust layer above the photoresist layer is expected to be removed.

8. The photoresist removal method of claim 6, further comprising:

collecting data relating to an ion signal associated with a selected type of gas molecule in the byproduct gas exhausted from the photoresist removal apparatus during a test plasma ashing process performed on a plurality of semiconductor substrate models; and

storing the data in a database, wherein the expected ion signal is from the database.

9. A photoresist removal method comprising:

adjusting a process parameter of the plasma ashing process when a difference exists between the detected ion signal and the desired ion signal associated with the selected point in time to align the detected ion signal with the desired ion signal.

10. The method of claim 9, wherein the plasma ashing process comprises a first plasma ashing process step and a second plasma ashing process step, and the selected point in time is in at least one of the first plasma ashing process step and the second plasma ashing process step.