CN110706398A - Magnetic signal identification circuit module compatible with world currency (paper money) - Google Patents
Magnetic signal identification circuit module compatible with world currency (paper money) Download PDFInfo
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- CN110706398A CN110706398A CN201810648833.7A CN201810648833A CN110706398A CN 110706398 A CN110706398 A CN 110706398A CN 201810648833 A CN201810648833 A CN 201810648833A CN 110706398 A CN110706398 A CN 110706398A
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- ZCJJIQHVZCFSGZ-UHFFFAOYSA-N 2,8-bis(diphenylphosphoryl)dibenzothiophene Chemical class C=1C=CC=CC=1P(C=1C=C2C3=CC(=CC=C3SC2=CC=1)P(=O)(C=1C=CC=CC=1)C=1C=CC=CC=1)(=O)C1=CC=CC=C1 ZCJJIQHVZCFSGZ-UHFFFAOYSA-N 0.000 claims abstract description 97
- 230000003321 amplification Effects 0.000 claims abstract description 23
- 238000003199 nucleic acid amplification method Methods 0.000 claims abstract description 23
- 238000004891 communication Methods 0.000 claims abstract description 13
- 239000003990 capacitor Substances 0.000 claims abstract description 8
- 238000001514 detection method Methods 0.000 abstract description 7
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- G—PHYSICS
- G07—CHECKING-DEVICES
- G07D—HANDLING OF COINS OR VALUABLE PAPERS, e.g. TESTING, SORTING BY DENOMINATIONS, COUNTING, DISPENSING, CHANGING OR DEPOSITING
- G07D7/00—Testing specially adapted to determine the identity or genuineness of valuable papers or for segregating those which are unacceptable, e.g. banknotes that are alien to a currency
- G07D7/04—Testing magnetic properties of the materials thereof, e.g. by detection of magnetic imprint
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Abstract
A compatible world currency (paper currency) magnetic signal identification circuit module which characterized in that: the magnetic signal identification circuit comprises a standard magnetic amplification circuit, a magnetic signal identification circuit, a communication circuit and a power supply circuit, wherein the power supply circuit is set to be VCC; the standard magnetic amplification circuit comprises an operational amplifier U1, resistors R '1 to R' 10, capacitors C '1 to C' 7, a protection resistor ESD, a magnetic sensor coil CC1 and an amplification signal output interface CN 1; the magnetic signal identification circuit is packaged by 40 pins and comprises an MCU chip U2, an operational amplifier IC U3, a DPDT analog switch chip U4, a U5, resistors R1 to R46 and capacitors C1 to C7; the invention aims to solve the technical problem of developing a magnetic detection circuit compatible with multinational paper money, quickening the period of developing new products and improving the quality of the products.
Description
Technical Field
The invention relates to the technical field of magnetic signal identification circuits, in particular to a magnetic signal identification circuit module compatible with world currency (paper money).
Technical Field
The magnetic signals on the paper money are acquired by a special magnetic sensor, and the acquired signals are too weak and need to be amplified by an operational amplifier. The existing paper money magnetic data decoding scheme generally integrates a magnetic signal acquisition and data decoding circuit in a main board of a paper money checking machine directly, performs signal saturation amplification through a three-stage operational amplifier, and performs signal identification through data acquisition through an MCU (microprogrammed control unit). The above-mentioned technology has the defects: when the magnetic signal is amplified to a saturation state, the original real information can be lost and identified as a power difference; in addition, 90% of the current currency counting machines in various countries in the world need to use magnetic detection sensors, different national currencies adopt different magnetic detection schemes, and no independent magnetic detection unit special circuit is compatible with multinational currencies, so that the magnetic detection scheme needs to be redesigned when a new currency counting machine needs to be developed, the development period is too long, and the paper currency identification rate is poor.
Disclosure of Invention
The invention aims to solve the technical problem of developing a magnetic detection circuit compatible with multinational paper money, quickening the period of developing new products and improving the quality of the products.
A magnetic signal identification circuit module compatible with currency (paper money) of various countries in the world is composed of a standard magnetic amplification circuit, a magnetic signal identification circuit, a communication circuit and a power supply circuit, wherein the power supply circuit is set to be VCC.
The standard magnetic amplification circuit comprises an operational amplifier U1, resistors R '1 to R' 10, capacitors C '1 to C' 7, a protection resistor ESD, a magnetic sensor coil CC1, and an amplified signal output interface CN 1; the 1 st pin and the 4 th pin of the magnetic sensor coil CC1 are identification points MAG _ IN-, and the 2 nd pin and the 3 rd pin of the magnetic sensor coil CC1 are identification points MAG _ IN +; one end of R1 is connected to VCC; one end of R ' 2 is grounded, and the other end of R ' 2 and the other end of R ' 1 are connected to form an identification point VREF 1; one end of the parallel connection of the C ' 1 and the protection resistor ESD is connected to the 1 st pin of the amplification signal output interface CN1, the other end of the parallel connection of the C ' 1 and the protection resistor ESD is connected to VCC and the 5 th pin of the amplification signal output interface CN1, the 3 rd and 4 th pins of the amplification signal output interface CN1 are grounded, and the 2 nd pin of the amplification signal output interface CN1 is connected in series with R ' 10 to form an identification point OUT; an identification point L1_ OUT is connected with one parallel end of the C '4 and R' 5 and then connected with the 1 st pin of the operational amplifier U1; the identification point MAG _ IN-is connected with the C '2 and R' 3 IN series and then is connected with the 2 nd pin of the operational amplifier U1 together with the other end of the C '4 and R' 5 IN parallel; the identification point VREF1 is connected to one end of the R '8, C' 5 in parallel; the identification point MAG _ IN + is connected with the 3 rd pin of the amplified signal output interface CN1 after being connected with the C '3 and R' 4 IN series and the other end of the R '8 and C' 5 IN parallel; the 4 th pin of the operational amplifier U1 is grounded; the identification point VREF1 is connected with the 5 th pin of the operational amplifier U1 after being connected with R' 7 in series; one end of the identification point L1_ OUT connected in series with C '6, R' 6, C '7 and R' 9 in parallel is connected with the 6 th pin of the operational amplifier U1 after being connected; the other ends of the C '7 and R' 9 parallel are connected to an identification point OUT and a 7 th pin of an operational amplifier U1; the 8 th pin of the operational amplifier U1 is connected to VCC.
The magnetic signal identification circuit is a 40-pin package and comprises an MCU chip U2, an operational amplifier IC U3, a DPDT analog switch chip U4, a U5, resistors R1 to R46 and capacitors C1 to C7.
The 1 st pin of the DPDT analog switch chip U4 is serially connected with the R10 and then set as the 1 st pin of the 40-pin package, the 15 th pin of the DPDT analog switch chip U4 is serially connected with the R11 and then set as the 2 nd pin of the 40-pin package, the 3 rd pin of the DPDT analog switch chip U4 is serially connected with the R12 and then set as the 3 rd pin of the 40-pin package, the 5 th pin of the DPDT analog switch chip U4 is serially connected with the R13 and then set as the 4 th pin of the 40-pin package, the 9 th pin of the DPDT analog switch chip U4 is serially connected with the R14 and then set as the 5 th pin of the 40-pin package, the 7 th pin of the DPDT analog switch chip U4 is serially connected with the R15 and then set as the 6 th pin of the 40-pin package, the 13 th pin of the DPDT analog switch chip U4 is serially connected with the R16 and then set as the 7 th pin of the 40-pin package, the 11 th pin of the DPDT analog switch chip U4 is serially connected with the R17 and then, the 6 th pin of the DPDT analog switch chip U4 is set as ground, the 16 th pin of the DPDT analog switch chip U4 is connected to the 7 th pin of the MCU chip U2, the 4 th pin of the DPDT analog switch chip U4 is connected to the 8 th pin of the MCU chip U2, the 8 th pin of the DPDT analog switch chip U4 is connected to the 9 th pin of the MCU chip U2, the 12 th pin of the DPDT analog switch chip U4 is connected to the 10 th pin of the MCU chip U2, the 2 nd pin of the DPDT analog switch chip U4 is connected to the 2 nd pin of the MCU chip U2 after being connected to the R5 in series, and the 10 th pin of the DPDT analog switch chip U4 is connected to the 3 rd pin of the MCU chip U2 after being connected to the R6 in series.
The 1 st pin of the DPDT analog switch chip U5 is serially connected with the R19 and then set as the 9 th pin of the 40-pin package, the 15 th pin of the DPDT analog switch chip U5 is serially connected with the R20 and then set as the 10 th pin of the 40-pin package, the 3 rd pin of the DPDT analog switch chip U5 is serially connected with the R21 and then set as the 11 th pin of the 40-pin package, the 5 th pin of the DPDT analog switch chip U5 is serially connected with the R22 and then set as the 12 th pin of the 40-pin package, the 9 th pin of the DPDT analog switch chip U5 is serially connected with the R23 and then set as the 19 th pin of the 40-pin package, the 7 th pin of the DPDT analog switch chip U5 is serially connected with the R24 and then set as the 20 th pin of the 40-pin package, the 13 th pin of the DPDT analog switch chip U5 is serially connected with the R25 and then set as the 21 st pin of the 40-pin package, the 11 th pin of the DPDT analog switch chip U5 is serially connected with the R26 and then, the 6 th pin of the DPDT analog switch chip U5 is set as ground, the 16 th pin of the DPDT analog switch chip U5 is connected to the 11 th pin of the MCU chip U2, the 4 th pin of the DPDT analog switch chip U5 is connected to the 12 th pin of the MCU chip U2, the 8 th pin of the DPDT analog switch chip U5 is connected to the 13 th pin of the MCU chip U2, the 12 th pin of the DPDT analog switch chip U5 is connected to the 14 th pin of the MCU chip U2, the 2 nd pin of the DPDT analog switch chip U5 is connected to the 2 nd pin of the MCU chip U2 after being connected to the R7 in series, and the 10 th pin of the DPDT analog switch chip U5 is connected to the 3 rd pin of the MCU chip U2 after being connected to the R8 in series.
The 1 st pin, the 6 th pin, the 19 th pin and the 27 th pin of the MCU chip U2 are all connected to VCC, the 4 th pin of the MCU chip U2 is set as the 37 th pin of a 40-pin package, the 15 th pin of the MCU chip U2 is set as the 23 th pin of a 40-pin package after being connected with a series resistor R41, the 16 th pin of the MCU chip U2 is set as the 24 th pin of a 40-pin package after being connected with a series resistor R42, the 21 st pin of the MCU chip U2 is set as the 31 st pin of a 40-pin package after being connected with a series resistor R39, the 22 nd pin of the MCU chip U2 is set as the 32 th pin of a 40-pin package after being connected with a series resistor R40, the 23 th pin of the MCU chip U2 is connected to the 14 th pin of an operational amplifier ICU3 after being connected with a series resistor R34, the 24 th pin of the MCU chip U2 is connected to the 8 th pin of an operational amplifier IC 3, the 25 th pin of the MCU chip U2 is set as the 40 th pin of a series resistor R45, the U3639 th pin, a 29 th pin series resistor R35 of the MCU chip U2 is set as a 33 th pin of a 40-pin package, a 30 th pin series resistor R36 of the MCU chip U2 is set as a 34 th pin of the 40-pin package, a 31 st pin series resistor R37 of the MCU chip U2 is set as a 35 th pin of the 40-pin package, a 32 th pin series resistor R38 of the MCU chip U2 is set as a 36 th pin of the 40-pin package, a 33 th pin series resistor R33 of the MCU chip U2 is connected to a 7 th pin of the operational amplifier IC 3, a 34 th pin series resistor R31 of the MCU chip U2 is connected to a 1 st pin of the operational amplifier IC 3, a 35 th pin of the MCU chip U2 is set as a 40 th pin of the 40-pin package and grounded after the series resistor R43, and 18 th, 26 th and 36 th pins of the MCU chip U2 are all set as grounded; the 25 th pin of the 40 pin package is connected to VCC, and the 26 th pin of the 40 pin package is set to ground.
The 3 rd pin series resistor R27 of the operational amplifier IC U3 is set as the 27 th pin of a 40-pin package, the 4 th pin of the operational amplifier IC U3 is connected to VCC, the 12 th pin series resistor R28 of the operational amplifier IC U3 is set as the 28 th pin of the 40-pin package, the 6 th pin series resistor R32 of the operational amplifier IC U3 is set as the 29 th pin of the 40-pin package, the 10 th pin series resistor R29 of the operational amplifier IC U3 is set as the 30 th pin of the 40-pin package, and the 11 th pin of the operational amplifier IC U3 is set as ground.
One end of C2, C3, C4, C5, C6 and C7 which are connected in series is connected to VCC, and the other end of C2, C3, C4, C5, C6 and C7 which are connected in series is grounded; one end of R9 is connected with VCC, one end of C1 is grounded, and the other ends of R9 and C1 are connected with the 4 th pin of MCU chip U2; one ends of R1 and R2 are connected to the 5 th, 9 th and 13 th pins of an operational amplifier IC U3, one end of R, R4 is connected to the 2 nd pin of an operational amplifier IC U3, the other ends of R1 and R3 are connected to VCC, and the other ends of R2 and R4 are grounded.
Further, the communication circuit may employ one or more of a UART communication interface or an SPI communication interface.
Further, the power supply circuit supplies power for external connection at 3.3V.
Further, the MCU chip U2 selects an STM32F103 series microcontroller single chip microcomputer; the operational amplifier IC U3 selects an LM324 series operational amplifier; the DPDT analog switch chips U4 and U5 select DIO1466 analog switches.
The circuit provided by the circuit scheme of the invention can be universally used in magnetic signal acquisition and identification algorithm modules of currencies (paper money) of all countries in the world. 1. The signal is amplified to an unsaturated state by adopting a two-stage amplification circuit, the original paper currency magnetic number is collected, and the module identifies the denomination and the authenticity of the paper currency by analyzing the magnetic signal; 2. the magnetic waveform information is identified by adopting a module matching mode, so that the speed of developing a new currency is improved; 3. the number of the magnetic channels used by the national currencies of various countries is 18, and the circuit of the invention simultaneously supports 24-channel magnetic signal input and is compatible with the maximum magnetic channel.
Drawings
Fig. 1 is a schematic block diagram of the circuit of the present invention.
Fig. 2 is a circuit diagram of a standard magnetic amplifying circuit of the present invention.
Fig. 3 is a circuit diagram of a magnetic signal identifying circuit of the present invention.
Detailed Description
As shown in fig. 1, 2, and 3, the change in the circuit pins is a schematic designed network connection designation, with the same name designation being connected in the electrical sense.
A magnetic signal identification circuit module compatible with currency (paper money) of various countries in the world is composed of a standard magnetic amplification circuit, a magnetic signal identification circuit, a communication circuit and a power supply circuit, wherein the power supply circuit is set to be VCC.
The standard magnetic amplification circuit comprises an operational amplifier U1, resistors R '1 to R' 10, capacitors C '1 to C' 7, a protection resistor ESD, a magnetic sensor coil CC1, and an amplified signal output interface CN 1; the 1 st pin and the 4 th pin of the magnetic sensor coil CC1 are identification points MAG _ IN-, and the 2 nd pin and the 3 rd pin of the magnetic sensor coil CC1 are identification points MAG _ IN +; one end of R1 is connected to VCC; one end of R ' 2 is grounded, and the other end of R ' 2 and the other end of R ' 1 are connected to form an identification point VREF 1; one end of the parallel connection of the C ' 1 and the protection resistor ESD is connected to the 1 st pin of the amplification signal output interface CN1, the other end of the parallel connection of the C ' 1 and the protection resistor ESD is connected to VCC and the 5 th pin of the amplification signal output interface CN1, the 3 rd and 4 th pins of the amplification signal output interface CN1 are grounded, and the 2 nd pin of the amplification signal output interface CN1 is connected in series with R ' 10 to form an identification point OUT; an identification point L1_ OUT is connected with one parallel end of the C '4 and R' 5 and then connected with the 1 st pin of the operational amplifier U1; the identification point MAG _ IN-is connected with the C '2 and R' 3 IN series and then is connected with the 2 nd pin of the operational amplifier U1 together with the other end of the C '4 and R' 5 IN parallel; the identification point VREF1 is connected to one end of the R '8, C' 5 in parallel; the identification point MAG _ IN + is connected with the 3 rd pin of the amplified signal output interface CN1 after being connected with the C '3 and R' 4 IN series and the other end of the R '8 and C' 5 IN parallel; the 4 th pin of the operational amplifier U1 is grounded; the identification point VREF1 is connected with the 5 th pin of the operational amplifier U1 after being connected with R' 7 in series; one end of the identification point L1_ OUT connected in series with C '6, R' 6, C '7 and R' 9 in parallel is connected with the 6 th pin of the operational amplifier U1 after being connected; the other ends of the C '7 and R' 9 parallel are connected to an identification point OUT and a 7 th pin of an operational amplifier U1; the 8 th pin of the operational amplifier U1 is connected to VCC.
The magnetic signal identification circuit is a 40-pin package and comprises an MCU chip U2, an operational amplifier IC U3, a DPDT analog switch chip U4, a U5, resistors R1 to R46 and capacitors C1 to C7.
The 1 st pin of the DPDT analog switch chip U4 is serially connected with the R10 and then set as the 1 st pin of the 40-pin package, the 15 th pin of the DPDT analog switch chip U4 is serially connected with the R11 and then set as the 2 nd pin of the 40-pin package, the 3 rd pin of the DPDT analog switch chip U4 is serially connected with the R12 and then set as the 3 rd pin of the 40-pin package, the 5 th pin of the DPDT analog switch chip U4 is serially connected with the R13 and then set as the 4 th pin of the 40-pin package, the 9 th pin of the DPDT analog switch chip U4 is serially connected with the R14 and then set as the 5 th pin of the 40-pin package, the 7 th pin of the DPDT analog switch chip U4 is serially connected with the R15 and then set as the 6 th pin of the 40-pin package, the 13 th pin of the DPDT analog switch chip U4 is serially connected with the R16 and then set as the 7 th pin of the 40-pin package, the 11 th pin of the DPDT analog switch chip U4 is serially connected with the R17 and then, the 6 th pin of the DPDT analog switch chip U4 is set as ground, the 16 th pin of the DPDT analog switch chip U4 is connected to the 7 th pin of the MCU chip U2, the 4 th pin of the DPDT analog switch chip U4 is connected to the 8 th pin of the MCU chip U2, the 8 th pin of the DPDT analog switch chip U4 is connected to the 9 th pin of the MCU chip U2, the 12 th pin of the DPDT analog switch chip U4 is connected to the 10 th pin of the MCU chip U2, the 2 nd pin of the DPDT analog switch chip U4 is connected to the 2 nd pin of the MCU chip U2 after being connected to the R5 in series, and the 10 th pin of the DPDT analog switch chip U4 is connected to the 3 rd pin of the MCU chip U2 after being connected to the R6 in series.
The 1 st pin of the DPDT analog switch chip U5 is serially connected with the R19 and then set as the 9 th pin of the 40-pin package, the 15 th pin of the DPDT analog switch chip U5 is serially connected with the R20 and then set as the 10 th pin of the 40-pin package, the 3 rd pin of the DPDT analog switch chip U5 is serially connected with the R21 and then set as the 11 th pin of the 40-pin package, the 5 th pin of the DPDT analog switch chip U5 is serially connected with the R22 and then set as the 12 th pin of the 40-pin package, the 9 th pin of the DPDT analog switch chip U5 is serially connected with the R23 and then set as the 19 th pin of the 40-pin package, the 7 th pin of the DPDT analog switch chip U5 is serially connected with the R24 and then set as the 20 th pin of the 40-pin package, the 13 th pin of the DPDT analog switch chip U5 is serially connected with the R25 and then set as the 21 st pin of the 40-pin package, the 11 th pin of the DPDT analog switch chip U5 is serially connected with the R26 and then, the 6 th pin of the DPDT analog switch chip U5 is set as ground, the 16 th pin of the DPDT analog switch chip U5 is connected to the 11 th pin of the MCU chip U2, the 4 th pin of the DPDT analog switch chip U5 is connected to the 12 th pin of the MCU chip U2, the 8 th pin of the DPDT analog switch chip U5 is connected to the 13 th pin of the MCU chip U2, the 12 th pin of the DPDT analog switch chip U5 is connected to the 14 th pin of the MCU chip U2, the 2 nd pin of the DPDT analog switch chip U5 is connected to the 2 nd pin of the MCU chip U2 after being connected to the R7 in series, and the 10 th pin of the DPDT analog switch chip U5 is connected to the 3 rd pin of the MCU chip U2 after being connected to the R8 in series.
The 1 st pin, the 6 th pin, the 19 th pin and the 27 th pin of the MCU chip U2 are all connected to VCC, the 4 th pin of the MCU chip U2 is set as the 37 th pin of a 40-pin package, the 15 th pin of the MCU chip U2 is set as the 23 th pin of a 40-pin package after being connected with a series resistor R41, the 16 th pin of the MCU chip U2 is set as the 24 th pin of a 40-pin package after being connected with a series resistor R42, the 21 st pin of the MCU chip U2 is set as the 31 st pin of a 40-pin package after being connected with a series resistor R39, the 22 nd pin of the MCU chip U2 is set as the 32 th pin of a 40-pin package after being connected with a series resistor R40, the 23 th pin of the MCU chip U2 is connected to the 14 th pin of an operational amplifier ICU3 after being connected with a series resistor R34, the 24 th pin of the MCU chip U2 is connected to the 8 th pin of an operational amplifier IC 3, the 25 th pin of the MCU chip U2 is set as the 40 th pin of a series resistor R45, the U3639 th pin, a 29 th pin series resistor R35 of the MCU chip U2 is set as a 33 th pin of a 40-pin package, a 30 th pin series resistor R36 of the MCU chip U2 is set as a 34 th pin of the 40-pin package, a 31 st pin series resistor R37 of the MCU chip U2 is set as a 35 th pin of the 40-pin package, a 32 th pin series resistor R38 of the MCU chip U2 is set as a 36 th pin of the 40-pin package, a 33 th pin series resistor R33 of the MCU chip U2 is connected to a 7 th pin of the operational amplifier IC 3, a 34 th pin series resistor R31 of the MCU chip U2 is connected to a 1 st pin of the operational amplifier IC 3, a 35 th pin of the MCU chip U2 is set as a 40 th pin of the 40-pin package and grounded after the series resistor R43, and 18 th, 26 th and 36 th pins of the MCU chip U2 are all set as grounded; the 25 th pin of the 40 pin package is connected to VCC, and the 26 th pin of the 40 pin package is set to ground.
The 3 rd pin series resistor R27 of the operational amplifier IC U3 is set as the 27 th pin of a 40-pin package, the 4 th pin of the operational amplifier IC U3 is connected to VCC, the 12 th pin series resistor R28 of the operational amplifier IC U3 is set as the 28 th pin of the 40-pin package, the 6 th pin series resistor R32 of the operational amplifier IC U3 is set as the 29 th pin of the 40-pin package, the 10 th pin series resistor R29 of the operational amplifier IC U3 is set as the 30 th pin of the 40-pin package, and the 11 th pin of the operational amplifier IC U3 is set as ground.
One end of C2, C3, C4, C5, C6 and C7 which are connected in series is connected to VCC, and the other end of C2, C3, C4, C5, C6 and C7 which are connected in series is grounded; one end of R9 is connected with VCC, one end of C1 is grounded, and the other ends of R9 and C1 are connected with the 4 th pin of MCU chip U2; one ends of R1 and R2 are connected to the 5 th, 9 th and 13 th pins of an operational amplifier IC U3, one end of R, R4 is connected to the 2 nd pin of an operational amplifier IC U3, the other ends of R1 and R3 are connected to VCC, and the other ends of R2 and R4 are grounded.
In this embodiment, the communication circuit may adopt one or more of a UART communication interface or an SPI communication interface; the power supply circuit supplies power for external connection at 3.3V; the MCU chip U2 selects an STM32F103 series microcontroller singlechip; the operational amplifier IC U3 selects an LM324 series operational amplifier; the DPDT analog switch chips U4 and U5 adopt DIO1466 analog switches, the chips are all commercially available chips, and the specific definition and function of each pin are not repeated.
The invention aims to provide a magnetic signal acquisition and recognition algorithm module which can be universally used for currency (paper money) of various countries in the world, can be compatible with a multi-country paper money magnetic detection circuit, quickens the period of developing new products and improves the quality of the products, and the circuit module of the invention is presented in the mode of an integral module circuit, the size of the module is 18mm by 20mm, the output mode of a stamp hole is 40 output pins. In order to facilitate the design of modules used in different cash registers, the size is small, 24 magnetic signal amplifying circuits are not integrated inside, an external amplifying circuit is adopted, and a user can expand the number of the amplifying circuits according to the number of channels required actually (the amplifying circuits adopt standard magnetic amplifying circuits in the circuit).
The above description is only a preferred embodiment of the present invention, and all equivalent changes or modifications of the structure, characteristics and principles described in the present invention are included in the scope of the present invention.
Claims (4)
1. A compatible world currency (paper currency) magnetic signal identification circuit module which characterized in that: the magnetic signal identification circuit comprises a standard magnetic amplification circuit, a magnetic signal identification circuit, a communication circuit and a power supply circuit, wherein the power supply circuit is set to be VCC;
the standard magnetic amplification circuit comprises an operational amplifier U1, resistors R '1 to R' 10, capacitors C '1 to C' 7, a protection resistor ESD, a magnetic sensor coil CC1, and an amplified signal output interface CN 1;
the 1 st pin and the 4 th pin of the magnetic sensor coil CC1 are identification points MAG _ IN-, and the 2 nd pin and the 3 rd pin of the magnetic sensor coil CC1 are identification points MAG _ IN +; one end of R1 is connected to VCC; one end of R ' 2 is grounded, and the other end of R ' 2 and the other end of R ' 1 are connected to form an identification point VREF 1; one end of the parallel connection of the C ' 1 and the protection resistor ESD is connected to the 1 st pin of the amplification signal output interface CN1, the other end of the parallel connection of the C ' 1 and the protection resistor ESD is connected to VCC and the 5 th pin of the amplification signal output interface CN1, the 3 rd and 4 th pins of the amplification signal output interface CN1 are grounded, and the 2 nd pin of the amplification signal output interface CN1 is connected in series with R ' 10 to form an identification point OUT; an identification point L1_ OUT is connected with one parallel end of the C '4 and R' 5 and then connected with the 1 st pin of the operational amplifier U1; the identification point MAG _ IN-is connected with the C '2 and R' 3 IN series and then is connected with the 2 nd pin of the operational amplifier U1 together with the other end of the C '4 and R' 5 IN parallel; the identification point VREF1 is connected to one end of the R '8, C' 5 in parallel; the identification point MAG _ IN + is connected with the 3 rd pin of the amplified signal output interface CN1 after being connected with the C '3 and R' 4 IN series and the other end of the R '8 and C' 5 IN parallel; the 4 th pin of the operational amplifier U1 is grounded; the identification point VREF1 is connected with the 5 th pin of the operational amplifier U1 after being connected with R' 7 in series; one end of the identification point L1_ OUT connected in series with C '6, R' 6, C '7 and R' 9 in parallel is connected with the 6 th pin of the operational amplifier U1 after being connected; the other ends of the C '7 and R' 9 parallel are connected to an identification point OUT and a 7 th pin of an operational amplifier U1; the 8 th pin of the operational amplifier U1 is connected to VCC;
the magnetic signal identification circuit is packaged by 40 pins and comprises an MCU chip U2, an operational amplifier IC U3, a DPDT analog switch chip U4, a U5, resistors R1 to R46 and capacitors C1 to C7;
the 1 st pin of the DPDT analog switch chip U4 is serially connected with the R10 and then set as the 1 st pin of the 40-pin package, the 15 th pin of the DPDT analog switch chip U4 is serially connected with the R11 and then set as the 2 nd pin of the 40-pin package, the 3 rd pin of the DPDT analog switch chip U4 is serially connected with the R12 and then set as the 3 rd pin of the 40-pin package, the 5 th pin of the DPDT analog switch chip U4 is serially connected with the R13 and then set as the 4 th pin of the 40-pin package, the 9 th pin of the DPDT analog switch chip U4 is serially connected with the R14 and then set as the 5 th pin of the 40-pin package, the 7 th pin of the DPDT analog switch chip U4 is serially connected with the R15 and then set as the 6 th pin of the 40-pin package, the 13 th pin of the DPDT analog switch chip U4 is serially connected with the R16 and then set as the 7 th pin of the 40-pin package, the 11 th pin of the DPDT analog switch chip U4 is serially connected with the R17 and then, a 6 th pin of the DPDT analog switch chip U4 is set to be grounded, a 16 th pin of the DPDT analog switch chip U4 is connected to a 7 th pin of the MCU chip U2, a 4 th pin of the DPDT analog switch chip U4 is connected to an 8 th pin of the MCU chip U2, an 8 th pin of the DPDT analog switch chip U4 is connected to a 9 th pin of the MCU chip U2, a 12 th pin of the DPDT analog switch chip U4 is connected to a 10 th pin of the MCU chip U2, a 2 nd pin of the DPDT analog switch chip U4 is connected to a 2 nd pin of the MCU chip U2 after being connected to the R5 in series, and a 10 th pin of the DPDT analog switch chip U4 is connected to a 3 rd pin of the MCU chip U2 after being connected to the R6 in series;
the 1 st pin of the DPDT analog switch chip U5 is serially connected with the R19 and then set as the 9 th pin of the 40-pin package, the 15 th pin of the DPDT analog switch chip U5 is serially connected with the R20 and then set as the 10 th pin of the 40-pin package, the 3 rd pin of the DPDT analog switch chip U5 is serially connected with the R21 and then set as the 11 th pin of the 40-pin package, the 5 th pin of the DPDT analog switch chip U5 is serially connected with the R22 and then set as the 12 th pin of the 40-pin package, the 9 th pin of the DPDT analog switch chip U5 is serially connected with the R23 and then set as the 19 th pin of the 40-pin package, the 7 th pin of the DPDT analog switch chip U5 is serially connected with the R24 and then set as the 20 th pin of the 40-pin package, the 13 th pin of the DPDT analog switch chip U5 is serially connected with the R25 and then set as the 21 st pin of the 40-pin package, the 11 th pin of the DPDT analog switch chip U5 is serially connected with the R26 and then, a 6 th pin of the DPDT analog switch chip U5 is set to be grounded, a 16 th pin of the DPDT analog switch chip U5 is connected to an 11 th pin of the MCU chip U2, a 4 th pin of the DPDT analog switch chip U5 is connected to a 12 th pin of the MCU chip U2, an 8 th pin of the DPDT analog switch chip U5 is connected to a 13 th pin of the MCU chip U2, a 12 th pin of the DPDT analog switch chip U5 is connected to a 14 th pin of the MCU chip U2, a 2 nd pin of the DPDT analog switch chip U5 is connected to a 2 nd pin of the MCU chip U2 after being connected to the R7 in series, and a 10 th pin of the DPDT analog switch chip U5 is connected to a 3 rd pin of the MCU chip U2 after being connected to the R8 in series;
the 1 st pin, the 6 th pin, the 19 th pin and the 27 th pin of the MCU chip U2 are all connected to VCC, the 4 th pin of the MCU chip U2 is set as the 37 th pin of a 40-pin package, the 15 th pin of the MCU chip U2 is set as the 23 th pin of a 40-pin package after being connected with a series resistor R41, the 16 th pin of the MCU chip U2 is set as the 24 th pin of a 40-pin package after being connected with a series resistor R42, the 21 st pin of the MCU chip U2 is set as the 31 st pin of a 40-pin package after being connected with a series resistor R39, the 22 nd pin of the MCU chip U2 is set as the 32 th pin of a 40-pin package after being connected with a series resistor R40, the 23 th pin of the MCU chip U2 is connected to the 14 th pin of an operational amplifier IC 3 after being connected with a series resistor R34, the 24 th pin of the MCU chip U2 is connected to the 8 th pin of an operational amplifier IC 3, the 25 th pin of the MCU chip U2 is set as the 40 th pin of a series resistor R45, and the U3639 th pin, a 29 th pin series resistor R35 of the MCU chip U2 is set as a 33 th pin of a 40-pin package, a 30 th pin series resistor R36 of the MCU chip U2 is set as a 34 th pin of the 40-pin package, a 31 st pin series resistor R37 of the MCU chip U2 is set as a 35 th pin of the 40-pin package, a 32 th pin series resistor R38 of the MCU chip U2 is set as a 36 th pin of the 40-pin package, a 33 th pin series resistor R33 of the MCU chip U2 is connected to a 7 th pin of the operational amplifier IC 3, a 34 th pin series resistor R31 of the MCU chip U2 is connected to a 1 st pin of the operational amplifier IC U3, a 35 th pin of the MCU chip U2 is set as a 40 th pin of the 40-pin package and is grounded after the series resistor R43, and an 18 th pin, a 26 th pin and a 36 th pin of the MCU chip U2 are all set as ground; a 25 th pin of the 40-pin package is connected to VCC, and a 26 th pin of the 40-pin package is set as ground;
a 3 rd pin series resistor R27 of an operational amplifier IC U3 is set as a 27 th pin of a 40-pin package, a 4 th pin of the operational amplifier IC U3 is connected with VCC, a 12 th pin series resistor R28 of the operational amplifier IC U3 is set as a 28 th pin of the 40-pin package, a 6 th pin series resistor R32 of the operational amplifier IC U3 is set as a 29 th pin of the 40-pin package, a 10 th pin series resistor R29 of the operational amplifier IC U3 is set as a 30 th pin of the 40-pin package, and an 11 th pin of the operational amplifier IC U3 is set as ground;
one end of C2, C3, C4, C5, C6 and C7 which are connected in series is connected to VCC, and the other end of C2, C3, C4, C5, C6 and C7 which are connected in series is grounded; one end of R9 is connected with VCC, one end of C1 is grounded, and the other ends of R9 and C1 are connected with the 4 th pin of MCU chip U2; one ends of R1 and R2 are connected to the 5 th, 9 th and 13 th pins of an operational amplifier IC U3, one end of R, R4 is connected to the 2 nd pin of an operational amplifier IC U3, the other ends of R1 and R3 are connected to VCC, and the other ends of R2 and R4 are grounded.
2. The magnetic signal identification circuit module compatible with world currency (paper money) according to claim 1, characterized in that: the communication circuit may employ one or more of a UART communication interface or an SPI communication interface.
3. The magnetic signal identification circuit module compatible with world currency (paper money) according to claim 1, characterized in that: the power supply circuit supplies power for external connection at 3.3V.
4. The magnetic signal identification circuit module compatible with world currency (paper money) according to claim 1, characterized in that: the MCU chip U2 selects an STM32F103 series microcontroller singlechip; the operational amplifier IC U3 selects an LM324 series operational amplifier; the DPDT analog switch chips U4 and U5 select DIO1466 analog switches.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810648833.7A CN110706398A (en) | 2018-06-22 | 2018-06-22 | Magnetic signal identification circuit module compatible with world currency (paper money) |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810648833.7A CN110706398A (en) | 2018-06-22 | 2018-06-22 | Magnetic signal identification circuit module compatible with world currency (paper money) |
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| CN110706398A true CN110706398A (en) | 2020-01-17 |
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Application publication date: 20200117 |