CN110704113B - Starting method and system based on FPGA platform and development board device - Google Patents

Starting method and system based on FPGA platform and development board device Download PDF

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Publication number
CN110704113B
CN110704113B CN201910834125.7A CN201910834125A CN110704113B CN 110704113 B CN110704113 B CN 110704113B CN 201910834125 A CN201910834125 A CN 201910834125A CN 110704113 B CN110704113 B CN 110704113B
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data
memory
boot
circuit board
program data
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CN110704113A (en
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张贞雷
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Suzhou Inspur Intelligent Technology Co Ltd
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Suzhou Inspur Intelligent Technology Co Ltd
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/44—Arrangements for executing specific programs
    • G06F9/4401—Bootstrapping
    • G06F9/4406—Loading of operating system
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

The application discloses a starting method based on an FPGA platform, which comprises the steps of compiling and downloading boot loader data, information data on a description circuit board, boot system starting program data and real-time operating system program data to different positions in a first memory of an FPGA development board in the FPGA debugging process, and only need to recompile and download the data needing to be modified when one data needs to be modified, so that the debugging/optimizing speed is greatly accelerated, and the progress of projects is ensured; the application also discloses a starting system based on the FPGA platform; the application also provides a development board device.

Description

Starting method and system based on FPGA platform and development board device
Technical Field
The application relates to the field of processor debugging, in particular to a starting method and system based on an FPGA platform and a development board device.
Background
As processor systems are increasingly used, FPGA-based platforms are increasingly developed. In the process of developing the FPGA, a developer modifies part of data after compiling and downloading, after the modification is completed, the developer recompiles and downloads all data into the FPGA, wherein the all data comprises unmodified data and modified data, and in the process of recompilation and downloading, the developer recompilation and downloading the unmodified data, so that the development period of the FPGA is unnecessarily increased.
Disclosure of Invention
In view of this, it is necessary to provide a starting method, system and development board device based on FPGA platform.
The application provides a starting method based on an FPGA platform, which comprises the following steps:
compiling and downloading the boot loader data, the information data on the description circuit board, the boot system starting program data and the real-time operating system program data to different positions in the first memory of the FPGA development board;
running boot loader data, copying information data, boot system start program data and real-time operating system program data described on a circuit board in the first memory to a designated address in a second memory;
information data on the run-description circuit board, run-boot system boot program data to boot run-time operating system program data to boot the system.
Optionally, after compiling and downloading the boot loader data, the information data on the description circuit board, the boot system startup program data and the real-time operating system program data to different positions in the first memory of the FPGA development board, the method further includes:
modifying at least one of the bootloader data, the information data on the descriptive circuit board, the bootloader data, and the real-time operating system program data;
and recompiling and downloading the modified data to a designated position in the first memory of the FPGA development board.
Optionally, running the boot loader data, copying the information data described on the circuit board, the boot system startup program data and the real-time operating system program data in the first memory to the specified address in the second memory further includes:
and the boot loader data configures a check module register to check the copied data.
Optionally, verifying the copied data includes:
and comparing the data of the appointed address in the second memory with the information data, the boot system starting program data and the real-time operating system program data which are described on the circuit board in the first memory.
Optionally, verifying the copied data further includes:
if the copied data is abnormal, stopping checking.
Optionally, if the copied data is abnormal, the method further includes:
the bootloader data configures the alarm module register and alarms.
The application also provides a starting system based on the FPGA platform, which comprises:
the device comprises a downloading unit, an operating unit, a first storage unit and a second storage unit;
the downloading unit is used for compiling and downloading the boot loader data, the information data on the description circuit board, the boot system starting program data and the real-time operating system program data to different positions in the first storage unit of the FPGA development board;
the running unit is used for running the boot loader data, copying the information data, the boot system starting program data and the real-time operating system program data which are described in the first memory to the appointed address in the second memory unit, running the information data which are described in the circuit board, and running the boot system starting program data to guide the real-time operating system program data to run so as to start the system.
Optionally, the starting system based on the FPGA platform further includes:
and the verification unit is used for verifying the copied data, and stopping verification if the copied data is abnormal.
Optionally, the starting system based on the FPGA platform further includes:
and the alarm unit is used for alarming the copied data abnormality.
The present application also provides a development board apparatus comprising:
the first interface, the peripheral bus, the first memory and the second memory;
the first memory is connected with the first interface;
the first memory is configured as a boot loader data storage area, an information data storage area on the description circuit board, a boot system startup program data storage area and a real-time operating system program data storage area;
the first memory is connected with the second memory through the peripheral bus.
Optionally, the loader data storage area includes:
the boot loader data storage area is used for copying data in the information data storage area, the boot system boot program data storage area and the real-time operating system program data storage area on the description circuit board to the second memory.
Optionally, the development board device further includes:
and the verifier is used for verifying the copied data, and stopping verification if the copied data is abnormal.
Optionally, the development board device further includes:
and the alarm is used for alarming the copied data abnormality.
Compared with the prior art, the application has at least the following advantages:
according to the starting method based on the FPGA platform, the boot loader data, the information data on the description circuit board, the boot system starting program data and the real-time operating system program data are compiled and downloaded to different positions in the first memory of the FPGA development board, when one of the data needs to be modified, the data needing to be modified is recompiled and downloaded, the defect that in the prior art, once one of the data needs to be modified, all the data need to be recompiled and downloaded is avoided, and the period of FPGA development is shortened.
Further, after the information data, the boot system starting program data and the real-time operating system program data described on the circuit board in the first memory are copied to the appointed address in the second memory, a verification module is added to verify the copied data, and once data abnormality occurs, verification is stopped, and the completion of all data verification is not waited, so that the development period of the FPGA is further shortened.
Furthermore, an alarm module is added, if the copied data is abnormal, the alarm module generates an alarm, thereby facilitating the positioning problem of openers and further shortening the development period of the FPGA.
Drawings
In order to more clearly illustrate the embodiments of the application or the technical solutions of the prior art, the drawings which are used in the description of the embodiments or the prior art will be briefly described, it being obvious that the drawings in the description below are only some embodiments of the application, and that other drawings can be obtained according to these drawings without inventive faculty for a person skilled in the art.
FIG. 1 is a flowchart of a starting method based on an FPGA platform provided by an embodiment of the application;
FIG. 2 is a flowchart of another starting method based on an FPGA platform according to an embodiment of the present application;
FIG. 3 is a flowchart of another starting method based on an FPGA platform according to an embodiment of the present application;
FIG. 4 is an exemplary diagram of a starting system based on an FPGA platform according to an embodiment of the present application;
fig. 5 is a diagram of an example of a development board device according to an embodiment of the present application.
Detailed Description
In order to make the technical solution of the present application better understood by those skilled in the art, the technical solution of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application, and it is apparent that the described embodiments are only some embodiments of the present application, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.
The embodiment of the application provides a starting method based on an FPGA platform, which is a reduced instruction set RISC processor system based on an FPGA, wherein when a traditional reduced instruction set RISC processor system based on the FPGA is used for guiding the RISC system to start, boot loader data, information data on a description circuit board, boot system starting program data and real-time operating system program data are compiled and downloaded together to generate an instruction, but in the development process, a developer modifies part of the data after compiling and downloading, so that under the condition that the developer modifies one data, the developer is required to compile and download all the data, a great amount of time is occupied, and the development period of the FPGA is unnecessarily increased. Therefore, the application provides a starting method based on the FPGA platform so as to shorten the development period of the FPGA.
Method embodiment one:
referring to fig. 1, the flowchart of a starting method based on an FPGA platform according to an embodiment of the present application is shown.
The starting method based on the FPGA platform provided by the embodiment of the application comprises the following steps:
step 101: and compiling and downloading the boot loader data, the information data on the description circuit board, the boot system starting program data and the real-time operating system program data to different positions in the first memory of the FPGA development board.
In an alternative method, the bootloader data may be a first stage bootloader FSBL for copying information data describing the circuit board, booting system boot program data and real-time operating system program data to the second memory, and configuring the check module registers.
In an alternative method, the above information data describing the circuit board may be a device tree boot loader DTB for describing information of the CPU, bus, device, etc. on the circuit board.
In an alternative method, the boot system boot program data may be a berkeley boot loader BBL for booting the system.
In an alternative method, the real-time operating system program data may be a system KERNEL, which is a system running on a computer.
As one embodiment, the FSBL compilation is downloaded into a first region fsbl_ram of the first memory; downloading the DTB compilation to a second area DTB_RAM of the first memory; downloading the BBL compilation into a BBL_RAM of a third area of the first memory; and downloading the KERNEL compilation to a fourth area KERNEL_RAM of the first memory.
It should be noted that, the foregoing compiling and downloading process may be simultaneous compiling and downloading, or may be sequential compiling and downloading.
Step 102: and running the boot loader data, and copying the information data, the boot system starting program data and the real-time operating system program data which are described on the circuit board in the first memory to a designated address in the second memory.
As one embodiment, running the data in the fsbl_ram, the FSBL copies the data in dtb_ram to the first address of the second memory; copying data in the BBL_RAM to a second address of the second memory; copying the data in the KERNEL_RAM to a third address of the second memory.
It should be noted that the above-mentioned copying process may be simultaneous copying or sequential copying.
Step 103: running the DTB, running the BBL to boot the KERNEL to start the system
In an alternative method, running the DTB is running data of the first address of the second memory; running the BBL is running data of the second address of the second memory; running the KERNEL is running data of the third address of the second memory to boot the system.
Method embodiment two:
the second embodiment of the method is an improvement based on the first embodiment of the method, and for brevity, the content of the second embodiment of the method is the same as that of the first embodiment of the method, and the description thereof will be omitted herein.
Referring to fig. 2, in the starting method based on the FPGA platform provided by the embodiment of the present application, on the basis of the first method embodiment, after step 201, the modification is performed on the data already compiled and downloaded, including:
in an alternative method, modifying at least one of the FSBL, the DTB, the BBL, and the KERNEL; and recompiling and downloading the modified data to a designated position in the first memory of the FPGA development board.
As an implementation manner, after the FSBL, the DTB, the BBL and the KERNEL are compiled and downloaded to different locations in the first memory of the FPGA development board, a developer needs to modify the FSBL therein, and after modification is completed, the FSBL is recompiled and downloaded to a designated location in the first memory of the FPGA development board.
As another implementation, after the FSBL, DTB, BBL, and kennel compilations have been downloaded to different locations in the FPGA development board first memory, a developer needs to modify the FSBL and BBL therein, and after modification is completed, recompilations download the FSBL and BBL to different locations in the FPGA development board first memory.
In the above embodiment, the data to be modified may be at least one of the FSBL, the DTB, the BBL, and the kenel.
According to the starting method based on the FPGA platform, provided by the embodiment of the application, in the development process, a developer can modify part of data after compiling and downloading, and because in the embodiment of the application, the FSBL, the DTB, the BBL and the KERNEL are stored separately, when the developer modifies the data needing to be modified, the developer only needs to recompile the data after downloading and modifying, and the data which is compiled and downloaded and modified does not need to recompile and downloading, so that a large amount of time is saved, and the period of FPGA development is shortened.
Method embodiment three:
the third embodiment of the method is an improvement based on the first embodiment of the method and the second embodiment of the method, and for brevity, the third embodiment of the method is the same as the first embodiment of the method and the second embodiment of the method, and is not described herein, and the different portions of the third embodiment of the method and the second embodiment of the method are mainly described below.
Referring to fig. 3, in the starting method based on the FPGA platform provided by the embodiment of the present application, after step 304, a verification module is added to verify the copied data on the basis of the first method embodiment and the second method embodiment, including:
step 305: and checking the copied data.
In an alternative method, the data verification process may be comparing the data before and after copying, and comparing the DTB before and after copying one by one; comparing the BBL before replication with the BBL after replication one by one; the KERNEL before replication and the KERNEL after replication are compared one by one.
Step 306: whether the data is normal.
In an alternative method, determining whether the data is normal may be: comparing whether the DTB before replication is completely consistent with the DTB after replication; comparing whether the BBL before replication and the BBL after replication are completely consistent; comparing whether the KERNEL before replication and the KERNEL after replication are completely consistent;
step 307: and (5) stopping checking when the data is abnormal.
In an alternative method, if the DTB before replication and the DTB after replication or the BBL before replication and the BBL after replication or the KERNEL before replication and the KERNEL after replication in step 204 are not consistent, stopping the verification.
It should be noted that, in the step 307, the check may be stopped if the DTB before replication and the DTB after replication are not consistent; or firstly, finding that the BBL before replication is inconsistent with the BBL after replication, and stopping checking; it is also possible to first find that the pre-replicated KERNEL is inconsistent with the post-replicated KERNEL. That is, at least one of the three conditions that the DTB before replication and the DTB after replication are inconsistent, that the BBL before replication and the BBL after replication are inconsistent, and that the KERNEL before replication and the KERNEL after replication are inconsistent, the verification is stopped.
In an optional method, an alarm module is added after the step 307, for alarming data anomalies, including
Step 308: and (5) alarming.
In an alternative method, the alarm module generates an alarm after stopping the verification.
It should be noted that, in step 308, the alarm generated by the alarm module may be a sound variation of the buzzer, a flashing light, or any other phenomenon that can play a role in warning the sender.
According to the starting method based on the FPGA platform, in the compiling and downloading process, the FSBL, the DTB, the BBL and the KERENL are compiled and downloaded to different positions in the first memory of the FPGA development board, when at least one data in the FSBL, the DTB, the BBL and the KERENL needs to be modified, a developer only needs to recompile the downloaded modified data, the recompilated unmodified data is not needed, and the period of FPGA development is shortened. Further, after the FSBL is operated, the DTB, the BBL and the KERNEL are copied to the designated address in the second memory, a verification module is added for verifying the copied data, and once the copied data is abnormal, the verification is stopped and the verification is not completed until all data verification is completed, so that the development period of the FPGA is further shortened. Furthermore, an alarm module is added, if the copied data is abnormal, the alarm module generates an alarm, so that a developer can conveniently position the problem, and the development period of the FPGA is further shortened.
Based on the starting method based on the FPGA platform, the embodiment of the application also provides a starting system based on the FPGA platform, and the starting system is explained and illustrated with reference to the accompanying drawings.
System embodiment:
referring to fig. 4, an FPGA platform-based starting system provided by an embodiment of the present application includes: a downloading unit 401, a first storing unit 402, an operating unit 403, a second storing unit 404, a checking unit 405 and an alerting unit 406.
The downloading unit 401 is configured to download the FSBL, the DTB, the BBL, and the kenel compilations to different locations in the first storage unit of the FPGA development board.
As one implementation, the FSBL compilation is downloaded into fsbl_ram in the first memory 402; compiling and downloading the DTB data into a DTB_RAM in the first memory 402; downloading the BBL compilation into bbl_ram in the first memory 402; the KERNEL compilation is downloaded into KERNEL_RAM in the first memory 402.
It should be noted that, the foregoing compiling and downloading process may be simultaneous compiling and downloading, or may be sequential compiling and downloading.
The first storage unit 402 is configured to store data compiled and downloaded by the downloading unit 401.
The running unit 403 is configured to run the FSBL, copy the DTB in the dtb_ram in the first memory 402, the BBL in the bbl_ram in the first memory 402, and the kennel in the kennel_ram in the first memory 402 to specified addresses in the second memory unit 404, run the DTB, run the BBL to boot the kennel, so as to start the system.
As one embodiment, the FSBL is run, copying DTBs in dtb_ram in the first memory 402 to the first address of the second memory unit 404; copying the BBL in the BBL RAM in the first memory 402 to the second address of the second memory location 404; KERNEL in KERNEL_RAM in first memory 402 is copied to the third address of second memory unit 404.
The second storage unit 404 is configured to store the copied data, so that the system operates.
In an alternative approach, the replicated data may be DTB, BBL and KERNEL.
The verification unit 405 is configured to verify the copied data.
As an embodiment, in an alternative method, the data verification process may be comparing the data before replication and the data after replication, and comparing the DTB before replication and the DTB after replication one by one; comparing the BBL before replication with the BBL after replication one by one; the KERNEL before replication and the KERNEL after replication are compared one by one. Comparing whether the DTB before replication is completely consistent with the DTB after replication; comparing whether the BBL before replication and the BBL after replication are completely consistent; comparing whether the KERNEL before replication and the KERNEL after replication are completely consistent; and stopping checking if the DTB before copying is inconsistent with the DTB after copying or the BBL before copying is inconsistent with the BBL after copying or the KERNEL before copying is inconsistent with the KERNEL after copying.
In the above embodiment, the check may be stopped when the DTB before copying and the DTB after copying are found to be inconsistent; or firstly, finding that the BBL before replication is inconsistent with the BBL after replication, and stopping checking; it is also possible to first find that the pre-replicated KERNEL is inconsistent with the post-replicated KERNEL. That is, at least one of the three conditions that the DTB before replication and the DTB after replication are inconsistent, that the BBL before replication and the BBL after replication are inconsistent, and that the KERNEL before replication and the KERNEL after replication are inconsistent, the verification is stopped.
And the alarm unit 406 is used for generating an alarm after stopping the verification, prompting the developer that the data is abnormal, and facilitating the positioning of the openers.
The alarm generated by the alarm unit can be the sound variation of the buzzer, the flashing of the light, or any other phenomenon which can play a role in alarming the sender.
The starting system based on the FPGA provided by the embodiment of the application comprises the following components: the system comprises a downloading unit 401, a first storage unit 402, an operating unit 403, a second storage unit 404, a checking unit 405 and an alarm unit 406, wherein when the downloading unit 401 downloads the FSBL, the DTB, the BBL and the KERNEL to different positions in the first storage unit 402 of the FPGA development board in a compiling manner, when at least one data in the FSBL, the DTB, the BBL and the KERNEL needs to be modified, the system only needs to recompile the downloaded modified data, and the data which is not modified does not need to be recompiled, so that the period of FPGA development is shortened. Further, after the operation unit 403 copies the DTB, the BBL, and the kenel to the designated addresses in the second memory unit 404 after operating the FSBL, a verification unit 405 is added to verify the copied data, and once the copied data is abnormal, the verification is stopped, and not until all data verification is completed, thereby further shortening the period of FPGA development. Furthermore, the alarm unit 406 generates an alarm after the copied data is abnormal, which further shortens the development period of the FPGA.
Based on the starting method based on the FPGA platform and the starting system based on the FPGA platform, the embodiment of the application also provides a starting device based on the FPGA platform, and the starting device is explained and illustrated below with reference to the accompanying drawings.
Device example:
referring to fig. 5, an FPGA platform-based starting apparatus provided by an embodiment of the present application includes: the system comprises a first interface, a first memory, a second memory, an alarm, a verifier and a peripheral bus.
The first interface is connected with the first memory and is used for compiling and downloading data into a boot loader data storage area, an information data storage area, a boot system starting program data storage area and a real-time operating system program data storage area on the description circuit board in the first memory.
The peripheral bus is used for connecting internal and external resources of the system.
The first memory is connected with the second memory through the peripheral bus and is used for copying data in the information data storage area, the data in the boot system boot program data storage area and the data in the real-time operating system program data storage area on the description circuit board into the second memory.
The checker is connected with the second memory through the peripheral bus and is used for checking the copied memory.
The alarm device is connected with the verifier through the peripheral bus and used for warning the developer if the data are abnormal.
According to the development board device provided by the embodiment of the application, the data is compiled and downloaded to the four different storage areas in the first memory through the first interface, once the data of one storage area needs to be modified, the data in the modified storage area is only required to be recompiled and downloaded through the first interface, and the recompilation and downloading of the unmodified storage area are not required, so that the development period of the FPGA is shortened. Furthermore, after the first memory copies the data in the first memory to the second memory through the peripheral bus, a checker is added to check the copied data, and once the copied data is abnormal, the check is stopped and not until all data checks are completed, so that the development period of the FPGA is further shortened. Furthermore, an alarm is added, if the copied data is abnormal, an alarm is generated, the problem of positioning is more direct, and the development period of the FPGA is further shortened.
It should be noted that, in the present specification, each embodiment is described in a progressive manner, and identical and similar parts of each embodiment are all referred to each other, and each embodiment is mainly described in a different point from other embodiments. In particular, for system and apparatus embodiments, since they are substantially similar to method embodiments, the description is relatively simple, with reference to the description of method embodiments in part. The system and apparatus embodiments described above are merely illustrative, in which elements illustrated as separate elements may or may not be physically separate, and elements shown as elements may or may not be physical elements, may be located in one place, or may be distributed over a plurality of network elements. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of this embodiment. Those of ordinary skill in the art will understand and implement the present application without undue burden.
The above description is only of the preferred embodiment of the present application, and is not intended to limit the present application in any way. Although the preferred embodiments of the present application have been described above, the present application is not limited thereto. Any person skilled in the art can make many possible variations and modifications to the technical solution of the present application, or modifications to equivalent embodiments, using the methods and technical contents disclosed above, without departing from the scope of the technical solution of the present application. Therefore, any simple modification, equivalent variation and modification made to the above embodiments according to the technical substance of the present application still fall within the scope of the technical solution of the present application, unless the technical substance of the present application is separated from the content of the technical solution of the present application.

Claims (11)

1. The starting method based on the FPGA platform is characterized by comprising the following steps of:
compiling and downloading boot loader data into a first area FSBL_RAM in a first memory of an FPGA development board, compiling and downloading information data on a description circuit board into a second area DTB_RAM in the first memory of the FPGA development board, compiling and downloading boot system starting program data into a third area BBL_RAM in the first memory of the FPGA development board, and compiling and downloading real-time operating system program data into a KERNEL_RAM in a fourth memory of the FPGA development board; the boot loader data is a first stage boot loader FSBL used for copying information data, boot system starting program data and real-time operating system program data on the description circuit board to a second memory; the information data describing the circuit board is a device tree boot loader (DTB) and is used for describing the information of a CPU, a bus and devices on the circuit board;
running boot loader data, copying information data on a description circuit board in the first memory to a first address of a second memory, copying boot system startup program data to a second address of the second memory, and copying real-time operating system program data to a third address of the second memory;
running information data on the descriptive circuit board, running boot system boot program data to boot running real-time operating system program data to boot the system;
after compiling and downloading the boot loader data, the information data on the description circuit board, the boot system startup program data and the real-time operating system program data to different positions in the first memory of the FPGA development board, the method further comprises: modifying at least one of the bootloader data, the information data on the descriptive circuit board, the bootloader data, and the real-time operating system program data; and recompiling and downloading the modified data to a designated position in the first memory of the FPGA development board.
2. The method of claim 1, wherein running the boot loader data copies the information data described on the circuit board, the boot system boot program data, and the real-time operating system program data in the first memory to specified addresses in the second memory further comprises:
and the boot loader data configures a check module register to check the copied data.
3. The method of claim 2, wherein verifying the copied data comprises:
and comparing the data of the appointed address in the second memory with the information data, the boot system starting program data and the real-time operating system program data which are described on the circuit board in the first memory.
4. The method of claim 2, wherein verifying the copied data further comprises:
if the copied data is abnormal, stopping checking.
5. The method of claim 4, wherein if the copied data is abnormal further comprises:
the bootloader data configures the alarm module register and alarms.
6. An FPGA platform-based starting system, comprising:
the device comprises a downloading unit, an operating unit, a first storage unit and a second storage unit;
the downloading unit is used for compiling and downloading boot loader data into a first area FSBL_RAM in a first memory of the FPGA development board, compiling and downloading information data on a description circuit board into a second area DTB_RAM in the first memory of the FPGA development board, compiling and downloading boot system starting program data into a third area BBL_RAM in the first memory of the FPGA development board and compiling and downloading real-time operating system program data into a KERNEL_RAM in a fourth memory of the FPGA development board, wherein the boot loader data is a first stage boot loader FSBL used for copying the information data on the description circuit board, the boot system starting program data and the real-time operating system program data into the second memory; the information data describing the circuit board is a device tree boot loader (DTB) and is used for describing the information of a CPU, a bus and devices on the circuit board;
the running unit is used for running the boot loader data, copying the information data on the description circuit board in the first memory to a first address of the second memory, copying the boot system startup program data to a second address of the second memory and copying the real-time operating system program data to a third address of the second memory, running the information data on the description circuit board, and running the boot system startup program data to guide the running of the real-time operating system program data so as to start the system;
after compiling and downloading the boot loader data, the information data on the description circuit board, the boot system startup program data and the real-time operating system program data to different positions in the first memory of the FPGA development board, the method further comprises: modifying at least one of the bootloader data, the information data on the descriptive circuit board, the bootloader data, and the real-time operating system program data; and recompiling and downloading the modified data to a designated position in the first memory of the FPGA development board.
7. The system of claim 6, further comprising:
and the verification unit is used for verifying the copied data, and stopping verification if the copied data is abnormal.
8. The system of claim 6, further comprising:
and the alarm unit is used for alarming the copied data abnormality.
9. A development board apparatus, comprising:
the first interface, the peripheral bus, the first memory and the second memory;
the first memory is connected with the first interface;
the first memory is configured as a boot loader data storage area, an information data storage area on the description circuit board, a boot system startup program data storage area and a real-time operating system program data storage area; the boot loader data in the boot loader data storage area is a first stage boot loader FSBL used for copying information data, boot system starting program data and real-time operating system program data on the description circuit board to the second memory; the information data on the description circuit board in the information data storage area on the description circuit board is an equipment tree guide loader DTB and is used for describing information of a CPU, a bus and equipment on the circuit board;
the first memory is connected with the second memory through the peripheral bus;
the loader data storage area includes: the boot loader data storage area is used for copying information data on the description circuit board in the first memory to a first address of the second memory, copying boot system startup program data to a second address of the second memory and copying real-time operating system program data to a third address of the second memory;
the apparatus further comprises:
modifying at least one of the boot loader data in the boot loader data storage area, the information data on the description circuit board in the information data storage area on the description circuit board, the boot system startup program data in the boot system startup program data storage area, and the real-time operating system program data in the real-time operating system program data storage area; and recompiling and downloading the modified data to a designated position in a first memory of the FPGA development board.
10. The apparatus as recited in claim 9, further comprising:
and the verifier is used for verifying the copied data, and stopping verification if the copied data is abnormal.
11. The apparatus as recited in claim 10, further comprising: and the alarm is used for alarming the copied data abnormality.
CN201910834125.7A 2019-09-04 2019-09-04 Starting method and system based on FPGA platform and development board device Active CN110704113B (en)

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