CN110690283A - Homoepitaxial gallium nitride transistor device structure - Google Patents
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- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 title claims abstract description 43
- 229910002601 GaN Inorganic materials 0.000 title claims abstract description 41
- 230000004888 barrier function Effects 0.000 claims abstract description 62
- 239000000758 substrate Substances 0.000 claims abstract description 32
- 229910003460 diamond Inorganic materials 0.000 claims description 4
- 239000010432 diamond Substances 0.000 claims description 4
- 238000002161 passivation Methods 0.000 claims description 4
- 229910052594 sapphire Inorganic materials 0.000 claims description 4
- 239000010980 sapphire Substances 0.000 claims description 4
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims description 4
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 4
- 229910052710 silicon Inorganic materials 0.000 claims description 3
- 239000010703 silicon Substances 0.000 claims description 3
- 230000002829 reductive effect Effects 0.000 abstract description 5
- 238000001657 homoepitaxy Methods 0.000 abstract description 3
- 239000004065 semiconductor Substances 0.000 abstract description 2
- 238000000034 method Methods 0.000 description 11
- 238000010586 diagram Methods 0.000 description 6
- 239000012535 impurity Substances 0.000 description 4
- 230000008569 process Effects 0.000 description 4
- 230000007547 defect Effects 0.000 description 2
- 238000000407 epitaxy Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 208000032750 Device leakage Diseases 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 230000002401 inhibitory effect Effects 0.000 description 1
- 230000000670 limiting effect Effects 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 239000011185 multilayer composite material Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 230000005533 two-dimensional electron gas Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
Abstract
The invention is suitable for the technical field of semiconductors, and provides a homoepitaxy gallium nitride transistor device structure, which comprises: the transistor comprises a substrate, a channel layer positioned on the substrate, a barrier layer positioned on the channel layer and an electrode positioned on the barrier layer, wherein the electrode comprises a source electrode, a drain electrode and a gate electrode; the source electrode and the drain electrode are respectively positioned on two sides of the upper surface of the barrier layer, and the gate electrode is positioned on the barrier layer between the source electrode and the drain electrode; the thickness range of the channel layer satisfies d is more than or equal to 1nm1Less than or equal to 20nm, and the thickness range of the barrier layer satisfies d2>12 nm. According to the heterojunction interface main channel structure, the thin channel layer is arranged, so that electrons of the auxiliary channel can enter the heterojunction interface main channel and become controllable main channel electrons, and leakage current is reduced.
Description
Technical Field
The invention belongs to the technical field of semiconductors, and particularly relates to a homoepitaxial gallium nitride transistor device structure.
Background
Compared with the existing heteroepitaxial gallium nitride (GaN) HEMT (High Electron Mobility Transistor) device, homoepitaxial GaN has the advantages of low dislocation density, low current collapse, High reliability and High breakdown. However, since the surface of the GaN substrate is prone to absorb impurities, the conventional homoepitaxial GaN HEMT has a side channel and the device leakage is large.
At present, impurity compensation is introduced into the structure of the low-leakage homoepitaxy GaN HEMT device, and the method is the most effective method for inhibiting a secondary channel and reducing leakage current. However, the method of introducing impurity compensation introduces new defects, current collapse is increased, and saturation current is reduced.
Disclosure of Invention
In view of the above, embodiments of the present invention provide a homoepitaxial gan transistor device structure to solve the problem of current leakage caused by the sub-channel effect in the prior art.
A first aspect of an embodiment of the present invention provides a homoepitaxial gallium nitride transistor device structure, including:
the transistor comprises a substrate, a channel layer positioned on the substrate, a barrier layer positioned on the channel layer and an electrode positioned on the barrier layer, wherein the electrode comprises a source electrode, a drain electrode and a gate electrode;
the source electrode and the drain electrode are respectively positioned on two sides of the upper surface of the barrier layer, and the gate electrode is positioned on the barrier layer between the source electrode and the drain electrode;
the thickness range of the channel layer satisfies d is more than or equal to 1nm1Less than or equal to 20nm, and the thickness range of the barrier layer satisfies d2>12nm, said d1Denotes the thickness of the channel layer, d2Indicating the thickness of the barrier layer.
In one embodiment, the substrate is a substrate that is epitaxially coated with a layer of gallium nitride on a sapphire, silicon carbide, silicon or diamond basis.
In one embodiment, the gallium nitride substrate is a pure gallium nitride substrate.
In one embodiment, the channel layer is InmAlnGarN; wherein m is more than or equal to 0 and less than or equal to 1, n is more than or equal to 0 and less than or equal to 0.1, r is more than or equal to 0.9 and less than or equal to 1, and m + n + r is equal to 1.
In one embodiment, the channel layer is InGaN.
In one embodiment, the barrier layer is InxAlyGazN; wherein x is more than or equal to 0 and less than or equal to 0.85, y is more than or equal to 0.15 and less than or equal to 1, z is more than or equal to 0 and less than or equal to 0.85, and x + y + z is equal to 1.
In one embodiment, further comprising a passivation layer on the barrier layer between the source electrode and the gate electrode, and between the gate electrode and the drain electrode.
In one embodiment, the gate electrode is any one of a T-gate, a straight gate, a Y-gate, a TT-gate, and a U-gate.
In one embodiment, the gate electrode is a straight gate, and the homoepitaxial gallium nitride transistor device structure further comprises a gate dielectric layer on the barrier layer below the straight gate.
In one embodiment, the gate electrode is a schottky gate.
The homoepitaxy gallium nitride transistor device structure provided by the embodiment of the invention comprises: the transistor comprises a substrate, a channel layer positioned on the substrate, a barrier layer positioned on the channel layer and an electrode positioned on the barrier layer, wherein the electrode comprises a source electrode, a drain electrode and a gate electrode; the source electrode and the drain electrode are respectively positioned on two sides of the upper surface of the barrier layer, and the gate electrode is positioned on the barrier layer between the source electrode and the drain electrode; the thickness range of the channel layer satisfies d is more than or equal to 1nm1Less than or equal to 20nm, and the thickness range of the barrier layer satisfies d2>12 nm. According to the heterojunction interface main channel structure, the thin channel layer is arranged, so that electrons of the auxiliary channel can enter the heterojunction interface main channel and become controllable main channel electrons, and leakage current is reduced.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the embodiments or the prior art descriptions will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without inventive exercise.
Fig. 1 is a schematic diagram of a homoepitaxial gallium nitride transistor device structure provided by an embodiment of the present invention;
FIG. 2 is a schematic diagram of a prior art GaN transistor device structure provided by an embodiment of the invention;
fig. 3 is a schematic diagram of another homoepitaxial gan transistor device structure provided by an embodiment of the present invention.
Detailed Description
In the following description, for purposes of explanation and not limitation, specific details are set forth, such as particular system structures, techniques, etc. in order to provide a thorough understanding of the embodiments of the invention. It will be apparent, however, to one skilled in the art that the present invention may be practiced in other embodiments that depart from these specific details. In other instances, detailed descriptions of well-known systems, devices, circuits, and methods are omitted so as not to obscure the description of the present invention with unnecessary detail.
The terms "comprises" and "comprising," and any variations thereof, in the description and claims of this invention and the above-described drawings are intended to cover non-exclusive inclusions. For example, a process, method, or system, article, or apparatus that comprises a list of steps or elements is not limited to only those steps or elements listed, but may alternatively include other steps or elements not listed, or inherent to such process, method, article, or apparatus. Furthermore, the terms "first," "second," and "third," etc. are used to distinguish between different objects and are not used to describe a particular order.
In order to explain the technical means of the present invention, the following description will be given by way of specific examples.
Example 1:
one embodiment of the present invention provides a homoepitaxial gallium nitride transistor device structure, which is as follows:
as shown in fig. 1, fig. 1 shows a schematic structural diagram of a homoepitaxial gallium nitride transistor device provided by an embodiment of the present invention, which includes:
the transistor comprises a substrate 1, a channel layer 2 positioned on the substrate 1, a barrier layer 3 positioned on the channel layer 2 and electrodes positioned on the barrier layer 3, wherein the electrodes comprise a source electrode 4, a drain electrode 5 and a gate electrode 6;
the source electrode 4 and the drain electrode 5 are respectively positioned on two sides of the upper surface of the barrier layer 3, and the gate electrode 6 is positioned on the barrier layer 3 between the source electrode 4 and the drain electrode 5;
the thickness range of the channel layer satisfies d is more than or equal to 1nm1Less than or equal to 20nm, and the thickness range of the barrier layer satisfies d2>12nm, said d1Denotes the thickness of the channel layer, d2Indicating the thickness of the barrier layer.
In the present embodiment, as shown in fig. 1, a channel layer 2 is disposed on a substrate 1, a barrier layer 3 is disposed on the channel layer 2, an active electrode 4 and a drain electrode 5 are disposed on both sides of an upper surface of the barrier layer 3, and a gate electrode 6 is disposed between the active electrode 4 and the drain electrode 5 and also disposed on the barrier layer 3.
In the prior art, as shown in fig. 2, fig. 2 shows a schematic structural diagram of a gallium nitride transistor in the prior art, in fig. 2, a main channel 8 exists between a channel layer 2 and a barrier layer 3, electrons exist in the main channel 8, a sub-channel 9 exists between the channel layer 2 and a substrate 1, and electrons exist in the sub-channel 9, so that the leakage of the device is large.
In this embodiment, the thickness of the channel layer is set to be 1nm to 20nm, and the thin channel layer 2 enables electrons in the sub-channel 9 to enter the main channel 8, so that the two-dimensional electron gas concentration of the main channel 8 is increased, and the improvement of the saturation current is facilitated. Meanwhile, the embodiment does not introduce a new process, does not cause new defects, and has the advantages of simple process, low epitaxy cost and reduced epitaxy time.
In the present embodiment, the channel layer 2 is an ultra-thin layer, and the channel layer 2 is not compensated by impurities, which does not cause the phenomena of increased current collapse and decreased saturation current.
In one embodiment, the substrate 1 is a substrate 1 of epitaxial layer gallium nitride on the basis of sapphire, silicon carbide, silicon or diamond.
In one embodiment, the gallium nitride substrate 1 is a pure gallium nitride substrate.
In one embodiment, the channel layer 2 is InmAlnGarN; wherein m is more than or equal to 0 and less than or equal to 1, n is more than or equal to 0 and less than or equal to 0.1, r is more than or equal to 0.9 and less than or equal to 1, and m + n + r is equal to 1.
In one embodiment, the channel layer 2 is InGaN.
In one embodiment, the barrier layer 3 is InxAlyGazN; wherein x is more than or equal to 0 and less than or equal to 0.85, y is more than or equal to 0.15 and less than or equal to 1, z is more than or equal to 0 and less than or equal to 0.85, and x + y + z is equal to 1.
In one embodiment, as shown in fig. 1, further comprising a passivation layer 7, the passivation layer 7 being located on the barrier layer 3 between the source electrode 4 and the gate electrode 6, and between the gate electrode 6 and the drain electrode 5.
In one embodiment, the gate electrode 6 is any one of a T-gate, a straight gate, a Y-gate, a TT-gate, and a U-gate.
In one embodiment, as shown in fig. 3, fig. 3 shows a schematic diagram of another homoepitaxial gallium nitride transistor device structure.
As shown in fig. 3, the gate electrode 6 is a straight gate, the homoepitaxial gan transistor device structure further includes a gate dielectric layer 10, and the gate dielectric layer 10 is located on the barrier layer 3 below the straight gate.
In one embodiment, the gate electrode 6 is a schottky gate.
The inventionEmbodiments provide homoepitaxial gallium nitride transistor device structures comprising: the transistor comprises a substrate 1, a channel layer 2 positioned on the substrate 1, a barrier layer 3 positioned on the channel layer 2 and electrodes positioned on the barrier layer 3, wherein the electrodes comprise a source electrode 4, a drain electrode 5 and a gate electrode 6; the source electrode 4 and the drain electrode 5 are respectively positioned on two sides of the upper surface of the barrier layer 3, and the gate electrode 6 is positioned on the barrier layer 3 between the source electrode 4 and the drain electrode 5; the thickness range of the channel layer satisfies d is more than or equal to 1nm1Less than or equal to 20nm, and the thickness range of the barrier layer satisfies d2>12 nm. By arranging the thin channel layer 2, electrons of the auxiliary channel 9 can enter the heterojunction interface main channel 8 and become controllable electrons of the main channel 8, and accordingly leakage current is reduced.
As an embodiment of the present invention, this embodiment provides a specific homoepitaxial gallium nitride transistor device structure, which includes:
the transistor comprises a substrate 1, a channel layer 2 positioned on the substrate 1, a barrier layer 3 positioned on the channel layer 2 and electrodes positioned on the barrier layer 3, wherein the electrodes comprise a source electrode 4, a drain electrode 5 and a gate electrode 6; the source electrode 4 and the drain electrode 5 are respectively positioned on two sides of the upper surface of the barrier layer 3, and the gate electrode 6 is positioned on the barrier layer 3 between the source electrode 4 and the drain electrode 5; the thickness range of the channel layer satisfies d is more than or equal to 1nm1Less than or equal to 20nm, and the thickness range of the barrier layer satisfies d2>12nm, said d1Denotes the thickness of the channel layer, d2Indicating the thickness of the barrier layer.
Specifically, the channel layer 2 may be GaN.
Specifically, the barrier layer 3 is AlyGazN; wherein y is more than or equal to 0.15 and less than or equal to 1, z is more than or equal to 0 and less than or equal to 0.85, and y + z is equal to 1.
Specifically, the gate electrode 6 is a T-shaped gate.
As another embodiment of the present invention, this embodiment further provides a specific homoepitaxial gallium nitride transistor device structure, which includes:
a substrate 1, a channel layer 2 on the substrate 1, a barrier layer 3 on the channel layer 2, and an electrode on the barrier layer 3The electrodes include a source electrode 4, a drain electrode 5, and a gate electrode 6; the source electrode 4 and the drain electrode 5 are respectively positioned on two sides of the upper surface of the barrier layer 3, and the gate electrode 6 is positioned on the barrier layer 3 between the source electrode 4 and the drain electrode 5; the thickness range of the channel layer satisfies d is more than or equal to 1nm1Less than or equal to 20nm, and the thickness range of the barrier layer satisfies d2>12nm, said d1Denotes the thickness of the channel layer, d2Indicating the thickness of the barrier layer.
In particular, the channel layer 2 does not introduce a journal compensation.
Specifically, the channel layer 2 is InGaN.
Specifically, the barrier layer 3 is shown as InxAlyAnd N, wherein x is more than or equal to 0 and less than or equal to 1, y is more than or equal to 0 and less than or equal to 1, and x + y is equal to 1.
Specifically, the gate electrode 6 is a straight gate, and a dielectric layer is arranged on the upper surface of the barrier layer 3 below the straight gate.
Specifically, the gate is a dielectric gate.
The invention is not limited to the above embodiment, and protects a novel III-nitride material enhanced HEMT structure based on the transverse cutting theory; from the above description of the embodiments, those skilled in the art can make obvious changes, for example, the material of the channel layer 2 is selected from a multilayer composite material, a back barrier structure, a multilayer buffer layer, etc., and the substrate 1 is selected from a SiC, Si, diamond, sapphire, GaN multilayer composite substrate, but these changes should fall into the protection scope of the claims of the present invention.
The above-mentioned embodiments are only used for illustrating the technical solutions of the present invention, and not for limiting the same; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications and substitutions do not substantially depart from the spirit and scope of the embodiments of the present invention, and are intended to be included within the scope of the present invention.
Claims (10)
1. A homoepitaxial gallium nitride transistor device structure, comprising: the transistor comprises a substrate, a channel layer positioned on the substrate, a barrier layer positioned on the channel layer and an electrode positioned on the barrier layer, wherein the electrode comprises a source electrode, a drain electrode and a gate electrode;
the source electrode and the drain electrode are respectively positioned on two sides of the upper surface of the barrier layer, and the gate electrode is positioned on the barrier layer between the source electrode and the drain electrode;
the thickness range of the channel layer satisfies d is more than or equal to 1nm1Less than or equal to 20nm, and the thickness range of the barrier layer satisfies d2>12nm, said d1Denotes the thickness of the channel layer, d2Indicating the thickness of the barrier layer.
2. The homoepitaxial gallium nitride transistor device structure of claim 1, wherein the substrate is a substrate that is epitaxially layered gallium nitride on sapphire, silicon carbide, silicon, or diamond basis.
3. The homoepitaxial gallium nitride transistor device structure of claim 1, wherein the gallium nitride substrate is a pure gallium nitride substrate.
4. The homoepitaxial gallium nitride transistor device structure of claim 1, wherein the channel layer is InmAlnGarN; wherein m is more than or equal to 0 and less than or equal to 1, n is more than or equal to 0 and less than or equal to 0.1, r is more than or equal to 0.9 and less than or equal to 1, and m + n + r is equal to 1.
5. The homoepitaxial gallium nitride transistor device structure of claim 4, wherein the channel layer is InGaN.
6. The homoepitaxial gallium nitride transistor device structure of claim 1, wherein the barrier layer is InxAlyGazN; wherein x is more than or equal to 0 and less than or equal to 0.85, y is more than or equal to 0.15 and less than or equal to 1, z is more than or equal to 0 and less than or equal to 0.85, and x + y + z is equal to 1.
7. The homoepitaxial gallium nitride transistor device structure of claim 1, further comprising a passivation layer on the barrier layer between the source electrode and the gate electrode, and between the gate electrode and the drain electrode.
8. The homoepitaxial gallium nitride transistor device structure of claim 1, wherein the gate electrode is any one of a T-gate, a straight gate, a Y-gate, a TT-gate and a U-gate.
9. The homoepitaxial gallium nitride transistor device structure of claim 8, wherein the gate electrode is a straight gate, the homoepitaxial gallium nitride transistor device structure further comprising a gate dielectric layer on the barrier layer below the straight gate.
10. The homoepitaxial gallium nitride transistor device structure of claim 9, wherein the gate electrode is a schottky gate.
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| CN109273527A (en) * | 2018-11-21 | 2019-01-25 | 芜湖启迪半导体有限公司 | A kind of semiconductor structure and forming method thereof |
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