CN110688260A - EC reset circuit and electronic equipment based on earphone interface - Google Patents
EC reset circuit and electronic equipment based on earphone interface Download PDFInfo
- Publication number
- CN110688260A CN110688260A CN201911030620.9A CN201911030620A CN110688260A CN 110688260 A CN110688260 A CN 110688260A CN 201911030620 A CN201911030620 A CN 201911030620A CN 110688260 A CN110688260 A CN 110688260A
- Authority
- CN
- China
- Prior art keywords
- gate
- signal
- detection circuit
- terminal
- electronic switch
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/14—Error detection or correction of the data by redundancy in operation
- G06F11/1402—Saving, restoring, recovering or retrying
- G06F11/1415—Saving, restoring, recovering or retrying at system level
- G06F11/1441—Resetting or repowering
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Quality & Reliability (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Electronic Switches (AREA)
Abstract
The invention discloses an EC reset circuit based on an earphone interface, which relates to the technical field of electronic circuits and comprises a detection circuit and a control circuit, wherein the input end of the detection circuit is connected with an earphone wire and is used for receiving a forced reset signal output by the earphone wire or a forced reset signal output by external equipment through the earphone wire, and the input end of the detection circuit is also connected with a starting signal end; the output end of the detection circuit is connected with the starting signal end and the enabling signal end of the power supply chip for supplying power to the EC through the control circuit, so that after the detection circuit receives the forced reset signal and the low-level starting signal, the starting signal of the starting signal end and the enabling signal of the enabling signal end are pulled down through the control circuit, and the power supply connection of the EC is disconnected. The embodiment of the invention also discloses electronic equipment comprising the EC reset circuit based on the earphone interface. The embodiment of the invention can complete forced reset only by means of the earphone interface.
Description
Technical Field
The embodiment of the invention relates to the technical field of electronic circuits, in particular to an EC reset circuit based on an earphone interface and electronic equipment.
Background
EC (embedded Controller) is widely used in notebook computers, tablet computers and various industrial personal computers, and is also called KBC (Keyboard Controller) in notebook computers and tablet computers. The EC is high in the system. The EC controls the timing of most important signals during system start-up. After the computer is started, the EC controls equipment such as a keyboard, an indicator light, a fan, a touch panel and the like. In addition, the EC controls the standby, sleep, etc. states of the system.
If the EC is down, it cannot operate, which will affect the stability and operation of the whole system. Conventionally, the power supply equipment and the batteries are removed, but some batteries are built in and inconvenient to operate. At this time, it is necessary to perform an EC reset to allow the entire system to operate normally again.
Disclosure of Invention
In order to overcome the defects of the prior art, the invention aims to provide an EC reset circuit based on an earphone interface and an electronic device, wherein forced reset can be completed only by means of the earphone interface.
In a first aspect, an embodiment of the present invention provides an EC reset circuit based on a headset interface, which includes a detection circuit and a control circuit, where:
the input end of the detection circuit is connected with the earphone wire and used for receiving a forced reset signal output by the earphone wire or a forced reset signal output by an external device through the earphone wire, and the input end of the detection circuit is also connected with a starting signal end;
the output end of the detection circuit is connected with the starting signal end and the enabling signal end of the power supply chip for supplying power to the EC through the control circuit, so that after the detection circuit receives the forced reset signal and the low-level starting signal, the starting signal of the starting signal end and the enabling signal of the enabling signal end are pulled down through the control circuit, and the power supply connection of the EC is disconnected.
In a preferred embodiment, an input end of the detection circuit is connected to an R end of an earphone interface of a local device where the detection circuit is located, and the forced reset signal is a high-level signal generated through the earphone line via the R end;
or;
the input end of the detection circuit is connected with the R end of an earphone interface of local equipment where the detection circuit is located, and the forced reset signal is a high-level signal generated by the earphone cable through the R end; and a divider resistor is connected between the R end and the GND end of the earphone interface.
In a preferred embodiment, the control circuit is an electronic switch, an input end of the electronic switch is respectively connected to the power-on signal end and the enable signal end, an output end of the electronic switch is grounded, and a control end of the electronic switch is connected to an output end of the detection circuit; when the detection circuit receives the forced reset signal and the low-level starting signal, the electronic switch is conducted, and the starting signal and the enabling signal are pulled down.
In a preferred embodiment, the control circuit is two-way, the input ends of the electronic switches of the two-way control circuit are respectively connected to the power-on signal end and the enable signal end, and a pull-down resistor is further connected in series with the electronic switch of any one or two-way control circuit.
In a preferred embodiment, the electronic switch is any one of a triode, a MOS transistor, a relay, an IGBT, a thyristor, and a diode current switch.
In a preferred embodiment, the detection circuit includes an and gate, a microprocessor, and an or gate, where the microprocessor has a first input terminal and a second input terminal, and a first output terminal corresponding to the first input terminal and a second output terminal corresponding to the second input terminal, respectively, both input terminals of the and gate are connected to the R terminal, an output terminal of the and gate is connected to the first input terminal of the microprocessor, both input terminals of the or gate are connected to the first output terminal and the power-on signal terminal, respectively, an output terminal of the or gate is connected to the second input terminal, and the second output terminal is connected to the control terminal of the electronic switch;
when the R end receives a forced reset signal, the first output end outputs a low level, and the second output end outputs a high level;
the AND gate is an independent logic AND gate device or is built through a NAND gate, and the OR gate is an independent OR gate device or is built through a NAND gate.
In a preferred embodiment, the detection circuit comprises a nand gate and a nor gate, wherein two input ends of the nand gate are both connected to the R terminal, two input ends of the nor gate are respectively connected to an output end of the nand gate and a power-on signal terminal, and an output end of the nor gate is connected to a control terminal of the electronic switch;
the NAND gate is an independent logic NAND gate device or is built through an AND gate and a NOR gate, and the NOR gate is an independent NOR gate device or is built through an OR gate and a NOR gate or is built through a NAND gate.
In a preferred embodiment, the electronic switch is an NMOS transistor, a gate of the NMOS transistor is connected to the output terminal of the detection circuit, a source of the NMOS transistor is grounded or grounded through a pull-down resistor, and a drain of the NMOS transistor is connected to the power-on signal terminal and the enable signal terminal.
In a preferred embodiment, the detection circuit comprises a nand gate and an or gate, wherein two input ends of the nand gate are both connected to the R terminal, two input ends of the or gate are respectively connected to an output end of the nand gate and a boot signal terminal, and an output end of the or gate is connected to a control terminal of the electronic switch;
the NAND gate is an independent logic NAND gate device or is built through an AND gate and a NOT gate, and the OR gate is an independent OR gate device or is built through an NAND gate;
the electronic switch is a PMOS (P-channel metal oxide semiconductor) tube, the grid electrode of the PMOS tube is connected to the output end of the OR gate, the source electrode of the PMOS tube is respectively connected to the starting signal end and the enabling signal end, and the drain electrode of the PMOS tube is grounded or grounded through a pull-down resistor.
In a second aspect, an embodiment of the present invention provides an electronic device, which includes the EC reset circuit based on the earphone interface according to the first aspect of the present invention.
Compared with the prior art, the embodiment of the invention receives the forced reset signal sent by the external equipment (which can be an earphone wire) through the earphone interface, thereby disconnecting the power supply connection of the EC according to the forced reset signal, achieving the purpose of forced reset and having flexible operation.
Drawings
Fig. 1 is a schematic block diagram of an EC reset circuit based on a headphone interface of embodiment 1;
FIG. 2 is a circuit schematic of a headset interface;
fig. 3 is a circuit schematic diagram of the EC reset circuit based on the headphone interface of embodiment 4;
fig. 4 is a circuit schematic diagram of the EC reset circuit based on the headphone interface of embodiment 5;
fig. 5 is a circuit schematic diagram of the EC reset circuit based on the headphone interface of embodiment 6;
fig. 6 is a circuit schematic diagram of the EC reset circuit based on the headphone interface of embodiment 7.
In the figure: 11. a USB C-type interface; 12. a detection circuit; 13. a control circuit; 14. a power supply chip; 15. EC; 16. a starting signal terminal; 121. an AND gate; 122. a microprocessor; 123. an OR gate; 124. a first not gate; 125. a second not gate; 126. a NAND gate; 127. a nor gate.
Detailed description of the preferred embodiments
The embodiments of the present invention are further described below with reference to the drawings and the specific embodiments, and it should be noted that, in the premise of no conflict, any combination between the embodiments or technical features described below may form a new embodiment. Except as specifically noted, the materials and equipment used in this example are commercially available.
Example 1:
an EC reset circuit based on an earphone interface forcibly resets an EC in local equipment through external equipment, an earphone interface 11 between the external equipment and the local equipment is connected through an earphone wire, and the earphone wire can also be used as the external equipment to directly forcibly reset the EC.
The local device mainly refers to a device having an EC (embedded Controller), such as a tablet computer or a notebook computer, and may also be various industrial control devices having an EC. The external device may be an electronic device with an earphone interface, such as a tablet computer or a smart phone, in addition to the earphone line, and is provided with a forced circuit module for sending a forced reset signal; of course, the external device may be only one forced circuit module, the forced circuit module may be a microprocessor, an ARM processor, or the like, or may be some touch switches, keys, or the like, as long as it can generate a high-level forced reset signal, the forced circuit module may be used.
In an implementation manner, referring to fig. 1, a detection circuit 12 and a control circuit 13 are disposed in the local device, and an input end of the detection circuit is connected to an earphone cable and a power-on signal end 16, and is configured to receive a forced reset signal generated by the earphone cable and also receive a power-on signal, and the earphone cable directly resets the EC. Certainly, the input end of the detection circuit may also be in communication connection with the external device through an earphone cable, and is configured to receive the forced reset signal generated by the forced circuit module, and also receive the power-on signal, that is, the input end of the detection circuit is connected to the earphone interface and the power-on signal end of the local device, and the output end of the forced circuit module is connected to the earphone interface of the external device, and then the local device is connected to the external device through the earphone cable, and the EC is reset by the external device.
The output end of the detection circuit is connected with the starting signal end and the enabling signal end of the power chip 14 for supplying power to the EC 15 through the control circuit, the output end of the power chip is connected with the power end of the EC, after the detection circuit receives a forced reset signal and a low-level starting signal, the starting signal of the starting signal end and the enabling signal of the enabling signal end are pulled down through the control circuit, so that the power chip stops working, the EC stops working due to power failure, the purpose of forced reset is achieved, and the operation is very flexible.
Example 2:
example 2 is a modification made on the basis of example 1. Embodiment 2 shows an implementation manner of the detection circuit and the control circuit. The external equipment or the earphone cable sends a forced reset signal to the R end of the local equipment; in this case, the detection circuit may be implemented by using a microprocessor or an ARM processor, that is, the level signal at the R end of the earphone interface of the local device is detected by using the microprocessor or the ARM processor to determine whether the level signal is a high-level forced reset signal, and detect whether the power-on signal is a low-level signal, and of course, the detection circuit may also be a logic gate device, which may be specifically described in embodiments 5 to 7.
A common earphone (national standard) has 4 sections (which can be understood as 4 ports), MIC, GND, L, R respectively. The MIC terminal is a microphone, the GND terminal is ground, the L terminal is a left channel, and the R terminal is a right channel. Referring to fig. 2, a voltage dividing resistor R2 is connected in series between the GND terminal and the R terminal to increase the voltage at the R terminal to be higher than the voltage at the normal state, so as to be used as the excitation signal.
The control circuit adopts an electronic switch, the input end of the electronic switch is respectively connected to the starting signal end and the enabling signal end, the output end of the electronic switch is grounded, and the control end of the electronic switch is connected to the output end of the detection circuit; when the detection circuit receives the forced reset signal and the low-level starting signal, the control end of the electronic switch controls the electronic switch to be conducted, and the starting signal and the enabling signal are pulled down. The electronic switch may be any one of a triode, an MOS transistor, a relay, an IGBT, a thyristor, and a diode current switch, and when the triode or the MOS transistor is used, the corresponding electronic switch is selected according to the logic of the selected logic gate device, which may be specifically described in embodiments 4 to 7. Other forms of electronic switches are similar to the MOS transistor and will not be described in detail here, and for the relay, the control terminal is a relay coil part, and the detection circuit receives a forced reset signal to excite the relay coil, and the input terminal and the output terminal of the relay coil are both terminals of the normally closed contact of the relay. For a diode current switch, the control terminal is the enable terminal of the diode current switch.
Example 3:
embodiment 3 is an improvement on the basis of embodiment 1 or 2, in embodiment 3, the control circuit adopts two paths, input ends of electronic switches of the two paths of control circuits are respectively connected to the power-on signal end and the enable signal end, wherein a pull-down resistor is further connected in series to the electronic switch of any one or two paths of control circuits, and preferably the pull-down resistor is connected in series to the enable signal end, that is, the power-on signal of the power-on signal end is directly pulled down to zero.
Example 4:
embodiment 4 is an improvement on embodiments 2 and 3, in embodiment 4, as shown in fig. 3, the detection circuit includes an and gate 121, a microprocessor 122, and an or gate 123, wherein the microprocessor has a first input terminal, a second input terminal, a first output terminal, and a second output terminal, the first input terminal corresponds to the first output terminal, the second input terminal corresponds to the second output terminal, and both input terminals of the and gate are connected to the R terminal, so that both input terminals are connected to the R terminal to filter low level and keep high level, and of course, the and gate may be omitted in some cases. The output end of the AND gate is connected to the first input end of the microprocessor, the two input ends of the OR gate are respectively connected to the first output end and the starting signal end, the output end of the OR gate is connected to the second input end, and the second output end is connected to the control end of the electronic switch.
In the preferred embodiment of the present invention, the and gate may be an independent logic and gate device, or may be built by a nand gate, or the or gate may also be an independent or gate device, or may be built by a nand gate.
The electronic switch is an NMOS tube, the grid electrode of the NMOS tube is connected to the output end of the detection circuit, the source electrode of the NMOS tube is grounded or grounded through a pull-down resistor, and the drain electrode of the NMOS tube is connected to the starting signal end and the enabling signal end (when one path of control circuit is used).
When two control circuits are adopted; the control circuit adopts NMOS pipe, is NMOS pipe Q1 and NMOS pipe Q2 respectively, the grid (as electronic switch's control end) of NMOS pipe Q1 and NMOS pipe Q2 is connected to the second output, the drain-source resistance (as electronic switch's input) of NMOS pipe Q1 and NMOS pipe Q2 is connected to start signal end and enable signal end respectively, the source-source resistance (as electronic switch's output) of NMOS pipe Q1 and NMOS pipe Q2 is ground connection respectively and is ground connection through pull-down resistance R1. When the end R receives a forced reset signal with a high level and a starting signal with a low level, the first output end outputs a low level, the second output end outputs a high level, then the NMOS tube Q1 and the NMOS tube Q2 are conducted, the starting signal and the enabling signal are pulled down, the power supply chip stops working, and the EC is forced to reset.
Example 5:
embodiment 5 is an improvement on the basis of embodiment 4, and in embodiment 5, please refer to fig. 4, the microprocessor in embodiment 4 is built by two not gates, namely, a first not gate 124 and a second not gate 125; two input ends of the and gate are both connected to the R end, an input end of the first not gate 124 is connected to an output end of the and gate, two input ends of the or gate are respectively connected to an output end of the first not gate 124 and the power-on signal end, and an input end and an output end of the second not gate 125 are respectively connected to an output end of the or gate and an input end of the control circuit. The structure of the control circuit is the same as that of embodiment 4, and is not described again here. When the R end receives a forced reset signal with high level and a starting signal with low level, the AND gate outputs high level, the first NOT gate outputs low level, the OR gate outputs low level, the second NOT gate outputs high level, then the PMOS tube Q3 and the PMOS tube Q4 are conducted, the starting signal and the enabling signal are pulled down, the power supply chip stops working, and the EC is forced to reset.
Similarly, the and gate may be an independent logic and gate device, or may be built by a nand gate, or the or gate may also be an independent or gate device, or may be built by a nand gate.
Example 6:
embodiment 6 is an improvement on embodiment 5, and in embodiment 6, as shown in fig. 5, the and gate and the first not gate in embodiment 5 are integrated into a nand gate 126, and the or gate and the second not gate are integrated into a nor gate 127, and other parts are the same as those in embodiment 5, but the nor gate 127 may be formed by building up a plurality of nand gates. When the end R receives a forced reset signal with high level and a starting signal with low level, the NAND gate 126 outputs low level, the NOR gate 127 outputs high level, then the PMOS tube Q3 and the PMOS tube Q4 are conducted, the starting signal and the enabling signal are pulled down, the power supply chip stops working, and the EC is forced to reset
Example 7:
embodiment 7 is a modification of embodiment 5 or embodiment 6, in which the nor gate in embodiment 6 is changed to an or gate, and the NMOS transistor of the control circuit is changed to a PMOS transistor. Referring to fig. 6, the detection circuit includes a nand gate 126 and an or gate 123, wherein two input ends of the nand gate are both connected to the R terminal, two input ends of the or gate are respectively connected to an output end of the nand gate and a boot signal terminal, and an output end of the or gate is connected to a control terminal of the electronic switch; of course, nand gate 126 is a stand-alone logic nand gate device or built through an and gate and a not gate, and or gate 123 is a stand-alone or built through a nand gate.
The electronic switch is a PMOS (P-channel metal oxide semiconductor) transistor which is respectively a PMOS transistor Q3 and a PMOS transistor Q4, the grids of the PMOS transistor Q3 and the PMOS transistor Q4 are connected to the output end of the OR gate 123, the sources of the PMOS transistor Q3 and the PMOS transistor Q4 are respectively connected to the starting signal end and the enabling signal end, and the drains of the PMOS transistor Q3 and the PMOS transistor Q4 are grounded or grounded through a pull-down resistor R3. When the R end receives a forced reset signal with high level and a starting signal with low level, the NAND gate outputs low level, the OR gate outputs low level, then the PMOS tube Q3 and the PMOS tube Q4 are conducted, the starting signal and the enabling signal are pulled down, the power supply chip stops working, and the EC is forced to reset.
Example 8:
embodiment 8 discloses an electronic device, which may be a notebook computer, a tablet computer, an industrial control device, or the like, and which has an EC and an earphone interface; in addition to the EC reset circuit based on the earphone interface in embodiments 1 to 7, the electronic device further includes necessary components, such as a PCB board for mounting components of the EC reset circuit based on the earphone interface and a housing for mounting the PCB board, an output interface, an indicator light, a display screen, etc., and of course, other components, such as a heat sink, etc., may be included as needed.
The above embodiments are only preferred embodiments of the present invention, and the scope of the embodiments of the present invention should not be limited thereby, and any insubstantial changes and substitutions made by those skilled in the art based on the embodiments of the present invention are within the scope of the claims of the embodiments of the present invention.
Claims (10)
1. An EC reset circuit based on a headphone interface, comprising a detection circuit and a control circuit, wherein:
the input end of the detection circuit is connected with the earphone wire and used for receiving a forced reset signal output by the earphone wire or a forced reset signal output by an external device through the earphone wire, and the input end of the detection circuit is also connected with a starting signal end;
the output end of the detection circuit is connected with the starting signal end and the enabling signal end of the power supply chip for supplying power to the EC through the control circuit, so that after the detection circuit receives the forced reset signal and the low-level starting signal, the starting signal of the starting signal end and the enabling signal of the enabling signal end are pulled down through the control circuit, and the power supply connection of the EC is disconnected.
2. The EC reset circuit based on the earphone interface of claim 1, wherein the input terminal of the detection circuit is connected with the R terminal of the earphone interface of the local device where the detection circuit is located, and the forced reset signal is a high-level signal generated through the earphone line via the R terminal;
or;
the input end of the detection circuit is connected with the R end of an earphone interface of local equipment where the detection circuit is located, and the forced reset signal is a high-level signal generated by the earphone cable through the R end; and a divider resistor is connected between the R end and the GND end of the earphone interface.
3. The EC reset circuit based on the earphone interface of claim 2, wherein the control circuit is an electronic switch, the input terminals of the electronic switch are respectively connected to the power-on signal terminal and the enable signal terminal, the output terminal of the electronic switch is grounded, and the control terminal of the electronic switch is connected to the output terminal of the detection circuit; when the detection circuit receives the forced reset signal and the low-level starting signal, the electronic switch is conducted, and the starting signal and the enabling signal are pulled down.
4. The EC reset circuit based on the earphone interface of claim 3, wherein the control circuit is two-way, the input terminals of the electronic switches of the two-way control circuit are respectively connected to the power-on signal terminal and the enable signal terminal, and a pull-down resistor is further connected in series with the electronic switch of any one or two-way control circuit.
5. The EC reset circuit based on the earphone interface as claimed in claim 3 or 4, wherein the electronic switch is any one of a triode, a MOS tube, a relay, an IGBT, a silicon controlled rectifier, and a diode current switch.
6. The headset interface-based EC reset circuit of claim 3, where the detection circuit comprises an and gate, a microprocessor, and an or gate; the microprocessor is provided with a first input end, a second input end, a first output end and a second output end, wherein the first output end corresponds to the first input end, the second output end corresponds to the second input end, the two input ends of the AND gate are connected to the R end, the output end of the AND gate is connected to the first input end of the microprocessor, the two input ends of the OR gate are connected to the first output end and the starting signal end respectively, the output end of the OR gate is connected to the second input end, and the second output end is connected to the control end of the electronic switch;
when the R end receives a forced reset signal, the first output end outputs a low level, and the second output end outputs a high level;
the AND gate is an independent logic AND gate device or is built through a NAND gate, and the OR gate is an independent OR gate device or is built through a NAND gate.
7. The headset interface-based EC reset circuit of claim 3, wherein the detection circuit comprises a nand gate and a nor gate; two input ends of the NAND gate are connected to the R end, two input ends of the NOR gate are connected to the output end of the NAND gate and the starting signal end respectively, and the output end of the NOR gate is connected to the control end of the electronic switch;
the NAND gate is an independent logic NAND gate device or is built through an AND gate and a NOR gate, and the NOR gate is an independent NOR gate device or is built through an OR gate and a NOR gate or is built through a NAND gate.
8. The EC reset circuit based on the earphone interface of claim 6 or 7, wherein the electronic switch is an NMOS tube, the gate of the NMOS tube is connected to the output end of the detection circuit, the source of the NMOS tube is grounded or grounded through a pull-down resistor, and the drain of the NMOS tube is connected to the power-on signal end and the enable signal end.
9. The headset interface-based EC reset circuit of claim 3, wherein the detection circuit comprises a nand gate and an or gate, wherein both inputs of the nand gate are connected to the R terminal, both inputs of the or gate are connected to the output of the nand gate and the power-on signal terminal, respectively, and the output of the or gate is connected to the control terminal of the electronic switch;
the NAND gate is an independent logic NAND gate device or is built through an AND gate and a NOT gate, and the OR gate is an independent OR gate device or is built through an NAND gate;
the electronic switch is a PMOS (P-channel metal oxide semiconductor) tube, the grid electrode of the PMOS tube is connected to the output end of the OR gate, the source electrode of the PMOS tube is respectively connected to the starting signal end and the enabling signal end, and the drain electrode of the PMOS tube is grounded or grounded through a pull-down resistor.
10. An electronic device, characterized in that it comprises a headset interface based EC reset circuit according to any of claims 1 to 9.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911030620.9A CN110688260B (en) | 2019-10-28 | 2019-10-28 | EC reset circuit and electronic equipment based on earphone interface |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911030620.9A CN110688260B (en) | 2019-10-28 | 2019-10-28 | EC reset circuit and electronic equipment based on earphone interface |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN110688260A true CN110688260A (en) | 2020-01-14 |
| CN110688260B CN110688260B (en) | 2023-07-07 |
Family
ID=69114340
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201911030620.9A Active CN110688260B (en) | 2019-10-28 | 2019-10-28 | EC reset circuit and electronic equipment based on earphone interface |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN110688260B (en) |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006109158A (en) * | 2004-10-06 | 2006-04-20 | Olympus Imaging Corp | Electronic device, electronic device system, and audio reproduction system |
| CN2921940Y (en) * | 2005-12-31 | 2007-07-11 | 联想(北京)有限公司 | Resetting device for notebook computer |
| CN101154179A (en) * | 2006-09-29 | 2008-04-02 | 联想(北京)有限公司 | Low-temperature reinforcing system and method for computer |
| CN101645969A (en) * | 2009-05-15 | 2010-02-10 | 上海闻泰电子科技有限公司 | Mobile terminal peripheral circuit system compatible with multiple platforms |
| CN103149996A (en) * | 2012-05-17 | 2013-06-12 | 江苏中科梦兰电子科技有限公司 | System and method for starting up, closing down and resetting hardware of mainboard |
| CN106897237A (en) * | 2017-01-22 | 2017-06-27 | 硅谷数模半导体（北京）有限公司 | The method and apparatus switched by BIOS controlling bus equipment |
| CN109412568A (en) * | 2019-01-03 | 2019-03-01 | 歌尔科技有限公司 | A kind of reset circuit for opening/closing |
-
2019
- 2019-10-28 CN CN201911030620.9A patent/CN110688260B/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006109158A (en) * | 2004-10-06 | 2006-04-20 | Olympus Imaging Corp | Electronic device, electronic device system, and audio reproduction system |
| CN2921940Y (en) * | 2005-12-31 | 2007-07-11 | 联想(北京)有限公司 | Resetting device for notebook computer |
| CN101154179A (en) * | 2006-09-29 | 2008-04-02 | 联想(北京)有限公司 | Low-temperature reinforcing system and method for computer |
| CN101645969A (en) * | 2009-05-15 | 2010-02-10 | 上海闻泰电子科技有限公司 | Mobile terminal peripheral circuit system compatible with multiple platforms |
| CN103149996A (en) * | 2012-05-17 | 2013-06-12 | 江苏中科梦兰电子科技有限公司 | System and method for starting up, closing down and resetting hardware of mainboard |
| CN106897237A (en) * | 2017-01-22 | 2017-06-27 | 硅谷数模半导体（北京）有限公司 | The method and apparatus switched by BIOS controlling bus equipment |
| CN109412568A (en) * | 2019-01-03 | 2019-03-01 | 歌尔科技有限公司 | A kind of reset circuit for opening/closing |
Non-Patent Citations (1)
| Title |
|---|
| 陆正毅: "一种软硬件结合的容错技术研究" * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN110688260B (en) | 2023-07-07 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP5941135B2 (en) | Electronic device having USB interface and USB communication activation method | |
| US8977870B2 (en) | Apparatus for determining a USB compatible device, and supplying corresponding power thereafter | |
| US7949886B2 (en) | Power supply system for motherboard | |
| TWI505083B (en) | Power control circuit and elelctronic device with power control circuit | |
| US20120131243A1 (en) | Multiplexing pin control circuit for computer system | |
| CN110703892A (en) | EC reset circuit and electronic equipment based on USB C type interface | |
| US20120274349A1 (en) | Debug card for motherboard | |
| US8013658B2 (en) | Circuit for controlling time sequence | |
| US8433837B2 (en) | System for connecting electronic devices | |
| US8520350B2 (en) | Protection circuit for digital integrated chip | |
| TW201328096A (en) | Power protection circuit | |
| CN110688260A (en) | EC reset circuit and electronic equipment based on earphone interface | |
| CN107340846B (en) | Power-down prevention logic circuit and notebook computer | |
| CN210488494U (en) | EC reset circuit and electronic equipment based on USB C type interface | |
| US8230251B2 (en) | Time sequence control circuit | |
| US20120250235A1 (en) | Interface module with protection circuit and electronic device | |
| CN110690883A (en) | EC reset circuit and electronic equipment based on composite signal | |
| CN209858632U (en) | Current detection circuit | |
| US20130227311A1 (en) | Power supply device for computer systems | |
| US9501116B2 (en) | Power integrated device and power control method thereof | |
| CN111046395B (en) | EC updating firmware protection circuit and electronic device | |
| CN210518243U (en) | EC reset circuit and electronic equipment based on composite signal | |
| CN110825591B (en) | System information reading method, reading device and electronic equipment | |
| TWI812013B (en) | Over voltage protection circuit for usb type-c port and related method | |
| CN211906032U (en) | Initialization control circuit and electronic equipment |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |