CN110686775A - Digital-to-analog conversion method and circuit - Google Patents
Digital-to-analog conversion method and circuit Download PDFInfo
- Publication number
- CN110686775A CN110686775A CN201910897324.2A CN201910897324A CN110686775A CN 110686775 A CN110686775 A CN 110686775A CN 201910897324 A CN201910897324 A CN 201910897324A CN 110686775 A CN110686775 A CN 110686775A
- Authority
- CN
- China
- Prior art keywords
- data
- circuit
- output
- digital
- conversion
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000006243 chemical reaction Methods 0.000 title claims abstract description 110
- 238000000034 method Methods 0.000 title claims abstract description 29
- 238000002955 isolation Methods 0.000 claims description 17
- 238000012360 testing method Methods 0.000 abstract description 40
- 238000002329 infrared spectrum Methods 0.000 abstract description 13
- 230000000694 effects Effects 0.000 abstract description 5
- 230000004044 response Effects 0.000 description 13
- 230000003595 spectral effect Effects 0.000 description 12
- 238000001228 spectrum Methods 0.000 description 12
- 238000010586 diagram Methods 0.000 description 10
- 230000001360 synchronised effect Effects 0.000 description 7
- 230000008901 benefit Effects 0.000 description 4
- 238000004891 communication Methods 0.000 description 4
- 230000002265 prevention Effects 0.000 description 4
- 230000008569 process Effects 0.000 description 4
- 238000012545 processing Methods 0.000 description 4
- 230000001629 suppression Effects 0.000 description 4
- 230000005540 biological transmission Effects 0.000 description 3
- 230000007613 environmental effect Effects 0.000 description 2
- 230000005457 Black-body radiation Effects 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 238000010998 test method Methods 0.000 description 1
- 230000009466 transformation Effects 0.000 description 1
- 230000001052 transient effect Effects 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01J—MEASUREMENT OF INTENSITY, VELOCITY, SPECTRAL CONTENT, POLARISATION, PHASE OR PULSE CHARACTERISTICS OF INFRARED, VISIBLE OR ULTRAVIOLET LIGHT; COLORIMETRY; RADIATION PYROMETRY
- G01J3/00—Spectrometry; Spectrophotometry; Monochromators; Measuring colours
- G01J3/28—Investigating the spectrum
- G01J3/2803—Investigating the spectrum using photoelectric array detector
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01J—MEASUREMENT OF INTENSITY, VELOCITY, SPECTRAL CONTENT, POLARISATION, PHASE OR PULSE CHARACTERISTICS OF INFRARED, VISIBLE OR ULTRAVIOLET LIGHT; COLORIMETRY; RADIATION PYROMETRY
- G01J3/00—Spectrometry; Spectrophotometry; Monochromators; Measuring colours
- G01J3/02—Details
Landscapes
- Physics & Mathematics (AREA)
- Spectroscopy & Molecular Physics (AREA)
- General Physics & Mathematics (AREA)
- Photometry And Measurement Of Optical Pulse Characteristics (AREA)
- Transforming Light Signals Into Electric Signals (AREA)
Abstract
The invention discloses a digital-to-analog conversion method and a circuit, wherein the method comprises the following steps: decoding the serial data passing through the input interface to obtain parallel decoded data; converting the parallel decoding data based on an FPGA program and outputting the converted data to a digital-analog-Digital (DA) conversion chip; and adjusting the data signal output by the DA conversion chip and then carrying out analog output. The method realizes the conversion of the digitized output on the basis of the existing traditional infrared spectrum testing equipment, and changes the digitized output into the traditional output form, thereby realizing the testing by using the existing equipment and obtaining the positive technical effect.
Description
Technical Field
The invention relates to the technical field of spectral response testing of a digital infrared focal plane detector, in particular to a digital-to-analog conversion method and a digital-to-analog conversion circuit.
Background
The spectral response test of the infrared focal plane detector is an important component in the infrared focal plane test link, and only when the spectral response is accurately tested, a relative spectral response curve can be drawn, so that the corresponding front and back cut-off wavelengths and peak wavelengths are obtained, and further, spectral factors are obtained. After the indexes are accurately tested, the method can be used for calculating indexes such as average peak detection rate, average peak response rate, quantum efficiency and the like. The completeness and the accuracy of the infrared focal plane test index are determined to a great extent by the existence and the accuracy of the test result. In the traditional infrared focal plane detector test, because the output of the infrared focal plane detector is analog voltage, the infrared focal plane detector can test the spectral response of the infrared focal plane detector relative to a spectral response curve test device. However, for the digital infrared focal plane detector, due to different internal structures of the reading circuits, the pixel-level digitalization has single-path output and dozens of paths of parallel output; the column level digitization is also the differential LVDS output, the output difference results in no universal digital infrared focal plane detector spectrum test equipment in the market, and the spectrum response of the detector is an important test index of the detector, thus having great guiding significance for improving the detector process and using by users.
The infrared focal plane spectral response test method has two types: (1) monochromator method: a monochromator is additionally arranged between an infrared focal plane detector window and a black body radiation surface, the detector window receives infrared light separated by the monochromator through a reflector, the distance between the window and the reflector is 20cm-50cm, and then an effective channel is selected for testing; (2) fourier spectrometer method: the window of the infrared focal plane detector is aligned with the light outlet of the Fourier spectrum tester, the distance between the window and the light outlet is 2cm-10cm, an effective channel is selected for testing, Fourier transformation is carried out on signals collected by the channel, and a spectrum curve is output.
FIG. 1 is a schematic diagram of an infrared spectral response test, which is composed of a Fourier spectrometer, a spectrometer control module, a detector to be detected, a detector driving circuit, a signal acquisition and processing module, a computer and the like. The spectrometer control module and the signal acquisition processing module belong to a Fourier spectrometer to form complete infrared spectrum response testing equipment. However, the device only has the signal acquisition capability of an analog output type infrared detector, and cannot acquire a digital output signal, so that the infrared spectrum of a plurality of types of developed digital infrared detectors does not have test conditions. The infrared spectrum testing equipment belongs to high-precision equipment, particularly digital spectrum testing, and only a few foreign manufacturers develop equipment capable of testing the spectrum of a digital infrared detector at present, but the equipment is expensive and not easy to buy.
Therefore, an output conversion circuit which can fully utilize the existing Fourier spectrometer, is practical and reliable and can measure the spectrum of the digital infrared detector is developed to be very urgent.
Disclosure of Invention
The embodiment of the invention provides a digital-to-analog conversion method and a digital-to-analog conversion circuit, which convert digitalized output on the basis of the existing traditional infrared spectrum testing equipment into a traditional output form, thereby realizing the testing by using the existing equipment.
In a first aspect, an embodiment of the present invention provides a digital-to-analog conversion method, where the method includes the following steps:
decoding the serial data passing through the input interface to obtain parallel decoded data;
converting the parallel decoding data based on an FPGA program and outputting the converted data to a digital-analog-Digital (DA) conversion chip;
and adjusting the data signal output by the DA conversion chip and then carrying out analog output.
Optionally, the decoding the data in parallel includes: standard parallel data and clock signals.
Optionally, the converting the parallel decoded data based on the FPGA program and outputting the converted parallel decoded data to the DA conversion chip includes:
under the condition that the frame rate is lower than a given threshold value, converting all the standard parallel data based on an FPGA program and outputting the converted data to a DA conversion chip;
and under the condition that the frame rate is higher than a given threshold value, selecting standard parallel data with specified digits based on the FPGA program, converting the standard parallel data and outputting the converted data to the DA conversion chip.
Optionally, the converting the parallel decoded data based on the FPGA program and outputting the converted parallel decoded data to the DA conversion chip further includes:
and reducing the frequency of the FPGA to a clock range which can be converted by the DA conversion chip, and outputting a frame starting signal, a line starting signal and the clock signal after isolation.
Optionally, the adjusting the data signal output by the DA conversion chip and then performing analog output includes:
and carrying out output range adjustment and drive enhancement on the data signal output by the DA conversion chip through the operational amplifier, and then carrying out analog output.
In a second aspect, an embodiment of the present invention provides a digital-to-analog conversion circuit, including:
the image decoding circuit is used for decoding the serial data passing through the input interface to obtain parallel decoding data;
the FPGA chip circuit is used for converting the parallel decoding data based on an FPGA program and outputting the converted parallel decoding data to a digital-to-analog DA conversion chip;
and the DA conversion circuit is used for adjusting the data signal output by the DA conversion chip and then carrying out analog output.
Optionally, the decoding the data in parallel includes: standard parallel data and clock signals.
Optionally, the FPGA chip circuit is configured to,
under the condition that the frame rate is lower than a given threshold value, converting all the standard parallel data based on an FPGA program and outputting the converted data to a DA conversion chip;
and under the condition that the frame rate is higher than a given threshold value, selecting standard parallel data with specified digits based on the FPGA program, converting the standard parallel data and outputting the converted data to the DA conversion chip.
Optionally, the FPGA chip circuit is further configured to down-convert the FPGA to a clock range convertible by the DA conversion chip, and output a frame start signal, a line start signal, and the clock signal after isolation.
Optionally, the DA conversion circuit further includes an operational amplifier circuit, and the operational amplifier circuit is configured to perform output range adjustment and drive enhancement on the data signal output by the DA conversion chip.
The embodiment of the invention decodes the serial data passing through the input interface to obtain parallel decoding data; converting the parallel decoding data based on an FPGA program and outputting the converted data to a digital-analog-Digital (DA) conversion chip; and adjusting the data signal output by the DA conversion chip and then carrying out analog output. The conversion of digital output on the basis of the existing traditional infrared spectrum testing equipment is realized, and the conversion is changed into a traditional output form, so that the existing equipment is utilized for testing, and a positive technical effect is achieved.
The foregoing description is only an overview of the technical solutions of the present invention, and the embodiments of the present invention are described below in order to make the technical means of the present invention more clearly understood and to make the above and other objects, features, and advantages of the present invention more clearly understandable.
Drawings
Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The drawings are only for purposes of illustrating the preferred embodiments and are not to be construed as limiting the invention. Also, like reference numerals are used to refer to like parts throughout the drawings. In the drawings:
FIG. 1 is a schematic diagram of a prior art infrared spectral response test;
FIG. 2 is a schematic block diagram of a digital-to-analog conversion circuit board of a general digital detector according to a second embodiment of the present invention;
FIG. 3 is a connection diagram of a spectrum test of a simulated infrared detector according to a second embodiment of the present invention;
FIG. 4 is a connection diagram of a second embodiment of a digital infrared detector spectral test according to the present invention;
FIG. 5 is a schematic diagram of a power supply reverse-connection prevention and current limiting protection circuit according to a third embodiment of the present invention;
FIG. 6 is a diagram of a Cameralink image decoding circuit interface according to a third embodiment of the present invention
FIG. 7 is a schematic diagram of a programming interface of a FPGA according to a third embodiment of the present invention;
fig. 8 is a schematic diagram of a DA conversion circuit according to a third embodiment of the present invention;
FIG. 9 is a schematic diagram of an output circuit according to a third embodiment of the present invention.
Detailed Description
Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.
In a first aspect, a first embodiment of the present invention provides a digital-to-analog conversion method, including the steps of:
decoding the serial data passing through the input interface to obtain parallel decoded data;
converting the parallel decoding data based on an FPGA program and outputting the converted data to a digital-analog-Digital (DA) conversion chip;
and adjusting the data signal output by the DA conversion chip and then carrying out analog output.
The embodiment solves the problem that the infrared spectrum of a plurality of styles of digital infrared detectors which are researched and developed does not have the test condition because the current equipment only has the signal acquisition capacity of an analog output type infrared detector and can not acquire a digital output signal, realizes the conversion of digital output on the basis of the existing traditional infrared spectrum test equipment and changes the digital output into the traditional output form, thereby realizing the test by utilizing the existing equipment and obtaining the positive technical effect.
Optionally, the decoding the data in parallel includes: standard parallel data and clock signals.
Specifically, the scheme may be to decode the Cameralink serial LVDS data input through the input interface into standard parallel data and a clock signal.
Optionally, in an optional embodiment of the present invention, the converting the parallel decoded data based on the FPGA program and outputting the converted parallel decoded data to the DA conversion chip includes:
under the condition that the frame rate is lower than a given threshold value, converting all the standard parallel data based on an FPGA program and outputting the converted data to a DA conversion chip;
and under the condition that the frame rate is higher than a given threshold value, selecting standard parallel data with specified digits based on the FPGA program, converting the standard parallel data and outputting the converted data to the DA conversion chip.
Specifically, the method can adapt to different FPGA programs aiming at different digital detectors, and realizes the state switching. Under the condition that the frame frequency is relatively low, the output of the whole frame can be realized, and under the condition that the frame frequency is too high, the output of every other column or a certain row can be adopted, which is similar to the multi-output mode of the traditional analog detector and adopts one path.
More specifically, in this embodiment, for example, the chip selected by the DA circuit has 14-bit analog-to-digital conversion, and in order to improve the signal-to-noise ratio, in this embodiment, the high 14 bits of the valid data may be selected for conversion.
Optionally, in this embodiment, the converting the parallel decoded data based on the FPGA program and outputting the converted parallel decoded data to the DA conversion chip further includes:
and reducing the frequency of the FPGA to a clock range which can be converted by the DA conversion chip, and outputting a frame starting signal, a line starting signal and the clock signal after isolation.
Specifically, when data is output, the synchronous clock signal, the frame start signal and the line start signal are output together with the data, and after DA conversion, the output form is the same as that of the analog infrared detector.
For example, the DA conversion circuit selects a chip having 14-bit digital-to-analog conversion, selects the high 14 bits of valid data for conversion, and simultaneously down-converts to a convertible clock range of the DA chip, and outputs a clock signal, a frame start signal and a line start signal to the output BNC interface, and these signals may also be subjected to interference suppression through a magnetic isolation circuit during transmission.
Optionally, in another optional embodiment of the present invention, the adjusting the data signal output by the DA conversion chip and then performing analog output includes:
and carrying out output range adjustment and drive enhancement on the data signal output by the DA conversion chip through the operational amplifier, and then carrying out analog output.
Specifically, the parallel decoding data is converted based on an FPGA program and then output to a digital-to-analog DA conversion chip, the DA conversion chip converts a parallel digital signal provided by an FPGA main chip circuit into an analog level, the magnetic isolation circuit can also be implemented in a mode of adopting a magnetic isolation chip, the magnetic isolation chip is arranged in front of the DA conversion chip, environmental noise and interference suppression are eliminated through the magnetic isolation chip, an operational amplifier link is arranged behind the DA conversion chip in the embodiment, specifically, the operational amplifier chip can be used for performing analog output after performing output range adjustment and drive enhancement on the data signal output by the DA conversion chip through the operational amplifier chip.
More specifically, on the basis that the chip selected by the DA circuit has 14-bit digital-to-analog conversion, the 14-bit data signal passes through the DA chip, then passes through the first-stage operational amplifier to adjust the output range and enhance the driving capability, and then is output to the output circuit.
In a second aspect, a second embodiment of the present invention provides a digital-to-analog conversion circuit, including:
the image decoding circuit is used for decoding the serial data passing through the input interface to obtain parallel decoding data;
the FPGA chip circuit is used for converting the parallel decoding data based on an FPGA program and outputting the converted parallel decoding data to a digital-to-analog DA conversion chip;
and the DA conversion circuit is used for adjusting the data signal output by the DA conversion chip and then carrying out analog output.
The embodiment solves the problem that the infrared spectrum of a plurality of styles of digital infrared detectors which are researched and developed does not have the test condition because the current equipment only has the signal acquisition capacity of an analog output type infrared detector and can not acquire a digital output signal, realizes the conversion of digital output on the basis of the existing traditional infrared spectrum test equipment and changes the digital output into the traditional output form, thereby realizing the test by utilizing the existing equipment and obtaining the positive technical effect.
Optionally, the decoding the data in parallel includes: standard parallel data and clock signals.
Specifically, in this embodiment, as shown in fig. 2, the image decoding circuit may be a CameraLink image decoding circuit, and the CameraLink image decoding circuit may use a standard CameraLink protocol decoding chip to decode CameraLink serial LVDS data input through the input interface into standard parallel data and a clock signal. The output end of the image decoding circuit is connected with the FPGA chip, and can support an RGB mode (aiming at output above 16 bits) or a base mode (below 16 bits).
Optionally, in an optional embodiment of the present invention, the FPGA chip circuit is configured to,
under the condition that the frame rate is lower than a given threshold value, converting all the standard parallel data based on an FPGA program and outputting the converted data to a DA conversion chip;
and under the condition that the frame rate is higher than a given threshold value, selecting standard parallel data with specified digits based on the FPGA program, converting the standard parallel data and outputting the converted data to the DA conversion chip.
The FPGA chip circuit is a core part of the digital-to-analog conversion circuit, and in this embodiment, the FPGA chip circuit may include an FPGA power supply circuit, an FPGA configuration circuit, an FPGA program download interface, and an RS422 communication interface circuit.
The RS422 communication interface circuit enables the circuit of the invention to have the functions of repeatable programming and external communication control. In this embodiment, the state switching can be realized by adapting different FPGA programs to different digital detectors through the FPGA program download interface.
When the frame rate is relatively low, the full-frame output is possible, and when the frame rate is too high, the column-alternate output or the row output may be adopted.
Optionally, in an optional embodiment of the present invention, the FPGA chip circuit is further configured to down-convert the FPGA to a convertible clock range of the DA conversion chip, and output a frame start signal, a line start signal, and the clock signal after isolation.
Specifically, when data is output, the synchronous clock signal and the frame start signal are output together with the data, and after DA conversion, the output form is the same as that of the analog infrared detector.
For example, the DA conversion circuit selects a chip having 14-bit digital-to-analog conversion, selects the high 14 bits of valid data for conversion, and simultaneously down-converts to a DA convertible clock range, and outputs a clock signal, a frame start signal and a line start signal to the output BNC interface, and these signals may also be subjected to interference suppression via a magnetic isolation circuit during transmission.
Optionally, the DA conversion circuit includes an operational amplifier circuit, and the operational amplifier circuit is used for performing output range adjustment and drive enhancement on the data signal output by the DA conversion chip.
Specifically, in this embodiment, the DA conversion chip converts the parallel digital signal provided by the FPGA main chip circuit into an analog level, and the magnetic isolation circuit may also be implemented in a manner of a magnetic isolation chip, as shown in fig. 2, the magnetic isolation chip is disposed in front of the DA conversion chip, and the magnetic isolation chip eliminates environmental noise and suppresses interference.
More specifically, on the basis that the chip selected by the DA circuit has 14-bit digital-to-analog conversion, the 14-bit data signal passes through the DA chip, then passes through the first-stage operational amplifier to adjust the output range and enhance the driving capability, and then is output to the output circuit.
In an alternative embodiment of the present invention, the input interface and the output interface may be integrated into an interface circuit, for example, the input interface may be a standard Cameralink connector, which converts the digitized detector output data into Cameralink data for input. The output interface can be composed of 4 standard BNC connectors, and respectively outputs a data synchronization clock, an analog output signal, a frame start enable signal and a line start enable signal, and is connected with the acquisition card of the Fourier spectrometer through a coaxial cable, so that the acquisition card can acquire required signals.
In summary, the present invention is a digital-to-analog conversion circuit for a universal infrared detector, and fig. 3 shows a specific connection manner for spectrum testing of an analog infrared detector, in which a signal acquisition board card can be accessed only by performing impedance conversion on an analog level output by the detector; fig. 4 shows a specific connection mode for spectrum testing of a digital infrared detector, wherein due to the diversity of the output of the digital infrared detector, the output is uniformly converted into Cameralink data during testing, and on the basis, the digital-to-analog conversion circuit of the present invention is added, so that the circuit of the present invention can uniformly pack the output into infrared output serial data of the Cameralink protocol, output a certain row or even a certain pixel after passing through an FPGA chip, convert the data into an analog output level the same as the output of the analog infrared detector after passing through a DA chip, and simultaneously output a clock and a frame start enable signal. The three signals are connected with a signal acquisition module of the Fourier spectrometer, so that the digital spectrum can be tested, and an infrared spectrum curve can be obtained. The digital-to-analog conversion circuit has strong universality, can be used for different types and specifications of digital detectors, is convenient to adjust, and has high cost performance, easy operation and recyclable engineering value.
The third embodiment of the present invention provides a digital-to-analog conversion circuit for a general infrared detector, and in this embodiment, the circuit of the present invention is exemplified by taking FPGA processing 28bit data and DA processing 14bit data as examples. The analog-to-digital conversion circuit mainly comprises a power supply reverse connection prevention and current limiting circuit, a CameraLink image decoding circuit, an FPGA main chip circuit, a DA conversion circuit and an interface circuit.
In this embodiment, the digital-to-analog conversion circuit of the digital infrared detector utilizes the input interface to connect the serial CameraLink data converted by the detector data to the decoding circuit, and the decoding circuit automatically decodes the serial LVDS data into parallel 28-bit data information, which includes frame, row and data valid signals, and also outputs a data synchronization clock signal.
Parallel 28bit data information is disassembled and selected in an FPGA (field programmable gate array) by combining with the area array specification or the line array specification of a detected detector, as a Fourier spectrometer can carry out spectrum test on a unit at least, all line array pixels are selected to carry out conversion of the next step, and the middle line of the area array pixels is selected to carry out conversion of the next step. Interference suppression is carried out on the 14-bit data signals through the magnetic isolation circuit in the transmission process, and the 14-bit data signals are output to the output circuit after passing through the DA chip and then through the first-stage operational amplifier to adjust the output range and enhance the driving capability.
Specifically, in the embodiment, the interface circuit includes an input interface and an output interface, the input interface may be a standard Cameralink connector, and the digital detector output data may be converted into Cameralink data for input. The output interface can be composed of 4 standard BNC connectors, and respectively outputs a data synchronization clock, an analog output signal, a frame start enable signal and a line start enable signal, and is connected with the acquisition card of the Fourier spectrometer through a coaxial cable, so that the acquisition card can acquire required signals.
The power supply reverse connection prevention and current limiting circuit is composed of a fuse wire and a diode as shown in fig. 5, and mainly performs current limiting protection on input voltage through the fuse wire and provides circuit protection for the condition that the positive and negative of a power supply are reversely connected due to possible misoperation. In fig. 5, D1 is a schottky diode, F1 is a fuse, VIN is a positive power supply, vingdd is a negative power supply, the positive electrode of D1 is externally connected to the negative power supply, the negative electrode of D1 is connected to the fuse, and the other end of the fuse is connected to the positive power supply. Meanwhile, the power supply also supplies power to the circuit main module, and when the power supply is connected reversely by mistake, due to the unidirectional conduction characteristic of the D1 diode, other modules of the digital-to-analog conversion circuit can be protected from being damaged by wrong connection; when the current is larger than a certain value, the fuse wire is fused to cut off the power supply, and the overload protection effect is achieved.
The CameraLink image decoding circuit, as shown in fig. 6, the left 5 pairs of differential signals are CameraLink serial data, which are introduced by the front-end interface, and output to the right 28-bit parallel data and 1 synchronous clock signal through the image decoding chip. Wherein, the 28bit data includes 24bit data information, namely the output code value of the digital detector, in addition, 4 bits represent the frame, line, data effective information and 1bit empty information of the image respectively, and the 29 output ends are all connected with the FPGA chip.
The FPGA chip circuit includes an FPGA power supply circuit, an FPGA configuration circuit, an FPGA program download interface, and an RS422 communication interface circuit, as shown in fig. 7, in this embodiment, the J3 connector is a JTAG interface and is a program programming interface of the FPGA chip, and the interface is a convenient programming interface to adapt to spectral response tests of digital infrared detectors of different specifications. In this embodiment, a U8 chip is further provided, and the U8 chip is used for suppressing the transient voltage of the ultra-low capacitor, so as to protect the JTAG interface and prevent the FPGA chip from being electrostatically broken down.
Further, as shown in fig. 8, a programming sequence in the FPGA chip circuit outputs a high 14-bit code value and a synchronous clock signal of the digital detector, and the high 14-bit code value and the synchronous clock signal are converted into two analog signals with opposite polarities through the DA chip. The two paths of outputs are used as two paths of inputs of the operational amplifier, and the two paths of inputs are amplified by one time; and a reference voltage is provided; and finally, the driving capability of the rear-stage output is enhanced through the first-stage operational amplifier.
As shown in fig. 9, the MC _ OUT signal is a synchronous clock of the DA chip to analog signal, the LAVL _ OUT signal is a line start enable signal of the analog output signal, and the FVAL _ OUT signal is a frame start enable signal of the analog output signal. In order to improve the signal-to-noise ratio of the acquisition end of the acquisition card of the fourier spectrometer, the output ends of the digital-to-analog conversion circuits in the embodiment are connected with an RC filter circuit to filter high-frequency interference, and then are respectively connected to BNC interfaces.
The invention adopts the FPGA chip and the DA chip, and utilizes the magnetic isolation module and the output operational amplifier to restrain various interference noises, thereby improving the signal-to-noise ratio; the output of the digital infrared detector is converted into the same form as that of the analog infrared detector, the purpose of testing the infrared spectrum of the infrared detector by using the existing Fourier spectrometer equipment is achieved, and the infrared spectrum testing circuit has the advantages of compact layout, strong anti-interference capability, reverse connection prevention of a power supply, overcurrent protection, simple interface and the like. Meanwhile, the output of analog level conversion can be carried out aiming at infrared detectors with different specifications and different output digits, and the output level synchronous clock frequency can be adjusted.
The invention has simple interface and certain universality, can carry out the conversion of digital-to-analog signals for different types of sensors as long as the output is Cameralink serial data, and can output a frame line start enabling signal to finish various applications, thereby having the capability of mass production of products.
It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
The above-mentioned serial numbers of the embodiments of the present invention are merely for description and do not represent the merits of the embodiments.
Through the above description of the embodiments, those skilled in the art will clearly understand that the method of the above embodiments can be implemented by software plus a necessary general hardware platform, and certainly can also be implemented by hardware, but in many cases, the former is a better implementation manner. Based on such understanding, the technical solutions of the present invention may be embodied in the form of a software product, which is stored in a storage medium (such as ROM/RAM, magnetic disk, optical disk) and includes instructions for enabling a terminal (such as a mobile phone, a computer, a server, an air conditioner, or a network device) to execute the method according to the embodiments of the present invention.
While the present invention has been described with reference to the embodiments shown in the drawings, the present invention is not limited to the embodiments, which are illustrative and not restrictive, and it will be apparent to those skilled in the art that various changes and modifications can be made therein without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (10)
1. A method of digital to analog conversion, the method comprising the steps of:
decoding the serial data passing through the input interface to obtain parallel decoded data;
converting the parallel decoding data based on an FPGA program and outputting the converted data to a digital-analog-Digital (DA) conversion chip;
and adjusting the data signal output by the DA conversion chip and then carrying out analog output.
2. The method of claim 1, wherein the decoding data in parallel comprises: standard parallel data and clock signals.
3. The method of claim 2, wherein the converting the parallel decoded data based on the FPGA program and outputting the converted parallel decoded data to a DA conversion chip comprises:
under the condition that the frame rate is lower than a given threshold value, converting all the standard parallel data based on an FPGA program and outputting the converted data to a DA conversion chip;
and under the condition that the frame rate is higher than a given threshold value, selecting standard parallel data with specified digits based on the FPGA program, converting the standard parallel data and outputting the converted data to the DA conversion chip.
4. The method of claim 3, wherein the parallel decoded data is converted by the FPGA-based program and then output to a DA conversion chip, further comprising:
and reducing the frequency of the FPGA to a clock range which can be converted by the DA conversion chip, and outputting a frame starting signal, a line starting signal and the clock signal after isolation.
5. The method of claim 4, wherein the adjusting the data signal output by the DA conversion chip to perform analog output comprises:
and carrying out output range adjustment and drive enhancement on the data signal output by the DA conversion chip through an operational amplifier circuit, and then carrying out analog output.
6. A digital-to-analog conversion circuit, the circuit comprising:
the image decoding circuit is used for decoding the serial data passing through the input interface to obtain parallel decoding data;
the FPGA chip circuit is used for converting the parallel decoding data based on an FPGA program and outputting the converted parallel decoding data to a digital-to-analog DA conversion chip;
and the DA conversion circuit is used for adjusting the data signal output by the DA conversion chip and then carrying out analog output.
7. The circuit of claim 6, wherein the parallel decoding of data comprises: standard parallel data and clock signals.
8. The circuit of claim 7, wherein the FPGA chip circuit is to,
under the condition that the frame rate is lower than a given threshold value, converting all the standard parallel data based on an FPGA program and outputting the converted data to a DA conversion chip;
and under the condition that the frame rate is higher than a given threshold value, selecting standard parallel data with specified digits based on the FPGA program, converting the standard parallel data and outputting the converted data to the DA conversion chip.
9. The circuit of claim 8, wherein the FPGA chip circuit is further configured to down-convert the FPGA to a switchable clock range of the DA conversion chip and to isolate the frame start signal, the row start signal, and the clock signal for signal output.
10. The circuit of claim 9, wherein the DA conversion circuit further comprises an operational amplifier circuit for performing output range adjustment and drive enhancement on the data signal output by the DA conversion chip.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910897324.2A CN110686775B (en) | 2019-09-23 | 2019-09-23 | Digital-to-analog conversion method and circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910897324.2A CN110686775B (en) | 2019-09-23 | 2019-09-23 | Digital-to-analog conversion method and circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN110686775A true CN110686775A (en) | 2020-01-14 |
| CN110686775B CN110686775B (en) | 2022-03-11 |
Family
ID=69109867
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201910897324.2A Active CN110686775B (en) | 2019-09-23 | 2019-09-23 | Digital-to-analog conversion method and circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN110686775B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114279571A (en) * | 2021-12-03 | 2022-04-05 | 中国电子科技集团公司第十一研究所 | Infrared focal plane outgoing circuit chip and preparation method thereof |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6041374A (en) * | 1994-04-29 | 2000-03-21 | Psc Inc. | PCMCIA interface card for coupling input devices such as barcode scanning engines to personal digital assistants and palmtop computers |
| CN2631157Y (en) * | 2003-08-08 | 2004-08-04 | 北京算通数字技术研究中心有限公司 | Video output connector for digital image equipment |
| CN1731861A (en) * | 2004-10-15 | 2006-02-08 | 中国科学院长春光学精密机械与物理研究所 | A kind of method that realizes the multiple image sensor information processing |
| CN104615153A (en) * | 2015-02-09 | 2015-05-13 | 哈尔滨工业大学 | TMX320F28335 floating point DSP (Digital Signal Processor) based two-shaft photoelectric tracking system |
| CN109150190A (en) * | 2018-07-31 | 2019-01-04 | 江门市蒙德电气股份有限公司 | A kind of transmission matching system for analog-digital converter |
-
2019
- 2019-09-23 CN CN201910897324.2A patent/CN110686775B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6041374A (en) * | 1994-04-29 | 2000-03-21 | Psc Inc. | PCMCIA interface card for coupling input devices such as barcode scanning engines to personal digital assistants and palmtop computers |
| CN2631157Y (en) * | 2003-08-08 | 2004-08-04 | 北京算通数字技术研究中心有限公司 | Video output connector for digital image equipment |
| CN1731861A (en) * | 2004-10-15 | 2006-02-08 | 中国科学院长春光学精密机械与物理研究所 | A kind of method that realizes the multiple image sensor information processing |
| CN104615153A (en) * | 2015-02-09 | 2015-05-13 | 哈尔滨工业大学 | TMX320F28335 floating point DSP (Digital Signal Processor) based two-shaft photoelectric tracking system |
| CN109150190A (en) * | 2018-07-31 | 2019-01-04 | 江门市蒙德电气股份有限公司 | A kind of transmission matching system for analog-digital converter |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114279571A (en) * | 2021-12-03 | 2022-04-05 | 中国电子科技集团公司第十一研究所 | Infrared focal plane outgoing circuit chip and preparation method thereof |
| CN114279571B (en) * | 2021-12-03 | 2024-03-22 | 中国电子科技集团公司第十一研究所 | Infrared focal plane readout circuit chip and preparation method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| CN110686775B (en) | 2022-03-11 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR20240052883A (en) | Optical-fingerprint detection system | |
| CN110686775B (en) | Digital-to-analog conversion method and circuit | |
| CN208092177U (en) | A kind of new ultra-violet imager based on the correction of ultraviolet light subnumber | |
| CN105451017A (en) | Camera module photosensitive quality detection method and device | |
| US20120249241A1 (en) | Light receiving circuit with differential output | |
| US20130093910A1 (en) | Image sensor and image processing apparatus including the same | |
| CN110620920A (en) | Vehicle-mounted camera testing device and vehicle-mounted camera testing system | |
| CN112399101A (en) | Method and system for increasing PSRR compensation range in image sensor | |
| CN102017410B (en) | Switched-capacitor decimator | |
| EP2726888A1 (en) | Method and device for controlling a gas-insulated high-voltage electrical substation | |
| CN106331542B (en) | High dynamic circuit of focal plane readout and its method of sampling | |
| CN113300776B (en) | Circuit and method for improving top-adjusting sensitivity | |
| CN208061187U (en) | Audio input fault detection circuit and program request apparatus | |
| CN106058860B (en) | A kind of full wave voltage comprehensive measurement device suitable for multiple voltage grade transformer substation | |
| CN103675626B (en) | Photon type location ultraviolet detection method | |
| US8847139B2 (en) | Methods, sub-systems and systems that reduce a mismatch error associated with an analog circuit | |
| CA3117002A1 (en) | Ultra-high dynamic range cmos sensor | |
| CN102135583A (en) | Automatic detecting device for detecting short circuit unusualness of internal circuit and shell of optical module | |
| CN217213004U (en) | Cable discharge detection equipment | |
| CN109120289A (en) | A kind of short-wave radio frequency front end processing block and method | |
| CN105116220A (en) | Signal analyzing device used for synchronously separating signals and noise and analyzing method thereof | |
| CN213072679U (en) | Multi-path optical signal detection circuit of wavelength division semi-active switching protection device | |
| CN110601724B (en) | Weak photoelectric signal anti-interference long-distance transmission system | |
| US20230396223A1 (en) | Electronic integration circuit having offset and collected charge reduction circuitries and associated methods | |
| CN107396008A (en) | A kind of cmos image sensor low noise reading circuit and its reading method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |