CN110677134A - Self-adaptive bandwidth adjusting circuit - Google Patents
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Abstract
A self-adaptive bandwidth adjusting circuit comprises a low-frequency gain stage, a high-frequency gain stage, a detection circuit and a comparison circuit, wherein the low-frequency gain stage amplifies low-frequency components of input signals of the self-adaptive bandwidth adjusting circuit to obtain a first amplified signal; the high-frequency gain stage amplifies the high-frequency component of the input signal of the adaptive bandwidth adjusting circuit to obtain a second amplified signal; the detection circuit comprises at least one detection module, the detection module is used for amplifying the first amplification signal and the second amplification signal after superposition to obtain a third amplification signal, outputting a peak value obtained by subtracting a set threshold value from a low-frequency component in the third amplification signal and a peak value of a high-frequency component in the third amplification signal to the comparison circuit for comparison, and adjusting the gain of the high-frequency gain stage according to a comparison result to realize bandwidth adjustment. The invention can quickly respond the change of the high-frequency gain of the signal in real time to adjust the bandwidth, does not generate bandwidth overshoot or improper adjustment, and realizes the characteristic of wide application range by setting different set thresholds.
Description
Technical Field
The invention relates to a self-adaptive bandwidth adjusting circuit which can be applied to an optical communication chip for automatic bandwidth adjustment.
Background
In an optical communication chip, the bandwidth of a transimpedance amplifier is designed to be 0.8 times of the transmission rate, so that a good compromise can be made between sensitivity and intersymbol interference. However, the bandwidth of the transimpedance amplifier is not only related to the circuit of the transimpedance amplifier, but also related to parameters of packaging and external components, such as parasitic capacitance of a photodiode, input bonding inductance and the like. Therefore, the design of the bandwidth of the transimpedance amplifier circuit is challenged, the same transimpedance amplifier chip is provided with photodiodes of different manufacturers, and the package of the same transimpedance amplifier chip in different manufacturers has larger bandwidth difference, which directly causes the inconsistency of the performance and finally causes the poor adaptability and portability of the transimpedance amplifier circuit.
In an optical communication chip, in order to satisfy a sufficient receiving dynamic range, a variable gain control circuit is generally integrated to control a transimpedance in a transimpedance amplifier, and when an input optical power is high, the variable gain control circuit reduces the transimpedance of the transimpedance amplifier to receive a larger input signal, as shown in fig. 1, a schematic diagram of the transimpedance amplifier of the integrated variable gain control circuit is shown. The transimpedance changes greatly along with the change of the size of an input signal, but the bandwidth of a link does not change greatly, and the decrease of the transimpedance inevitably brings the increase of the bandwidth of the transimpedance amplifier, if the bandwidth is not adjusted in time, the overshoot of an output signal is larger, an eye pattern is closed, and Jitter is increased. To address this problem, conventional solutions achieve adjusting the bandwidth of the transimpedance amplifier by adjusting the compensation network of the transimpedance amplifier while the variable gain control circuit adjusts the transimpedance. However, the input variable for adjusting the bandwidth by the method is the amplitude of the signal, and if the link does not need to adjust the bandwidth and the amplitude of the signal reaches the adjustment threshold, the bandwidth is adjusted, so that the overshoot is caused; if the link needs bandwidth adjustment and the signal amplitude does not reach the adjustment threshold, the bandwidth adjustment is not performed, so that the adjustment is not in place.
Disclosure of Invention
Aiming at the defects that the bandwidth of a link is difficult to keep stable under different environments, different input conditions and the like, and the traditional bandwidth adjusting method causes overshoot or cannot be adjusted, the invention provides a self-adaptive bandwidth adjusting circuit which can be applied to a signal link of a chip.
The technical scheme of the invention is as follows:
a self-adaptive bandwidth adjusting circuit comprises a low-frequency gain stage, a high-frequency gain stage, a detection circuit and a comparison circuit,
the input end of the low-frequency gain stage is connected with the input signal of the self-adaptive bandwidth adjusting circuit, and the output end of the low-frequency gain stage outputs a first amplified signal obtained by amplifying the low-frequency component of the input signal of the self-adaptive bandwidth adjusting circuit;
the input end of the high-frequency gain stage is connected with the input signal of the self-adaptive bandwidth adjusting circuit, and the output end of the high-frequency gain stage outputs a second amplified signal obtained by amplifying the high-frequency component of the input signal of the self-adaptive bandwidth adjusting circuit;
the detection circuit comprises at least one detection module, the input end of the detection module is connected with the first amplification signal and the second amplification signal and is used for superposing and amplifying the first amplification signal and the second amplification signal to obtain a third amplification signal, the first output end of the detection module is connected with the first output end of the detection circuit and outputs a peak value obtained by subtracting a set threshold value from a low-frequency component in the third amplification signal, and the second output end of the detection module is connected with the second output end of the detection circuit and outputs a peak value of a high-frequency component in the third amplification signal;
the comparison circuit is used for comparing the output signals of the two output ends of the detection circuit and controlling the gain of the high-frequency gain stage according to the comparison result, when the output signal of the first output end of the detection circuit is detected to be larger than the output signal of the second output end of the detection circuit, the gain of the high-frequency gain stage is improved, and when the output signal of the first output end of the detection circuit is detected to be smaller than the output signal of the second output end of the detection circuit, the gain of the high-frequency gain stage is reduced until the output signals of the two output ends of the detection circuit are equal.
Specifically, the comparison circuit comprises a second amplifier, a third amplifier, a fourteenth resistor, a fifteenth resistor, a sixteenth resistor and a seventeenth resistor,
the positive input end of the second amplifier is connected with the second output end of the detection circuit and is connected with the power supply voltage after passing through the fifteenth resistor, the negative input end of the second amplifier is connected with the first output end of the detection circuit and is connected with the power supply voltage after passing through the fourteenth resistor, and the output end of the second amplifier is connected with the positive input end of the third amplifier;
the negative input end of the third amplifier is connected with the second reference voltage, the positive output end of the third amplifier outputs a positive output signal of the comparison circuit and is connected with one end of the seventeenth resistor, and the negative output end of the third amplifier outputs a negative output signal of the comparison circuit and is connected with the other end of the seventeenth resistor after passing through the sixteenth resistor.
Specifically, the low-frequency gain stage comprises a first resistor, a second resistor, a third resistor, a fourth resistor, a first constant current source, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor and a fourth NMOS transistor,
the grid electrode of the first NMOS tube is used as the positive input end of the low-frequency gain stage, the source electrode of the first NMOS tube is connected with one end of the first resistor, and the drain electrode of the first NMOS tube is connected with the source electrode of the third NMOS tube;
the grid electrode of the second NMOS tube is used as the negative input end of the low-frequency gain stage, the source electrode of the second NMOS tube is connected with one end of the second resistor, and the drain electrode of the second NMOS tube is connected with the source electrode of the fourth NMOS tube;
the other end of the first resistor is connected with the other end of the second resistor and is grounded after passing through the first constant current source;
the grid electrode of the third NMOS tube is connected with the grid electrode of the fourth NMOS tube and is connected with the connection point of the sixteenth resistor and the seventeenth resistor in the comparison circuit, and the drain electrode of the third NMOS tube is used as the negative output end of the low-frequency gain stage and is connected with power supply voltage after passing through the third resistor;
and the drain electrode of the fourth NMOS tube is used as the forward output end of the low-frequency gain stage and is connected with a power supply voltage after passing through a fourth resistor.
Specifically, the high-frequency gain stage comprises a fifth resistor, a first capacitor, a fifth NMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, an eighth NMOS transistor, a ninth NMOS transistor, a tenth NMOS transistor, a second constant current source and a third constant current source,
the grid electrode of the fifth NMOS tube is used as the positive input end of the high-frequency gain stage, the source electrode of the fifth NMOS tube is connected with one end of the first capacitor and is grounded after passing through the second constant current source, and the drain electrode of the fifth NMOS tube is connected with the source electrodes of the seventh NMOS tube and the eighth NMOS tube;
a grid electrode of the sixth NMOS tube is used as a negative input end of the high-frequency gain stage, a source electrode of the sixth NMOS tube is connected with the other end of the first capacitor and is grounded after passing through a third constant current source, and a drain electrode of the sixth NMOS tube is connected with source electrodes of the ninth NMOS tube and the tenth NMOS tube;
the grid electrode of the seventh NMOS tube is connected with the grid electrode of the ninth NMOS tube and a negative output signal of the comparison circuit, and the drain electrode of the seventh NMOS tube is used as a negative output end of the high-frequency gain stage;
the grid electrode of the eighth NMOS tube is connected with the grid electrode of the tenth NMOS tube and a positive output signal of the comparison circuit, and the drain electrode of the eighth NMOS tube is connected with the drain electrode of the tenth NMOS tube and is connected with a power supply voltage after passing through a fifth resistor;
the drain electrode of the ninth NMOS tube is used as the positive output end of the high-frequency gain stage;
by setting the voltage value of the second reference voltage and the gain of the third amplifier OP3 in the comparison circuit, the current of the seventh NMOS transistor M7 and the current of the eighth NMOS transistor M8 branch in the high-frequency gain stage are both enabled to flow through the eighth NMOS transistor M8, and the current of the ninth NMOS transistor M9 and the current of the tenth NMOS transistor M10 branch in the high-frequency gain stage are both enabled to flow through the tenth NMOS transistor M10.
Specifically, the detection module includes a first amplifier, a second capacitor, a third capacitor, a fourth capacitor, a fifth capacitor, a sixth capacitor, a seventh capacitor, a sixth resistor, a seventh resistor, an eighth resistor, a ninth resistor, a tenth resistor, an eleventh resistor, a twelfth resistor, a thirteenth resistor, an eleventh NMOS transistor, a twelfth NMOS transistor, a thirteenth NMOS transistor, a fourteenth NMOS transistor, and a fourth constant current source,
a positive input end of the first amplifier is used as a positive input end of the detection module, a negative input end of the first amplifier is used as a negative input end of the detection module, a positive output end of the first amplifier is connected with one end of the second capacitor and one end of the fourth capacitor, and a negative output end of the first amplifier is connected with one end of the third capacitor and one end of the fifth capacitor;
the grid electrode of the eleventh NMOS tube is connected with one end of the sixth resistor and one end of the tenth resistor and is grounded through the sixth capacitor, the source electrode of the eleventh NMOS tube is connected with the source electrodes of the twelfth NMOS tube, the thirteenth NMOS tube and the fourteenth NMOS tube and is grounded through the fourth constant current source, and the drain electrode of the eleventh NMOS tube is connected with the drain electrode of the twelfth NMOS tube and serves as the first output end of the detection module;
the other end of the sixth resistor is connected with the other end of the second capacitor;
the grid electrode of the twelfth NMOS tube is connected with one end of the seventh resistor and one end of the eleventh resistor and is grounded through the seventh capacitor;
the other end of the seventh resistor is connected with the other end of the third capacitor;
the grid electrode of the thirteenth NMOS tube is connected with one end of the thirteenth resistor and is connected with the other end of the fourth capacitor after passing through the eighth resistor, and the drain electrode of the thirteenth NMOS tube is connected with the drain electrode of the fourteenth NMOS tube and serves as a second output end of the detection module;
a grid electrode of the fourteenth NMOS tube is connected with one end of the twelfth resistor and is connected with the other end of the fifth capacitor after passing through the ninth resistor;
the other end of the tenth resistor, the other end of the eleventh resistor, the other end of the twelfth resistor and the other end of the thirteenth resistor are connected to a first reference voltage.
Specifically, the sixth capacitor and the seventh capacitor in the detection module are a single capacitor or a capacitor array.
Specifically, when the sixth capacitor and the seventh capacitor in the detection module are capacitor arrays, the capacitor arrays have a trimming function.
The invention has the beneficial effects that: the invention can detect the signal in real time, and adjust the high-frequency gain of the signal in real time according to the comparison result of the high-frequency component peak value of the current signal and the peak value of the low-frequency component after passing through the threshold value network, thereby realizing the quick and real-time response to the change of the high-frequency gain of the signal and being particularly suitable for a link with a variable gain control circuit; the invention avoids the bandwidth overshoot or the situation that the adjustment is not in place, and the bandwidth can be kept stable when a large signal or a small signal is input; in addition, different bandwidth thresholds can be set by setting different capacitance values of the sixth capacitor C6 and the seventh capacitor C7, so that the requirements of different scheme applications on link bandwidth are met, and the method has the characteristics of flexibility and changeability.
Drawings
Fig. 1 is a schematic diagram of a transimpedance amplifier of an integrated variable gain control circuit.
Fig. 2 is a block diagram of an implementation of applying the adaptive bandwidth adjusting circuit of the present invention to an optical communication chip.
Fig. 3 is a specific circuit implementation form of an adaptive bandwidth adjusting circuit according to an embodiment of the present invention.
Fig. 4 is a block diagram of an implementation in which a detector circuit in an adaptive bandwidth adjusting circuit according to the present invention includes 3 detector modules.
Detailed Description
The technical solution of the present invention is described in detail below with reference to the accompanying drawings and examples.
The adaptive bandwidth adjusting circuit provided by the invention can adaptively adjust the bandwidth of a signal link, and is explained below by taking the application of the invention between a second stage and a third stage in an optical communication TIA chip as an example, the optical communication TIA chip is generally divided into a first-stage transimpedance amplifier, a second-stage single-to-dual circuit and a third-stage output driving stage, as shown in fig. 2, a pre-stage amplifier is the first-stage transimpedance amplifier and the second-stage single-to-dual circuit of the optical communication TIA chip, and the output of the pre-stage amplifier is used as an input signal of the invention; the post amplifier is a third-stage output driving stage of the optical communication TIA chip, and the output of the low-frequency gain stage and the output of the high-frequency gain stage are used as input signals of the post amplifier.
As shown in fig. 2, the adaptive bandwidth adjusting circuit provided by the present invention includes a low frequency gain stage, a high frequency gain stage, a detection circuit and a comparison circuit, and the high frequency gain of the link is adjusted according to the comparison result by comparing the peak value of the low frequency component of the output signal of the transimpedance amplifier in the optical communication TIA chip after passing through the threshold network with the peak value of the high frequency component, thereby realizing automatic bandwidth adjustment.
The input signals of the low-frequency gain stage and the high-frequency gain stage are the output of the pre-amplifier, and the setting of the low-frequency gain stage should not influence the frequency of the output signal of the pre-amplifierThe low-frequency gain stage is configured to amplify a low-frequency component of an output (i.e., an input signal of the adaptive bandwidth adjusting circuit) of the preamplifier to obtain a first amplified signal, as shown in fig. 3, an implementation form of the low-frequency gain stage 31 is given, in this embodiment, the input signal of the adaptive bandwidth adjusting circuit is a differential signal, and the low-frequency gain stage includes a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a first constant current source, a first NMOS transistor M1, a second NMOS transistor M2, a third NMOS transistor M3, and a fourth NMOS transistor M4, a gate of the first NMOS transistor M1 is used as a forward input end of the low-frequency gain stage, a source of the first NMOS transistor M1 is connected to one end of the first resistor R1, and a drain of the first NMOS transistor M3 is connected to a source of the first NMOS transistor M4; the grid electrode of the second NMOS tube M2 is used as the negative input end of the low-frequency gain stage, the source electrode of the second NMOS tube M2 is connected with one end of a second resistor R2, and the drain electrode of the second NMOS tube M4 is connected with the source electrode of the fourth NMOS tube; the other end of the first resistor R1 is connected with the other end of the second resistor R2 and is grounded after passing through the first constant current source; the grid electrode of the third NMOS tube M3 is connected with the grid electrode of the fourth NMOS tube M4 and is connected with a common-mode voltage VCMThe drain electrode of the low-frequency gain stage is used as the negative output end of the low-frequency gain stage and is connected with a power supply voltage after passing through a third resistor R3; the drain of the fourth NMOS transistor M4 is used as the forward output terminal of the low frequency gain stage and is connected to the power supply voltage through the fourth resistor R4. Common mode voltage V in the present embodimentCMPreferably, the output voltage is generated by a connection point of a sixteenth resistor R16 and a seventeenth resistor R17 in the comparison circuit.
The high-frequency gain stage is configured to amplify a high-frequency component of an output (i.e., an input signal of the adaptive bandwidth adjusting circuit) of the preamplifier to obtain a second amplified signal, and a gain of the high-frequency gain stage can be adjusted according to a comparison result of the comparison circuit, as shown in fig. 3, an implementation form of the high-frequency gain stage 32 is provided, which includes a fifth resistor R5, a first capacitor C1, a fifth NMOS transistor M5, a sixth NMOS transistor M6, a seventh NMOS transistor M7, an eighth NMOS transistor M8, a ninth NMOS transistor M9, a tenth NMOS transistor M10, a second constant current source, and a third constant current source, a gate of the fifth NMOS transistor M5 is used as a positive input end of the high-frequency gain stage, a source of the fifth NMOS transistor M5 is connected to one end of the first capacitor C1 and grounded through the second constant current source, and a drain of the fifth NMOS transistor M7 and the eighth NMOS transistor M8 are connected to a; the grid electrode of the sixth NMOS tube M6 is used as the negative input end of the high-frequency gain stage, the source electrode of the sixth NMOS tube M6 is connected with the other end of the first capacitor C1 and is grounded after passing through a third constant current source, and the drain electrode of the sixth NMOS tube M3578 is connected with the source electrodes of the ninth NMOS tube M9 and the tenth NMOS tube M10; the grid electrode of the seventh NMOS tube M7 is connected with the grid electrode of the ninth NMOS tube M9 and a negative output signal of the comparison circuit, and the drain electrode of the seventh NMOS tube M7 is used as a negative output end of the high-frequency gain stage; the gate of the eighth NMOS transistor M8 is connected to the gate of the tenth NMOS transistor M10 and the positive output signal of the comparator circuit, and the drain thereof is connected to the drain of the tenth NMOS transistor M10 and to the power supply voltage through the fifth resistor R5; the drain of the ninth NMOS transistor M9 is used as the positive output terminal of the high frequency gain stage.
The output of the low-frequency gain stage and the output of the high-frequency gain stage are jointly transmitted to a post-stage amplifier and a detection circuit, the detection circuit comprises at least one detection module, each detection module is used for amplifying the joint output of the low-frequency gain stage and the high-frequency gain stage again to obtain a third amplified signal and detecting the third amplified signal, peak detection is carried out on the low-frequency component of the third amplified signal after passing through a threshold value network, and peak detection is carried out on the high-frequency component of the third amplified signal. As shown in fig. 3, an implementation form of the detector module 33 is provided, which includes a first amplifier OP1, a second capacitor C2, a third capacitor C3, a fourth capacitor C4, a fifth capacitor C5, a sixth capacitor C6, a seventh capacitor C7, a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, a ninth resistor R9, a tenth resistor R10, an eleventh resistor R11, a twelfth resistor R12, a thirteenth resistor R13, an eleventh NMOS tube M11, a twelfth NMOS tube M12, a thirteenth NMOS tube M13, a fourteenth NMOS tube M14, and a fourth constant current source, wherein a positive input end of the first amplifier OP1 serves as a positive input end of the detector module, a negative input end of which serves as an input end of the detector module, a positive output end of which connects one end of the second capacitor C2 and one end of the fourth capacitor C4, and a negative output end of which connects a negative end of the third capacitor C3 and the fifth capacitor C5; the gate of the eleventh NMOS transistor M11 is connected to one end of the sixth resistor R6 and one end of the tenth resistor R10, and is grounded after passing through the sixth capacitor C6, the source thereof is connected to the sources of the twelfth NMOS transistor M12, the thirteenth NMOS transistor M13 and the fourteenth NMOS transistor M14, and is grounded after passing through the fourth constant current source, the drain thereof is connected to the drain of the twelfth NMOS transistor M12, and serves as the first output of the detector moduleA terminal; the other end of the sixth resistor R6 is connected with the other end of the second capacitor C2; the grid electrode of the twelfth NMOS tube M12 is connected with one end of the seventh resistor R7 and one end of the eleventh resistor R11 and is grounded after passing through the seventh capacitor C7; the other end of the seventh resistor R7 is connected with the other end of the third capacitor C3; the gate of the thirteenth NMOS transistor M13 is connected to one end of the thirteenth resistor R13, passes through the eighth resistor R8, and is connected to the other end of the fourth capacitor C4, and the drain thereof is connected to the drain of the fourteenth NMOS transistor M14 and serves as the second output terminal of the detector module; the gate of the fourteenth NMOS transistor M14 is connected to one end of the twelfth resistor R12, and to the other end of the fifth capacitor C5 through the ninth resistor R9; the other end of the tenth resistor R10, the other end of the eleventh resistor R11, the other end of the twelfth resistor R12 and the other end of the thirteenth resistor R13 are connected to a first reference voltage VREF1。
The bandwidth of the first amplifier OP1 in the low frequency gain stage and the detection module should be designed to be wide enough so as not to affect the spectral characteristics of the input signal and ensure the accuracy of peak detection.
The low-pass network of the sixth resistor R6, the sixth capacitor C6, the seventh resistor R7 and the seventh capacitor C7 in the detection module is a threshold network used for determining a set threshold, and the adjustment is to meet the requirement that the difference value between the amplitude of the high-frequency component and the amplitude of the low-frequency component in the detection module is equal to the set threshold; the specific set threshold may be determined by simulation. The sixth capacitor C6 and the seventh capacitor C7 in the threshold network of the detection module can be designed as a single capacitor or can be designed as a capacitor array. The capacitor array can also be added with a trimming function, the capacitor array with the trimming function can select different capacitor combinations through different trimming combinations after the chip is produced, so that the purpose of setting different thresholds is achieved, and in addition, the trimming function not only can set different thresholds, but also can be used for correcting comparison errors caused by circuit mismatch. Likewise, the first capacitor C1 to the fifth capacitor C5 may be designed as a single capacitor or a capacitor array.
At least one detection module is arranged in the detection circuit 33, as shown in fig. 2 and fig. 3, an implementation form that the detection circuit comprises one detection module is provided, in order to meet the sensitivity requirement of the whole link, a plurality of detection modules can also be arranged in the detection circuit, as shown in fig. 4, an implementation block diagram that 3 detection modules are arranged, the input end of each detection module is connected with the output of the low-frequency gain stage and the output of the high-frequency gain stage, after the direct current with high-frequency peak information and low-frequency peak information generated by each detection module is respectively applied, weighting is realized by a fourteenth resistor R14 and a fifteenth resistor R15 of the comparison circuit, and the weighting coefficients can be realized by setting different constant current sources of a fourth constant current source in each detection module. Due to the arrangement of a plurality of detection modules, the gain of the first amplifier OP1 in each detection module can be flexibly changed according to the sensitivity requirement of the whole link. When the sensitivity requirement is high and the input signal is small, the requirement of adjusting the bandwidth in place is met, the gain of the first amplifier OP1 of one of the detection modules can be set to be larger, normal detection under the condition of small input signal is realized, when the input signal is large, the detection module with the gain of the first amplifier OP1 set to be larger can be closed, and the other detection module with the gain of the first amplifier OP1 smaller is used, so that the adjustment effect cannot be influenced by the change of partial frequency spectrum due to amplitude limiting.
The comparison circuit is used for comparing output signals of two output ends of the detection circuit and controlling the gain of the high-frequency gain stage according to a comparison result, so that the gain of the high-frequency gain stage is increased or decreased, and the purpose of automatically adjusting the bandwidth is achieved. Fig. 3 shows an implementation form of the comparison circuit 34, which includes a second amplifier OP2, a third amplifier OP3, a fourteenth resistor R14, a fifteenth resistor R15, a sixteenth resistor R16 and a seventeenth resistor R17, wherein a positive input terminal of the second amplifier OP2 is connected to the second output terminal of the detector circuit and is connected to the power supply voltage through the fifteenth resistor R15, a negative input terminal of the second amplifier OP2 is connected to the first output terminal of the detector circuit and is connected to the power supply voltage through the fourteenth resistor R14, and an output terminal of the second amplifier OP2 is connected to the positive input terminal of the third amplifier OP 3; the negative input terminal of the third amplifier OP3 is connected to the second reference voltage VREF2A positive output terminal of the comparator outputs a positive output signal of the comparator and is connected to one end of a seventeenth resistor R17, a negative output terminal of the comparator outputs a negative output signal of the comparator, and is connected to a seventeenth resistor R17 after passing through a sixteenth resistor R16And the other end.
The working principle of the embodiment is as follows:
when there is no signal, the output of the second amplifier OP2 in the comparison circuit is less than the second reference voltage VREF2After the difference is amplified by the third amplifier OP3, the positive output terminal of the third amplifier outputs the positive output signal VOP of the comparison circuit to the gate terminals of the eighth NMOS transistor M8 and the tenth NMOS transistor M10 in the high-frequency gain stage, and the negative output terminal of the third amplifier outputs the negative output signal VON of the comparison circuit to the gate terminals of the seventh NMOS transistor M7 and the ninth NMOS transistor M9 in the high-frequency gain stage, thereby achieving the purpose of controlling the gain of the high-frequency gain stage. Second reference voltage V in comparison circuitREF2The setting of the voltage and the gain of the third amplifier OP3 need to ensure that the current of the branches of the seventh NMOS transistor M7 and the eighth NMOS transistor M8 in the high-frequency gain stage flows through the eighth NMOS transistor M8, and the current of the branches of the ninth NMOS transistor M9 and the tenth NMOS transistor M10 flows through the tenth NMOS transistor M10, at this time, the high-frequency gain stage is not connected to the link.
After the output signal of the front-stage amplifier is input to the positive input end and the negative input end of the low-frequency gain stage and the positive input end and the negative input end of the high-frequency gain stage, the low-frequency component in the output signal of the front-stage amplifier is amplified by the low-frequency gain stage to obtain a first amplified signal, the high-frequency component in the output signal of the front-stage amplifier is amplified by the high-frequency gain stage to obtain a second amplified signal, and then the first amplified signal and the second amplified signal are fed to a first amplifier OP1 in the detection module; the first amplifier OP1 performs sampling amplification to obtain a third amplified signal, the output of the first amplifier OP1 is divided into two paths, one path is output through alternating current coupling of the second capacitor C2 and the third capacitor C3, and the other path is output through alternating current coupling of the fourth capacitor C4 and the fifth capacitor C5. Signals output by alternating current coupling of the second capacitor C2 and the third capacitor C3 pass through a low-pass network of a sixth resistor R6, a sixth capacitor C6, a seventh resistor R7 and a seventh capacitor C7 and then are fed to gate ends of an eleventh NMOS transistor M11 and a twelfth NMOS transistor M12; signals output by alternating current coupling of the fourth capacitor C4 and the fifth capacitor C5 pass through the eighth resistor R8 and the ninth resistor R9 and then are fed into the thirteenth NMOS transistor M13 and the fourteenth NMOS transistor M14. The third amplified signal completes peak detection of low-frequency components in the third amplified signal after passing through a threshold network in an eleventh NMOS transistor M11 and a twelfth NMOS transistor M12, completes peak detection of high-frequency components in the third amplified signal in a thirteenth NMOS transistor M13 and a fourteenth NMOS transistor M14, converts peak information into a direct current signal, and flows through a fourteenth resistor R14 and a fifteenth resistor R15 in the comparison circuit respectively.
The direct current signal with the high-frequency peak information and the low-frequency peak information is converted into a voltage signal through a fourteenth resistor R14 and a fifteenth resistor R15 in the comparison circuit, and is amplified through a second amplifier OP2 in the comparison circuit, and the second amplifier OP2 can be designed as an integrating amplifier, so that the purpose of slowly adjusting the bandwidth is achieved; if the link bandwidth is insufficient at this time, the signal high frequency gain is insufficient, and the direct current flowing through the fourteenth resistor R14 is larger than the direct current flowing through the fifteenth resistor R15. The integrating amplifier, that is, the second amplifier OP2, continuously amplifies the voltage difference between the fourteenth resistor R14 and the fifteenth resistor R15, when the output of the second amplifier OP2 gradually increases, the positive output signal VOP of the comparison circuit output by the third amplifier OP3 gradually increases, the negative output signal VON gradually decreases, and the current flowing through the seventh NMOS transistor M7 and the ninth NMOS transistor M9 in the high-frequency gain stage gradually increases, so as to compensate the high-frequency gain of the link signal, with the continuous increase of the high-frequency gain of the link signal, until the dc current flowing through the fifteenth electronic transistor R14 is equal to the dc current flowing through the fifteenth resistor R15, the voltages of the positive output signal VOP of the comparison circuit and the negative output signal VON of the comparison circuit tend to be stable, the high-frequency gain stage no longer compensates the high-frequency gain of the link signal, and the bandwidth of the entire link reaches a stable state. If the spectral characteristics of the link change again, the adjustment is restarted. In this embodiment, when the link bandwidth is the largest, the currents of the branches of the seventh NMOS transistor M7 and the eighth NMOS transistor M8 in the high-frequency gain stage flow through the seventh NMOS transistor M7, the currents of the branches of the ninth NMOS transistor M9 and the tenth NMOS transistor M10 flow through the ninth NMOS transistor M9, and when the link bandwidth is the smallest, the currents of the branches of the seventh NMOS transistor M7 and the eighth NMOS transistor M8 flow through the eighth NMOS transistor M8, and the currents of the branches of the ninth NMOS transistor M9 and the tenth NMOS transistor M10 flow through the tenth NMOS transistor M10.
In summary, the present invention provides a self-adaptive bandwidth adjusting circuit, which includes a low-frequency gain stage and a high-frequency gain stage, wherein the low-frequency gain stage amplifies a low-frequency component of an input signal of the self-adaptive bandwidth adjusting circuit to obtain a first amplified signal, the high-frequency gain stage amplifies a high-frequency component of the input signal of the self-adaptive bandwidth adjusting circuit to obtain a second amplified signal, a gain of a high-frequency gain stage connected to a link is controlled by an output signal of a comparing circuit, and outputs of the low-frequency gain stage and the high-frequency gain stage are combined to be an output of the whole self-adaptive bandwidth adjusting circuit to a post-amplifier; the detection circuit superposes the first amplification signal and the second amplification signal and then amplifies the superposed signals to obtain a third amplification signal, detects the peak value of the high-frequency component in the third amplification signal in real time and the peak value of the low-frequency component in the third amplification signal after passing through a threshold network, and feeds the detection result to the comparison circuit for comparison, and then the comparison circuit controls the gain of the high-frequency gain stage in real time according to the comparison result. Compared with the traditional mode of adjusting the bandwidth by adjusting the transimpedance amplifier compensation network, the input variable of the invention is the frequency spectrum of the signal, so that the bandwidth cannot be overshot or not adjusted in place, and the bandwidth can be kept stable when a large signal or a small signal is input.
In this embodiment, the adaptive bandwidth adjusting circuit provided by the present invention is applied between the second stage and the third stage of the TIA chip for optical communication, but the adaptive bandwidth adjusting circuit of the present invention is also applicable to other chips with signal links. Those skilled in the art can make various other specific changes and combinations based on the teachings of the present invention without departing from the spirit of the invention, and these changes and combinations are within the scope of the invention.
Claims (7)
1. An adaptive bandwidth adjusting circuit is characterized by comprising a low-frequency gain stage, a high-frequency gain stage, a detection circuit and a comparison circuit,
the input end of the low-frequency gain stage is connected with the input signal of the self-adaptive bandwidth adjusting circuit, and the output end of the low-frequency gain stage outputs a first amplified signal obtained by amplifying the low-frequency component of the input signal of the self-adaptive bandwidth adjusting circuit;
the input end of the high-frequency gain stage is connected with the input signal of the self-adaptive bandwidth adjusting circuit, and the output end of the high-frequency gain stage outputs a second amplified signal obtained by amplifying the high-frequency component of the input signal of the self-adaptive bandwidth adjusting circuit;
the detection circuit comprises at least one detection module, the input end of the detection module is connected with the first amplification signal and the second amplification signal and is used for superposing and amplifying the first amplification signal and the second amplification signal to obtain a third amplification signal, the first output end of the detection module is connected with the first output end of the detection circuit and outputs a peak value obtained by subtracting a set threshold value from a low-frequency component in the third amplification signal, and the second output end of the detection module is connected with the second output end of the detection circuit and outputs a peak value of a high-frequency component in the third amplification signal;
the comparison circuit is used for comparing the output signals of the two output ends of the detection circuit and controlling the gain of the high-frequency gain stage according to the comparison result, when the output signal of the first output end of the detection circuit is detected to be larger than the output signal of the second output end of the detection circuit, the gain of the high-frequency gain stage is improved, and when the output signal of the first output end of the detection circuit is detected to be smaller than the output signal of the second output end of the detection circuit, the gain of the high-frequency gain stage is reduced until the output signals of the two output ends of the detection circuit are equal.
2. The adaptive bandwidth adjustment circuit of claim 1, wherein the comparison circuit comprises a second amplifier, a third amplifier, a fourteenth resistor, a fifteenth resistor, a sixteenth resistor, and a seventeenth resistor,
the positive input end of the second amplifier is connected with the second output end of the detection circuit and is connected with the power supply voltage after passing through the fifteenth resistor, the negative input end of the second amplifier is connected with the first output end of the detection circuit and is connected with the power supply voltage after passing through the fourteenth resistor, and the output end of the second amplifier is connected with the positive input end of the third amplifier;
the negative input end of the third amplifier is connected with the second reference voltage, the positive output end of the third amplifier outputs a positive output signal of the comparison circuit and is connected with one end of the seventeenth resistor, and the negative output end of the third amplifier outputs a negative output signal of the comparison circuit and is connected with the other end of the seventeenth resistor after passing through the sixteenth resistor.
3. The adaptive bandwidth adjusting circuit of claim 2, wherein the low frequency gain stage comprises a first resistor, a second resistor, a third resistor, a fourth resistor, a first constant current source, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, and a fourth NMOS transistor,
the grid electrode of the first NMOS tube is used as the positive input end of the low-frequency gain stage, the source electrode of the first NMOS tube is connected with one end of the first resistor, and the drain electrode of the first NMOS tube is connected with the source electrode of the third NMOS tube;
the grid electrode of the second NMOS tube is used as the negative input end of the low-frequency gain stage, the source electrode of the second NMOS tube is connected with one end of the second resistor, and the drain electrode of the second NMOS tube is connected with the source electrode of the fourth NMOS tube;
the other end of the first resistor is connected with the other end of the second resistor and is grounded after passing through the first constant current source;
the grid electrode of the third NMOS tube is connected with the grid electrode of the fourth NMOS tube and is connected with the connection point of the sixteenth resistor and the seventeenth resistor in the comparison circuit, and the drain electrode of the third NMOS tube is used as the negative output end of the low-frequency gain stage and is connected with power supply voltage after passing through the third resistor;
and the drain electrode of the fourth NMOS tube is used as the forward output end of the low-frequency gain stage and is connected with a power supply voltage after passing through a fourth resistor.
4. The adaptive bandwidth adjusting circuit of claim 2, wherein the high frequency gain stage comprises a fifth resistor, a first capacitor, a fifth NMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, an eighth NMOS transistor, a ninth NMOS transistor, a tenth NMOS transistor, a second constant current source, and a third constant current source,
the grid electrode of the fifth NMOS tube is used as the positive input end of the high-frequency gain stage, the source electrode of the fifth NMOS tube is connected with one end of the first capacitor and is grounded after passing through the second constant current source, and the drain electrode of the fifth NMOS tube is connected with the source electrodes of the seventh NMOS tube and the eighth NMOS tube;
a grid electrode of the sixth NMOS tube is used as a negative input end of the high-frequency gain stage, a source electrode of the sixth NMOS tube is connected with the other end of the first capacitor and is grounded after passing through a third constant current source, and a drain electrode of the sixth NMOS tube is connected with source electrodes of the ninth NMOS tube and the tenth NMOS tube;
the grid electrode of the seventh NMOS tube is connected with the grid electrode of the ninth NMOS tube and a negative output signal of the comparison circuit, and the drain electrode of the seventh NMOS tube is used as a negative output end of the high-frequency gain stage;
the grid electrode of the eighth NMOS tube is connected with the grid electrode of the tenth NMOS tube and a positive output signal of the comparison circuit, and the drain electrode of the eighth NMOS tube is connected with the drain electrode of the tenth NMOS tube and is connected with a power supply voltage after passing through a fifth resistor;
the drain electrode of the ninth NMOS tube is used as the positive output end of the high-frequency gain stage;
by setting the voltage value of the second reference voltage and the gain of the third amplifier OP3 in the comparison circuit, the current of the seventh NMOS transistor M7 and the current of the eighth NMOS transistor M8 branch in the high-frequency gain stage are both enabled to flow through the eighth NMOS transistor M8, and the current of the ninth NMOS transistor M9 and the current of the tenth NMOS transistor M10 branch in the high-frequency gain stage are both enabled to flow through the tenth NMOS transistor M10.
5. The adaptive bandwidth adjusting circuit according to any one of claims 1-4, wherein the detection module comprises a first amplifier, a second capacitor, a third capacitor, a fourth capacitor, a fifth capacitor, a sixth capacitor, a seventh capacitor, a sixth resistor, a seventh resistor, an eighth resistor, a ninth resistor, a tenth resistor, an eleventh resistor, a twelfth resistor, a thirteenth resistor, an eleventh NMOS transistor, a twelfth NMOS transistor, a thirteenth NMOS transistor, a fourteenth NMOS transistor, and a fourth constant current source,
a positive input end of the first amplifier is used as a positive input end of the detection module, a negative input end of the first amplifier is used as a negative input end of the detection module, a positive output end of the first amplifier is connected with one end of the second capacitor and one end of the fourth capacitor, and a negative output end of the first amplifier is connected with one end of the third capacitor and one end of the fifth capacitor;
the grid electrode of the eleventh NMOS tube is connected with one end of the sixth resistor and one end of the tenth resistor and is grounded through the sixth capacitor, the source electrode of the eleventh NMOS tube is connected with the source electrodes of the twelfth NMOS tube, the thirteenth NMOS tube and the fourteenth NMOS tube and is grounded through the fourth constant current source, and the drain electrode of the eleventh NMOS tube is connected with the drain electrode of the twelfth NMOS tube and serves as the first output end of the detection module;
the other end of the sixth resistor is connected with the other end of the second capacitor;
the grid electrode of the twelfth NMOS tube is connected with one end of the seventh resistor and one end of the eleventh resistor and is grounded through the seventh capacitor;
the other end of the seventh resistor is connected with the other end of the third capacitor;
the grid electrode of the thirteenth NMOS tube is connected with one end of the thirteenth resistor and is connected with the other end of the fourth capacitor after passing through the eighth resistor, and the drain electrode of the thirteenth NMOS tube is connected with the drain electrode of the fourteenth NMOS tube and serves as a second output end of the detection module;
a grid electrode of the fourteenth NMOS tube is connected with one end of the twelfth resistor and is connected with the other end of the fifth capacitor after passing through the ninth resistor;
the other end of the tenth resistor, the other end of the eleventh resistor, the other end of the twelfth resistor and the other end of the thirteenth resistor are connected to a first reference voltage.
6. The adaptive bandwidth adjustment circuit of claim 5, wherein the sixth capacitor and the seventh capacitor of the detection module are a single capacitor or a capacitor array.
7. The adaptive bandwidth adjustment circuit of claim 6, wherein when the sixth capacitor and the seventh capacitor in the detection module are capacitor arrays, the capacitor arrays have a trimming function.
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