CN1106762C

CN1106762C - Method and circuit for detecting data segment synchronizing signal in bigh-definition television

Info

Publication number: CN1106762C
Application number: CN97112983A
Authority: CN
Inventors: 申贤秀; 韩东锡
Original assignee: Samsung Electronics Co Ltd
Current assignee: Samsung Electronics Co Ltd
Priority date: 1996-06-17
Filing date: 1997-06-13
Publication date: 2003-04-23
Anticipated expiration: 2017-06-13
Also published as: US6014416A; CN1170313A; CN1390049A; CN1169322C

Abstract

A data segment synchronizing signal detecting circuit for reducing bit resolution of an HDTV without affecting its function. The apparatus includes a hard limiter added between a four-symbol correlator and an adder, to obtain a 2-bit output of three-level values for a four-bit input. The circuit may also include a first symbol delay for delaying an output of a symbol correlator by a factor N corresponding to a number of symbols of one segment, a first adder for adding the value delayed by the first symbol delay and the output of the symbol correlator, and accumulating the added result, a first maximum value location detector for detecting a first location of a first maximum value of the added result accumulated in the first adder, a second symbol delay for delaying the output of the symbol correlator by (one segment symbol)/N, according to the first maximum value detected by the first maximum value location detector, a second adder for adding the value delayed by the second symbol delay and the output of the symbol correlator, and accumulating the added result, a second maximum value location detector for detecting a second location of a second maximum value of the added result accumulated in the second adder, and a synchronizing signal generator for generating a segment synchronizing signal, according to an output of the second maximum value location detector.

Description

The data segment sync signal testing circuit

The present invention relates to detect in the high definition TV (HDTV) circuit of data segment sync signal, relate to the Method and circuits that detects data segment sync signal in high definition TV particularly, it makes that required door (gate) is counted minimum when realizing HDTV in ASTC.

Usually, in the HDTV system, before TV station (TV broadcasting station) transmits with horizontal behavior unit, added synchronizing signal, receive the receiver that is transmitted and from this signal, detect this synchronizing signal, the water parallel signal comes this signal synchronously, handles synchronous signal then.The form of horizontal line transmission data depends on the HDTV system.Fig. 1 and 2 has shown the structure of the data segment of the HDTV of U.S. Major Leagues (GA).A Frame is made of 626 row sections (line segments), and one section comprises 832 characters, and it is made up of 828 character datas and four character data segment sync signals, shown in Fig. 2 A.A data segment is corresponding to a TSC-system horizontal line.Data segment sync signal is made up of four characters that each data segment of indication begins.Data segment sync signal constitutes specific pattern in such a manner, promptly four characters have+5 ,-5 ,-5 ,+5 signal level, and other data segment signal has the random signal level.

Therefore, in the circuit that receives GA system transmissions signal, during beginning four characters of each data segment, detect data segment sync signal, to solve the stationary problem of the data segment signal that regularly recovers and received.Therefore, the detection of data segment sync signal affects the performance of GA-VSB system.At Korean Patent Application No. 1995-15218,30746 and 96-21886 in the apparatus and method that produce data segment sync signal from the data that receive are disclosed.

Explain another conventional method that produces data segment sync signal below in conjunction with Fig. 3.Separator 303 is isolated MSB from 8 bits of filter (not shown) output, so that it is used as reference signal.Four character correlators (correlator) 305 receive this MSB to produce the relevant character in position between the data.Because four character correlators only use MSB, as mentioned above, are (+) at character only, (-), output 4 then exports-4 in other situation ,-2,0 and 2 when (-) or (+).In adder 307, the output addition of the output of four character correlators 305 and one section delayer 309 promptly with first leading portion in the output addition of same position, the result of addition is by accumulative total.

The output of adder 307 is sent to maximum value detector 311.Maximum value detector 311 is observed the output of 823 characters (a section) of the relevant character that adds up, and judges the position that maximum occurs, as the section sync bit.Then this information is added to synchronous generator 313.Synchronous generator 313 produces lock-out pulse at the section sync bit.

As shown in Figure 3, in the conventional equipment that produces segment sync signal,, just need adder and 823 character delayers to accumulate this four bits output because four character correlators 305 are output as four bits.Therefore, the bit resolution of this device is 8 bits at least.When in ASIC, realizing this device, just need 832 characters to postpone, so this device just need 8 bits * 832 * 7 door.Therefore conventional device is that to finish the door that its function needs too many.

The purpose of this invention is to provide the bit resolution of a kind of HDTV of minimizing and do not influence the Method and circuits of its function, it uses a hard limiter in output place of correlator, therefore reduces needed number of this device.

Another object of the present invention provides a Method and circuits that detects data segment sync signal, and during from the position relevant character, it utilizes a plurality of delays, reduces the door number that is used to detect data segment sync signal at maximum value position.

For realizing purpose of the present invention, a hard limiter (hard limiter) is added to the output of four character correlators, to produce data segment sync signal, therefore reduces the door number.In addition, the length of delay that is postponed N character by four character correlations is by character delayer accumulative total, and this delayer has 2,4, and 8,13,16,26,32, one of 832 coefficients of 52,64,104,208 and 416, the value that postpones from the peaked position of aggregate-value, by four character correlations is according to the value that detects, by having 416,208,104,64,52,32,26, (832/N) character delayer accumulation one of in 16,13,8,4 and 2.Then, detect peaked position, to produce segment sync signal from the value that adds up.

Below in conjunction with accompanying drawing most preferred embodiment of the present invention is described.

Fig. 1 has shown the data format of the GA-VSB HDTV system of the U.S.;

Fig. 2 has shown the form of data segment sync signal;

Fig. 3 is the block diagram of data segment sync signal testing circuit in the conventional H DTV system;

Fig. 4 is the block diagram according to the data segment sync signal testing circuit of the GA-VSB HDTV system of embodiments of the invention;

Fig. 5 is the circuit diagram of the hard limiter of Fig. 4; With

Fig. 6 is the block diagram according to the data segment sync signal testing circuit of the GA-VSB HDTV system of another embodiment of the present invention;

Fig. 4 is the block diagram according to the data segment sync signal testing circuit of the GA-VSB HDTV system of embodiments of the invention.As shown in Figure 4, data segment sync signal testing circuit of the present invention in such a manner/constitute, promptly between four character correlators 305 and adder 307, add hard limiter 400, so that input obtains the 2 bits output of three level values to 4bit.

Fig. 5 has shown the circuit of the hard limiter 400 of Fig. 4 in detail.Hard limiter is made of following: the separator 501 that is used for separating from four bits of four character correlators, 305 outputs MSB; Be used for relatively and judge whether they equate first comparator 505 of (A=B) MSB and level " 0 "; Be used for relatively and judge that this four bits output is whether greater than level " 3 " (second comparator 507 of A 〉=B) the output of four bits of four character correlators 305 and level " 3 "; The synthesizer 503 that is used for the output of synthetic first and

second comparators

505 and 507; Select level-1 (00) with being used for according to the output of synthesizer 503, one multiplexer 509 in 0 (10) and 1 (11).

Below in conjunction with Fig. 4, Fig. 5 and Fig. 6 explain most preferred embodiment of the present invention.Separator 303 is isolated MSB from eight bits of filter (not shown) output.This MSB proofreaies and correct in four character correlators 305.This correlation technique is identical with routine, therefore omits its explanation.Four bits of proofreading and correct in four character correlators 305 are added to hard limiter 400, and are as shown in table 1 below.Hard limiter 400 receives this four bit from four character correlators 305, and utilizes the separator 501 that is included among Fig. 5 to separate its MSB.

Table 1

Input	Output
Input	Output	-4，-2	-1
0，2	0	-4，-2	-1
0，2	0	4	1

This MSB is added to first comparator 505, and the output of four character correlators 305 is added to second comparator 507.First comparator compares MSB and level " 0 ".Here, as MSB during less than level " 0 ", being input as of first comparator 505 " 1 ", it is output as " 0 ".Second comparator 507 compares the four bits output of four character correlators 305 with level " 3 ".When importing less than level " 0 ", second comparator 507 is output as " 0 ".Therefore, the output of synthesizer 503 becomes 00, and multiplexer 509 is selected output " 1 ".When the input from four bit character correlators 305 had " 0 " value between " 3 ", the one the

second comparators

505 and 507 output were respectively " 1 " and " 0 ", corresponding to input " 10 ", and multiplexer 509 outputs " 0 ".When input value during greater than " 3 ", the input of multiplexer 509 becomes " 11 ", and therefore, it selectively exports " 1 ".

Fig. 6 is the block diagram according to the data segment sync signal testing circuit of the GA-VSB HDTV system of another embodiment of the present invention.Be connected to the output of four character correlators 305 with reference to figure 6, the first and second adders 607 and 605.First adder 607 will be that the first character delayer is all character value additions of cell delay with the section from the correlation of four bit character correlators, 305 outputs and by N character delayer 601, and add up them.The output of first adder 607 is added to first maximum value detector 603.First maximum value detector 603 detects the peaked position by the character value of first adder 607 accumulative totals.The output of first maximum value detector 603 is added to the i.e. second character delayer of (832/N) character delayer 617.

Second adder 605 is with the correlation of four bit character correlators 305 and (832/N) the output valve addition of character delayer 617, and be used to detect control signal from the maximum value position of first maximum value detector 603, only accumulative total is corresponding to the value of the peaked position that detects correlation.Promptly first maximum value detector 603 detects peaked position in the section that each length produces.Provide corresponding to the detected value of maximum value position control signal as (832/N) character delayer 617.When the start-up control signal, (832/N) character delayer 617 is selected these values during this start-up period.The value of these selections is accumulative total in second adder 605, is added to second maximum value detector 609 then.When second maximum value detector 609 is selected maximum and it is added to synchronous generator 313 from the value of second adder 605 accumulative total, produce synchronizing signal at the maximum value position place.

For N character delayer 601 and (832/N) first and second characters of character delayer 617 postpone, N can be in 13,16,32 and 64, it is 832 factor.For example, when N character delayer 601 was the delay of 13 characters, (832/N) character delayer 617 was that 64 characters postpone.Therefore, under the situation of N=64,13 (=832/N) individual character position correlation 1,65,129,193,257...769 is first register that is imported into 64 shift registers after 832 characters.Similarly, has accumulative total in each that 13 character correlations of 64 character pitches can be in all the other 63 registers.

For foregoing circuit of the present invention, be designated as a factor (2,4 of 832 when the N value, 8,13,16,26,32,52,64,104,208,416) time, the quantity of required register (K) can be expressed from the next: K=N+ (832/N) does not need 832 registers to handle 832 characters and do not resemble custom circuit.Promptly working as N is 2, K=2+ (832/2)=418, and when N is 416, K=416+ (832/416).Therefore, the quantity of register can reduce to 50%, has also just reduced door number required in the ASIC circuit.

As mentioned above, in data segment sync signal testing circuit of the present invention, utilize hard limiter, input can obtain dibit output for four bits, and it is added to by adder and one section integrating instrument that delayer is formed.Learn from result of experiment, when SNR=0dB, can affirm, when the cumulative correction result at the section sync bit is higher than 8, can produce correct segment sync signal.That is, for accumulated result, roughly 6 bits are enough to.Therefore, required door number becomes about 6 bits * 832 * 7 bits=34,944 in the ASIC circuit.That is, from the required door number of custom circuit, approximately can reduce by 12,000 doors.

In addition, the bit resolution of this device also is reduced, and has simplified the complexity of other operation.Data segment sync signal testing circuit of the present invention is divided the also delay of processing section.Promptly at first add up all sections, in a section character, detect the peaked position of each character, once more by totally, detect peaked position, produce synchronizing signal thus from the secondary aggregate-value corresponding to the character value of this position.Therefore, the position relevant character for a section does not need accumulative total and handles whole character value.When in ASIC, realizing, can reduce the door number that detects the data segment sync signal circuit significantly.

Therefore, should be appreciated that the present invention is not restricted to as in the specific embodiment of implementing best mode of the present invention, also be not restricted in the specifying of this specification that scope of the present invention is limited by claim of the present invention.

Claims

1. data segment sync signal testing circuit comprises: a hard limiter is added between four bit character correlators and the adder, and so that input obtains 2 bit output valves of three level to four bits,

Wherein, this hard limiter comprises:

Separator is used for separating MSB from the four bits output of four bit character correlators output;

First comparator is used for this MSB and level " 0 " relatively and judge whether they equate;

Second comparator, be used for the output of four bit character of four bit character correlators and level " 3 " relatively and the output of judging this four bit character correlator whether greater than level " 3 ";

Synthesizer, be used for synthetic first and second comparators and output; With

Multiplexer is used for selecting level-1 (00) according to the output of synthesizer, in 0 (10) and 1 (11) one.