CN110672923A - Detection system for silicon waveguide admittance - Google Patents
Detection system for silicon waveguide admittance Download PDFInfo
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Abstract
The invention discloses a detection system of silicon waveguide admittance, which comprises an alternating current power supply, a sensor and a silicon waveguide admittance detection circuit, wherein the sensor comprises an excitation electrode, an induction electrode, a substrate, a silicon layer and a covering layer, and the substrate and the covering layer are made of SiO (silicon dioxide)2The sensor comprises a substrate, a silicon layer, a covering layer, an excitation electrode, an induction electrode, a grounding electrode, a detection circuit and a power supply, wherein the substrate, the silicon layer and the covering layer are laminated in sequence from bottom to top, the excitation electrode and the induction electrode are arranged on the covering layer at intervals, the excitation electrode is connected with the positive electrode of an alternating current power supply, the induction electrode is connected with the input end of the silicon waveguide admittance detection circuit, the sensor further comprises the grounding electrode, the grounding electrode is arranged on the covering layer and positioned between the excitation electrode and the induction electrode, the grounding electrode, the excitation electrode and the induction electrode are completely the same in size; the advantage is that detection accuracy is higher.
Description
Technical Field
The invention relates to a detection system, in particular to a detection system for silicon waveguide admittance.
Background
The optical integrated chip is favored in the fields of optical interconnection, optical communication and the like more and more by virtue of the advantages of small volume, low energy consumption, large bandwidth and the like. The internal optical power of the silicon waveguide is one of important technical indexes for detecting the stability of the optical integrated chip, and how to detect the internal optical power of the silicon waveguide is a design difficulty of the current optical integrated chip. The change of the silicon waveguide admittance reflects the change of the internal optical power of the silicon waveguide, and the detection of the internal optical power of the silicon waveguide is mainly realized at present through the detection of the silicon waveguide admittance.
The existing detection system for silicon waveguide admittance generally comprises an alternating current power supply V1, a sensor and a silicon waveguide admittance detection circuit, wherein the sensor adopts C4And D (capacitive coupled capacitive detection) scheme, wherein the silicon waveguide admittance detection circuit is realized based on a non-contact photon probe detection technology. As shown in FIG. 1, the sensor comprises an excitation electrode, a sensing electrode, a substrate, a silicon layer and a covering layer, wherein the substrate and the covering layer are made of SiO2The substrate, the silicon layer and the covering layer are stacked in sequence from bottom to top, the excitation electrode and the induction electrode are arranged on the covering layer at intervals, the excitation electrode is connected with an alternating current power supply, and the induction electrode is connected with the silicon waveguide admittance detection circuit. The equivalent circuit of the sensor is shown in fig. 2, a capacitor C1 is a stray capacitance between the excitation electrode and the sensing electrode, a capacitor C2 is a contact capacitance between the excitation electrode and the silicon layer, a capacitor C3 is a contact capacitance between the sensing electrode and the silicon layer, and G3 is a silicon layer equivalent admittance. Due to the presence of the capacitor C1, the output current I1 of the sensor consists of the current of a two-part branch: the current flowing through branch 1 formed by capacitor C1 and the current flowing through branch 2 formed by capacitor C2, silicon layer equivalent admittance G1 and capacitor C3. However, the current flowing through branch 1 is about three orders of magnitude higher than the current flowing through branch 2, and the phase of the current flowing through branch 1 leads 90 ° with respect to the phase of the current flowing through branch 2, thereby limiting the amplification of the current flowing out of the sensing electrode, which greatly reduces the sensitivity of the sensor. The silicon waveguide admittance detection circuit realized based on the non-contact photon probe detection technology is realized by adopting a traditional phase-locked amplification structure. The silicon waveguide admittance detection circuitIn the method, a current signal representing the conductance change information of the silicon waveguide is amplified and converted into a voltage signal through a trans-impedance amplifier, the voltage signal is multiplied by an external modulation signal to complete frequency spectrum migration, and finally, noise is filtered through a low-pass filter to obtain the amplified voltage signal representing the conductance change information. However, the existing silicon waveguide admittance detection circuit has a large influence of low-frequency flicker noise, and the accuracy of the obtained voltage signal representing conductance change information is not high, so that the silicon waveguide admittance resolution is not high. Therefore, the existing detection system of the silicon waveguide admittance is influenced by the sensitivity of the sensor and the resolution of the silicon waveguide admittance detection circuit, and finally the detection precision of the silicon waveguide admittance is not high.
Disclosure of Invention
The invention aims to provide a detection system for silicon waveguide admittance with high detection precision.
The technical scheme adopted by the invention for solving the technical problems is as follows: a detection system of silicon waveguide admittance comprises an alternating current power supply, a sensor and a silicon waveguide admittance detection circuit, wherein the sensor comprises an excitation electrode, an induction electrode, a substrate, a silicon layer and a covering layer, and the substrate and the covering layer are made of SiO2The substrate, the silicon layer and the covering layer are sequentially laminated from bottom to top, the excitation electrode and the induction electrode are arranged on the covering layer at intervals, the excitation electrode is connected with the positive electrode of the alternating current power supply, and the induction electrode is connected with the input end of the silicon waveguide admittance detection circuit. The sensor also comprises a grounding electrode, wherein the grounding electrode is arranged on the covering layer and is positioned between the excitation electrode and the induction electrode, the grounding electrode, the excitation electrode and the induction electrode have the same size, the distance between the grounding electrode and the excitation electrode is equal to the distance between the grounding electrode and the induction electrode, and the grounding electrode is grounded.
The distance between the excitation electrode and the grounding electrode is 100 micrometers, the distance between the induction electrode and the grounding electrode is 100 micrometers, the cross sections of the excitation electrode, the induction electrode and the grounding electrode are all square, and the side length of the square is 100 micrometers.
The silicon waveguide admittance detection circuit comprises a pre-integration circuit, a post-amplifier and a low-pass filter; the pre-integration circuit comprises a first operational amplifier, a first capacitor, a second capacitor and two electronic switches with the same structure, wherein the first operational amplifier is provided with a positive input end, a negative input end, an output end, a power supply end and a grounding end, the electronic switches are provided with a positive control end, a negative control end, an input end and an output end and are respectively called a first electronic switch and a second electronic switch, the input end of the first electronic switch is the input end of the pre-integration circuit, the positive control end of the first electronic switch is connected with the negative control end of the second electronic switch, the connecting end of the positive control end of the first electronic switch is the positive control end of the pre-integration circuit, the negative control end of the first electronic switch is connected with the positive control end of the second electronic switch, and the connecting end of the negative control end of the pre-integration circuit is the negative control end of the pre-integration circuit, the output end of the first electronic switch, the input end of the second electronic switch, and one end of the first capacitor are connected to the negative input end of the first operational amplifier, the positive input end of the first operational amplifier and the ground end of the first operational amplifier are all grounded, the other end of the first capacitor, the output end of the first operational amplifier and one end of the second capacitor are connected, the connection end of the first capacitor and the output end of the first operational amplifier is the output end of the pre-integrator, the other end of the second capacitor is grounded, and the power supply end of the first operational amplifier is connected to an external power supply; the post amplifier comprises a second operational amplifier, a first resistor, a second resistor and a third capacitor, the second operational amplifier has a positive input terminal, a negative input terminal, an output terminal, a power terminal and a ground terminal, the positive input end of the second operational amplifier and the grounding end of the second operational amplifier are both grounded, the power supply end of the second operational amplifier is connected with an external power supply, one end of the first resistor is the input end of the post amplifier, the other end of the first resistor and one end of the second resistor are connected with the negative input end of the second operational amplifier, the other end of the second resistor, the output end of the second operational amplifier and one end of the third capacitor are connected, the connection end of the second resistor and the output end of the second operational amplifier is the output end of the post-amplifier, and the other end of the third capacitor is grounded; the low-pass filter comprises a third resistor and a fourth capacitor, one end of the third resistor is an input end of the low-pass filter, the other end of the third resistor is connected with one end of the fourth capacitor, the connection end of the third resistor is an output end of the low-pass filter, and the other end of the fourth capacitor is grounded; the positive control end of the pre-integration circuit is the positive control end of the silicon waveguide admittance detecting circuit and is connected with a positive control signal, the negative control end of the pre-integration circuit is the negative control end of the silicon waveguide admittance detecting circuit and is connected with a negative control signal, the negative control signal is the inverted signal of a positive control signal, the positive control signal and the negative control signal are used for controlling the on and off of the first electronic switch and the second electronic switch, the input end of the pre-integration circuit is used as the input end of the silicon waveguide admittance detecting circuit, the output end of the pre-integrator circuit is connected with the input end of the post-amplifier, the output end of the post-amplifier is connected with the input end of the low-pass filter, the output end of the low-pass filter is used as the output end of the silicon waveguide admittance detecting circuit. The silicon waveguide admittance detection circuit utilizes the characteristics of periodicity and continuity of a current signal input into the silicon waveguide admittance detection circuit by a sensor, firstly, the current signal is integrated and amplified into a voltage signal by a pre-integration circuit, then, the voltage signal output by the pre-integration circuit is further amplified by a post-amplifier and then output, and finally, a direct current part in the voltage signal output by the post-amplifier is extracted by a low-pass filter, because noise is random and irregular, when the noise is input into the pre-integration circuit along with the current signal, the pre-integration circuit does not act on the noise, only the current signal is integrated and accumulated in a first capacitor and amplified into a voltage signal under the synergistic action of a first electronic switch and a second electronic switch in the pre-integration circuit, and the noise signal is not accumulated or amplified in the process, therefore, the whole circuit can play a great role in inhibiting the noise, the obtained voltage signal representing the conductance change information has high precision, the silicon waveguide admittance has high resolution, and finally the detection precision of the silicon waveguide admittance is high.
The first operational amplifier comprises a first MOS tube, a second MOS tube, a third MOS tube, a fourth MOS tube, a fifth MOS tube, a sixth MOS tube, a seventh MOS tube, an eighth MOS tube, a ninth MOS tube, a tenth MOS tube, an eleventh MOS tube, a twelfth MOS tube, a thirteenth MOS tube, a fourteenth MOS tube, a fifteenth MOS tube, a sixteenth MOS tube, a fourth resistor, a fifth capacitor, a sixth capacitor and a direct current power supply, the first MOS transistor, the second MOS transistor, the fifth MOS transistor, the sixth MOS transistor, the ninth MOS transistor, the tenth MOS transistor, the eleventh MOS transistor, the fourteenth MOS transistor and the sixteenth MOS transistor are all P-type MOS transistors, the third MOS transistor, the fourth MOS transistor, the seventh MOS transistor, the eighth MOS transistor, the twelfth MOS transistor, the thirteenth MOS transistor and the fifteenth MOS transistor are all N-type MOS transistors; the source of the first MOS transistor, the source of the second MOS transistor, the source of the ninth MOS transistor, the source of the fourteenth MOS transistor and the source of the sixteenth MOS transistor are connected, and the connection end is the power supply end of the first operational amplifier, the drain of the first MOS transistor, the gate of the first MOS transistor, the drain of the second MOS transistor, the gate of the second MOS transistor, the drain of the third MOS transistor, the gate of the third MOS transistor, the drain of the fourth MOS transistor, the gate of the ninth MOS transistor, the gate of the fourteenth MOS transistor and the gate of the sixteenth MOS transistor are connected, the source of the third MOS transistor and one end of the fourth resistor are connected, the other end of the fourth resistor, the source of the fourth MOS transistor, the source of the seventh MOS transistor, the gate of the sixth MOS transistor and the gate of the sixteenth MOS transistor are connected, and the other end of the fourth resistor is connected with the source of the fourth resistor, A source of the eighth MOS transistor, a source of the twelfth MOS transistor, a source of the thirteenth MOS transistor, a source of the fifteenth MOS transistor, and a negative electrode of the dc power supply are connected, and a connection end thereof is a ground end of the first operational amplifier, a gate of the fifth MOS transistor is a positive input end of the first operational amplifier, a source of the fifth MOS transistor, a source of the sixth MOS transistor, and a drain of the ninth MOS transistor are connected, a drain of the fifth MOS transistor, a drain of the seventh MOS transistor, a gate of the seventh MOS transistor, and a gate of the eighth MOS transistor are connected, a gate of the sixth MOS transistor is a negative input end of the first operational amplifier, a drain of the sixth MOS transistor, a drain of the eighth MOS transistor, a gate of the tenth MOS transistor, and one end of the fifth capacitor are connected, the source of the tenth MOS transistor, the source of the eleventh MOS transistor and the drain of the fourteenth MOS transistor are connected, the drain of the tenth MOS transistor, the drain of the twelfth MOS transistor, the gate of the twelfth MOS transistor and the gate of the thirteenth MOS transistor are connected, the drain of the eleventh MOS transistor, the drain of the thirteenth MOS transistor, the gate of the fifteenth MOS transistor and one end of the sixth capacitor are connected, the gate of the eleventh MOS transistor and the positive electrode of the dc power supply are connected, the drain of the fifteenth MOS transistor, the drain of the sixteenth MOS transistor, the other end of the fifth capacitor and the other end of the sixth capacitor are connected, the connection end of the fifteenth MOS transistor is the output end of the first operational amplifier, and the conductance value of the fifteenth MOS transistor is respectively greater than the conductance value of the fifth MOS transistor, and the gate of the fourteenth MOS transistor is connected, the drain of the eleventh MOS transistor and the gate of the fifteenth MOS are connected, the drain of the fifteenth MOS transistor and the other end of the sixth capacitor are connected, and the connection end of, The conductance value of the sixth MOS tube, the conductance value of the tenth MOS tube and the conductance value of the eleventh MOS tube. The first operational amplifier adopts a three-level cascade differential input structure, a fifth MOS tube, a sixth MOS tube, a seventh MOS tube, an eighth MOS tube and a ninth MOS tube form a first level, a tenth MOS tube, an eleventh MOS tube, a twelfth MOS tube, a thirteenth MOS tube and a fourteenth MOS tube form a second level, the fifteenth MOS tube and the sixteenth MOS tube form a third level, wherein the first level and the second level both adopt a five-tube differential amplification structure cascade, the output level of the first operational amplifier adopts a push-pull structure, in order to ensure the integral stability of the first operational amplifier, the phase Compensation is carried out by adopting a Nested Miller Compensation (NMC) mode, the fifth capacitor and the sixth capacitor are Compensation capacitors, the fifth capacitor is connected between the output end of the first level and the output end of the third level, the sixth capacitor is connected between the output end of the second level and the output end of the third level, a first level output end pole and a third level output end are introduced The poles of the first operational amplifier are split to improve the stability of the first operational amplifier, thereby ensuring that the first operational amplifier has higher stability.
The electronic switch comprises a seventeenth MOS tube and an eighteenth MOS tube, wherein the seventeenth MOS tube is a P-type MOS tube. The eighteenth MOS tube is an N-type MOS tube; the source electrode of the seventeenth MOS tube is connected with the source electrode of the eighteenth MOS tube, the connecting end of the seventeenth MOS tube is the input end of the electronic switch, the drain electrode of the seventeenth MOS tube is connected with the drain electrode of the eighteenth MOS tube, the connecting end of the seventeenth MOS tube is the output end of the electronic switch, the grid electrode of the seventeenth MOS tube is the negative control end of the electronic switch, and the grid electrode of the eighteenth MOS tube is the positive control end of the electronic switch.
The second operational amplifier comprises a nineteenth MOS tube, a twentieth MOS tube, a twenty-first MOS tube, a twenty-twelfth MOS tube, a twenty-thirteenth MOS tube, a twenty-fourteenth MOS tube, a twenty-fifth MOS tube, a twenty-sixth MOS tube, a twenty-seventh MOS tube, a twenty-eighteen MOS tube, a twenty-ninth MOS tube, a thirty-eleventh MOS tube, a thirty-twelfth MOS tube, a fifth resistor and a seventh capacitor, the nineteenth MOS tube, the twentieth MOS tube, the twenty-fifth MOS tube, the twenty-sixth MOS tube, the twenty-seventh MOS tube and the thirty-fifth MOS tube are all P-type MOS tubes, the twenty-first MOS tube, the twenty-second MOS tube, the twenty-third MOS tube, the twenty-fourth MOS tube, the twenty-eighth MOS tube, the twenty-ninth MOS tube, the thirty-first MOS tube and the third-twelfth MOS tube are all N-type MOS tubes; the source electrode of the nineteenth MOS tube, the source electrode of the twentieth MOS tube, the source electrode of the twenty-fifth MOS tube and the source electrode of the thirtieth MOS tube are connected, and the connection end of the source electrode of the twenty-fifth MOS tube and the source electrode of the thirtieth MOS tube is the power supply end of the second operational amplifier; the gate of the nineteenth MOS transistor, the drain of the nineteenth MOS transistor, the gate of the twentieth MOS transistor, the drain of the twenty-first MOS transistor, the gate of the twenty-fifth MOS transistor and the gate of the thirty-first MOS transistor are connected, the drain of the twentieth MOS transistor, the gate of the twenty-first MOS transistor, the gate of the twenty-twelfth MOS transistor, the drain of the twenty-twelfth MOS transistor and the gate of the thirty-eleventh MOS transistor are connected, the source of the twenty-first MOS transistor and the drain of the twenty-thirteenth MOS transistor are connected, the source of the twenty-twelfth MOS transistor, the gate of the twenty-thirteenth MOS transistor, the gate of the twenty-fourteenth MOS transistor and the drain of the twenty-fourteenth MOS transistor are connected, the source of the twenty-thirteenth MOS transistor and one end of the fifth resistor are connected, the other end of the fifth resistor is connected, The source of the twenty-fourth MOS transistor, the source of the twenty-eighth MOS transistor, the source of the twenty-ninth MOS transistor and the source of the third twelfth MOS transistor are connected, and the connection end is the ground end of the second operational amplifier, the drain of the twenty-fifth MOS transistor, the source of the twenty-sixth MOS transistor and the source of the twenty-seventh MOS transistor are connected, the gate of the twenty-sixth MOS transistor is the positive input end of the second operational amplifier, the drain of the twenty-sixth MOS transistor, the drain of the twenty-eighteen MOS transistor, the gate of the twenty-eighteen MOS transistor and the gate of the twenty-ninth MOS transistor are connected, the gate of the twenty-seventh MOS transistor is the negative input end of the second operational amplifier, the drain of the twenty-seventh MOS transistor, the drain of the twenty-ninth MOS transistor, the drain of the thirty-ninth MOS transistor and the gate of the twelfth MOS transistor are connected, the drain electrode of the thirty-third MOS transistor, one end of the seventh capacitor and the drain electrode of the thirty-second MOS transistor are connected, the connection end of the seventh capacitor is the output end of the second operational amplifier, and the other end of the seventh capacitor is connected with the source electrode of the thirty-first MOS transistor. This second operational amplifier has adopted the two-stage difference to amplify the structure, and the seventh electric capacity guarantees the stability of the whole work of second operational amplifier for Miller compensation capacitance, controls the on-resistance of thirty one MOS pipe through the grid voltage of twenty ninth MOS pipe and realizes the function of zero setting resistance, guarantees from this that second operational amplifier has higher stability.
Compared with the prior art, the invention has the advantages that the grounding electrode positioned between the excitation electrode and the induction electrode is arranged on the covering layer, the grounding electrode, the excitation electrode and the induction electrode are completely the same in size, the distance between the grounding electrode and the excitation electrode is equal to the distance between the grounding electrode and the induction electrode, and the grounding electrode is grounded, so that the stray capacitance between the excitation electrode and the induction electrode is shielded through the grounding electrode, and the stray capacitance between the excitation electrode and the grounding electrode and the stray capacitance between the induction electrode and the grounding electrode are generated.
Drawings
FIG. 1 is a block diagram of a sensor of a conventional silicon waveguide admittance detecting system;
FIG. 2 is an equivalent circuit diagram of a sensor of a prior art silicon waveguide admittance sensing system;
FIG. 3 is a block diagram of a sensor of the detection system of silicon waveguide admittance of the present invention;
FIG. 4 is a circuit diagram of a silicon waveguide admittance detecting circuit of the silicon waveguide admittance detecting system of the present invention.
FIG. 5 is a circuit diagram of a first operational amplifier of a silicon waveguide admittance detecting circuit of the silicon waveguide admittance detecting system of the present invention;
FIG. 6 is a circuit diagram of an electronic switch of a silicon waveguide admittance detecting circuit of the silicon waveguide admittance detecting system of the present invention;
FIG. 7 is a circuit diagram of a second operational amplifier of the silicon waveguide admittance detecting circuit of the silicon waveguide admittance detecting system of the present invention;
FIG. 8 is an equivalent circuit diagram of a sensor of the detection system of silicon waveguide admittance of the present invention;
FIG. 9 shows the relationship between the change △ V of the detected DC voltage and △ G when the variation △ G of the silicon waveguide admittance is within the range of 0.5 pS-5 nS;
FIG. 10 is a graph of △ V vs. △ G for a 0.5pS step detection system for silicon waveguide admittance according to the present invention.
Detailed Description
The invention is described in further detail below with reference to the accompanying examples.
The first embodiment is as follows: as shown in FIG. 3, a detection system for silicon waveguide admittance comprises an alternating current power supply AC, a sensor and a silicon waveguide admittance detection circuit, wherein the sensor comprises an excitation electrode 1, a sensing electrode 2, a substrate 3, a silicon layer 4 and a covering layer 5, the substrate 3 and the covering layer 5 are made of SiO2The substrate 3, the silicon layer 4 and the covering layer 5 are laminated in sequence from bottom to top, the excitation electrode 1 and the induction electrode 2 are arranged on the covering layer 5 at intervals, the excitation electrode 1 is connected with the positive pole of an alternating current power supply AC, and the induction electrode 2 is connected with the input end of a silicon waveguide admittance detection circuit. The sensor further comprises a grounding electrode 6, the grounding electrode 6 is arranged on the covering layer 5 and located between the excitation electrode 1 and the induction electrode 2, the grounding electrode 6, the excitation electrode 1 and the induction electrode 2 are identical in size, the distance between the grounding electrode 6 and the excitation electrode 1 is equal to the distance between the grounding electrode 6 and the induction electrode 2, and the grounding electrode 6 is grounded.
In the embodiment, the distance between the excitation electrode 1 and the grounding electrode 6 is 100 μm, the distance between the induction electrode 2 and the grounding electrode 6 is 100 μm, the cross sections of the excitation electrode 1, the induction electrode 2 and the grounding electrode 6 are all square, and the side length of the square is 100 μm.
As shown in fig. 4, in the present embodiment, the silicon waveguide admittance detecting circuit includes a pre-integrator circuit 7, a post-amplifier 8, and a low-pass filter 9; the pre-integrator 7 comprises a first operational amplifier OP1, a first capacitor C1, a second capacitor C2 and two electronic switches with the same structure, wherein the first operational amplifier OP1 has a positive input terminal, a negative input terminal, an output terminal, a power supply terminal and a ground terminal, the electronic switches have a positive control terminal, a negative control terminal, an input terminal and an output terminal, the two electronic switches are respectively called a first electronic switch K1 and a second electronic switch K2, the input terminal of the first electronic switch K1 is the input terminal of the pre-integrator 7, the positive control terminal of the first electronic switch K1 is connected with the negative control terminal of the second electronic switch K2, and the connection terminal is the positive control terminal of the pre-integrator 7, the negative control terminal of the first electronic switch K1 is connected with the positive control terminal of the second electronic switch K2, and the connection terminal is the negative control terminal of the pre-integrator 7, the output terminal of the first electronic switch K1, the input terminal of the second electronic switch K2, One end of a first capacitor C1 is connected with the negative input end of a first operational amplifier OP1, the positive input end of the first operational amplifier OP1 and the grounding end of the first operational amplifier OP1 are both grounded, the other end of the first capacitor C1, the output end of the first operational amplifier OP1 and one end of a second capacitor C2 are connected, the connecting end of the first capacitor C1 and the output end of the first operational amplifier OP1 are the output end of the pre-integrator circuit 7, the other end of the second capacitor C2 is grounded, and the power supply end of the first operational amplifier OP1 is connected with an external power supply VDD; the post-amplifier 8 comprises a second operational amplifier OP2, a first resistor R1, a second resistor R2 and a third capacitor C3, the second operational amplifier OP2 has a positive input terminal, a negative input terminal, an output terminal, a power supply terminal and a ground terminal, the positive input terminal of the second operational amplifier OP2 and the ground terminal of the second operational amplifier OP2 are both grounded, the power supply terminal of the second operational amplifier OP2 is connected to an external power supply VDD, one end of the first resistor R1 is the input terminal of the post-amplifier 8, the other end of the first resistor R1, one end of the second resistor R2 and the negative input terminal of the second operational amplifier OP2 are connected, the other end of the second resistor R2, the output terminal of the second operational amplifier OP2 and one end of the third capacitor C3 are connected, the connection terminal is the output terminal of the post-amplifier 8, and the other end of the third capacitor C3 is grounded; the low-pass filter 9 comprises a third resistor R3 and a fourth capacitor C4, one end of the third resistor R3 is an input end of the low-pass filter 9, the other end of the third resistor R3 is connected with one end of the fourth capacitor C4, the connection end of the third resistor R3 is an output end of the low-pass filter 9, and the other end of the fourth capacitor C4 is grounded; the positive control end of the pre-integrating circuit 7 is the positive control end of the silicon waveguide admittance detecting circuit and is accessed with a positive control signal, the negative control end of the pre-integrating circuit 7 is the negative control end of the silicon waveguide admittance detecting circuit and is accessed with a negative control signal, the negative control signal is the inverted signal of the positive control signal, the positive control signal and the negative control signal are used for controlling the on and off of the first electronic switch K1 and the second electronic switch K2, the input end of the pre-integrating circuit 7 is used as the input end of the silicon waveguide admittance detecting circuit, the output end of the pre-integrating circuit 7 is connected with the input end of the post-amplifier 8, the output end of the post-amplifier 8 is connected with the input end of the low-pass filter 9, and the output end of the low-pass filter 9 is used as the output end of the silicon waveguide admittance detecting.
As shown in fig. 5, in the present embodiment, the first operational amplifier OP1 includes a first MOS transistor M1, a second MOS transistor M2, a third MOS transistor M3, a fourth MOS transistor M4, a fifth MOS transistor M5, a sixth MOS transistor M6, a seventh MOS transistor M7, an eighth MOS transistor M8, a ninth MOS transistor M9, a tenth MOS transistor M10, an eleventh MOS transistor M11, a twelfth MOS transistor M12, a thirteenth MOS transistor M12, a fourteenth MOS transistor M12, a fifteenth MOS transistor M12, a sixteenth MOS transistor M12, a fourth resistor R12, a fifth capacitor C12, a sixth capacitor C12, and a direct current power DC, where the first MOS transistor M12, the second MOS transistor M12, the fifth MOS transistor M12, the sixth MOS transistor M12, the ninth MOS transistor M12, the tenth MOS transistor M12, the eleventh MOS transistor M12, the fourteenth MOS transistor M12, and the fourteenth MOS 12, the third MOS transistor M3, the fourth MOS transistor M4, the seventh MOS transistor M7, the eighth MOS transistor M8, the twelfth MOS transistor M12, the thirteenth MOS transistor M13 and the fifteenth MOS transistor M15 are all N-type MOS transistors; a source of the first MOS transistor M1, a source of the second MOS transistor M2, a source of the ninth MOS transistor M9, a source of the fourteenth MOS transistor M14 and a source of the sixteenth MOS transistor M16 are connected, and a connection terminal thereof is a power supply terminal of the first operational amplifier OP1, a drain of the first MOS transistor M1, a gate of the first MOS transistor M1, a drain of the second MOS transistor M2, a gate of the second MOS transistor M2, a drain of the third MOS transistor M3, a gate of the third MOS transistor M3, a drain of the fourth MOS transistor M4, a gate of the fourth MOS transistor M4, a gate of the ninth MOS transistor M9, a gate of the fourteenth MOS transistor M14 and a gate of the sixteenth MOS transistor M16 are connected, a source of the third MOS transistor M3 and one terminal of the fourth resistor R4 are connected, another terminal of the fourth resistor R4, a source of the fourth MOS transistor M4, a source of the seventh MOS transistor M4, a source of the twelfth transistor M4 and a connection terminal thereof is a source terminal of the twelfth MOS transistor OP 4, the gate of the fifth MOS transistor M5 is a positive input terminal of the first operational amplifier OP1, the source of the fifth MOS transistor M5, the source of the sixth MOS transistor M6 and the drain of the ninth MOS transistor M9 are connected, the drain of the fifth MOS transistor M5, the drain of the seventh MOS transistor M7, the gate of the seventh MOS transistor M7 and the gate of the eighth MOS transistor M8 are connected, the gate of the sixth MOS transistor M6 is a negative input terminal of the first operational amplifier OP1, the drain of the sixth MOS transistor M6, the drain of the eighth MOS transistor M8, the gate of the tenth MOS transistor M10 and one end of the fifth capacitor C5 are connected, the source of the tenth MOS transistor M10, the source of the eleventh MOS transistor M11 and the drain of the fourteenth MOS transistor M14 are connected, the drain of the tenth MOS transistor M10, the drain of the twelfth MOS transistor M12, the gate of the twelfth MOS transistor M12 and the drain of the thirteenth MOS transistor M13 are connected, the drain of the thirteenth MOS transistor M13 and the gate of the fifteenth MOS transistor M13 and the gate 13 and the drain of the fifteenth transistor M13, the grid electrode of the eleventh MOS transistor M11 is connected to the positive electrode of the DC power supply DC, the drain electrode of the fifteenth MOS transistor M15, the drain electrode of the sixteenth MOS transistor M16, the other end of the fifth capacitor C5 and the other end of the sixth capacitor C6 are connected, and the connection end thereof is the output end of the first operational amplifier OP1, and the conductance value of the fifteenth MOS transistor M15 is greater than the conductance value of the fifth MOS transistor M5, the conductance value of the sixth MOS transistor M6, the conductance value of the tenth MOS transistor M10 and the conductance value of the eleventh MOS transistor M11, respectively.
As shown in fig. 6, in the present embodiment, the electronic switch includes a seventeenth MOS transistor M17 and an eighteenth MOS transistor M18, and the seventeenth MOS transistor M17 is a P-type MOS transistor. The eighteenth MOS tube M18 is an N-type MOS tube; the source of the seventeenth MOS transistor M17 is connected to the source of the eighteenth MOS transistor M18, and the connection end of the seventeenth MOS transistor M17 is the input end of the electronic switch, the drain of the seventeenth MOS transistor M17 is connected to the drain of the eighteenth MOS transistor M18, and the connection end of the seventeenth MOS transistor M17 is the output end of the electronic switch, the gate of the seventeenth MOS transistor M17 is the negative control end of the electronic switch, and the gate of the eighteenth MOS transistor M18 is the positive control end of the electronic switch.
As shown in fig. 7, in the present embodiment, the second operational amplifier OP2 includes nineteenth MOS transistor M19, twentieth MOS transistor M20, twenty-first MOS transistor M21, twenty-twelfth MOS transistor M22, twenty-thirteenth MOS transistor M23, twenty-fourteenth MOS transistor M24, twenty-fifth MOS transistor M25, twenty-sixth MOS transistor M26, twenty-seventh MOS transistor M27, twenty-eighteen MOS transistor M28, twenty-ninth MOS transistor M29, thirty-third MOS transistor M30, thirty-first MOS transistor M31, third-twelfth MOS transistor M32, fifth resistor R5, and seventh capacitor C7, nineteenth MOS transistor M19, twenty-second MOS transistor M20, twenty-fifth MOS transistor M25, twenty-sixth MOS transistor M26, twenty-seventh MOS transistor M27, and thirty-third MOS transistor M30 which are all P-type MOS transistors, the twenty-first MOS transistor M21, the second twelfth MOS transistor M22, the twenty-third MOS transistor M23, the twenty-fourth MOS transistor M24, the twenty-ninth MOS transistor M28, the twenty-ninth MOS transistor M29, the thirty-first MOS transistor M31 and the third twelfth MOS transistor M32 are all N-type MOS transistors; the source electrode of the nineteenth MOS transistor M19, the source electrode of the twentieth MOS transistor M20, the source electrode of the twenty-fifth MOS transistor M25 and the source electrode of the thirtieth MOS transistor M30 are connected, and the connection end thereof is the power supply end of the second operational amplifier OP 2; the gate of the nineteenth MOS transistor M19, the drain of the nineteenth MOS transistor M19, the gate of the twentieth MOS transistor M20, the drain of the twenty-first MOS transistor M21, the gate of the twenty-fifth MOS transistor M25 and the gate of the thirty-first MOS transistor M30 are connected, the drain of the twentieth MOS transistor M20, the gate of the twenty-first MOS transistor M21, the gate of the twenty-second MOS transistor M22, the drain of the twenty-second MOS transistor M22 and the gate of the thirty-first MOS transistor M31 are connected, the source of the twenty-first MOS transistor M21 and the drain of the twenty-third MOS transistor M23 are connected, the source of the twenty-second MOS transistor M22, the gate of the twenty-third MOS transistor M23, the gate of the twenty-fourth MOS transistor M24 and the drain of the twenty-fourth MOS transistor M24 are connected, the source of the twenty-third MOS transistor M23 and one end of the fifth resistor R56 are connected, the other end of the fifth resistor R5, the source of the twenty-fourth MOS transistor M24, the twenty-fourth MOS transistor M24 and the source of the twenty-eighth MOS transistor M368672 and the grounding terminal of the twenty-eighth MOS transistor OP-eighth MOS transistor M3680, a drain of the twenty-fifth MOS transistor M25, a source of the twenty-sixth MOS transistor M26, and a source of the twenty-seventh MOS transistor M27 are connected, a gate of the twenty-sixth MOS transistor M26 is a positive input terminal of the second operational amplifier OP2, a drain of the twenty-sixth MOS transistor M26, a drain of the twenty-eighth MOS transistor M28, a gate of the twenty-eighth MOS transistor M28, and a gate of the twenty-ninth MOS transistor M29 are connected, a gate of the twenty-seventh MOS transistor M27 is a negative input terminal of the second operational amplifier OP2, a drain of the twenty-seventh MOS transistor M27, a drain of the twenty-ninth MOS transistor M29, a drain of the thirty-first MOS transistor M31, and a gate of the thirty-second MOS transistor M32 are connected, a drain of the thirty-third MOS transistor M30, one end of the seventh capacitor C7, and a drain of the thirty-second MOS transistor M32 are connected, and a connection terminal thereof is an output terminal of the second operational amplifier 2, and a source of the seventh capacitor C7 is connected to the eleventh MOS transistor M31.
As shown in fig. 8, since the ground electrode is added between the excitation electrode and the induction electrode, the stray capacitance between the excitation electrode and the induction electrode is shielded, and instead, the stray capacitance C10 between the excitation electrode and the ground electrode and the stray capacitance C12 between the induction electrode and the ground electrode are shielded. Wherein G2 is the silicon waveguide admittance between the excitation electrode and the grounding electrode, G3 is the silicon waveguide admittance between the induction electrode and the grounding electrode, C8 is the contact capacitance between the excitation electrode and the silicon layer, C9 is the contact capacitance between the grounding electrode and the silicon layer, and C11 is the contact capacitance between the induction electrode and the silicon layer. The distances among the excitation electrode, the induction electrode and the grounding electrode are all 100 mu m, and the excitation electrode, the induction electrode and the grounding electrode are all square electrodes with the length of 100 mu m.
When the silicon waveguide admittance variation △ G varies within the range of 0.5 pS-5 nS, the curve of variation of the DC voltage variation △ V detected by the detection system of the invention with △ G is shown in FIG. 9, and analysis of FIG. 9 shows that △ V increases linearly with △ G, thus proving that the detection system of the silicon waveguide admittance of the invention has good linearity and sensitivity of 1.7 × 107When △ G is 0.5pS, the conditions of not considering the self-noise of the detection circuit and considering the self-noise of the detection circuit in the bandwidth of 50MHz are simulated respectively, as shown in fig. 10, the analysis of fig. 10 shows that △ V has a linear variation relationship with △ G in both cases, and the slope of △ V/△ G is relatively close in both cases.
Claims (6)
1. SiliconThe detection system of the waveguide admittance comprises an alternating current power supply, a sensor and a silicon waveguide admittance detection circuit, wherein the sensor comprises an excitation electrode, an induction electrode, a substrate, a silicon layer and a covering layer, and the substrate and the covering layer are made of SiO (silicon dioxide)2The substrate, the silicon layer and the covering layer are sequentially laminated from bottom to top, the excitation electrode and the induction electrode are arranged on the covering layer at intervals, the excitation electrode is connected with the positive electrode of the alternating current power supply, and the induction electrode is connected with the input end of the silicon waveguide admittance detection circuit. The sensor is characterized by further comprising a grounding electrode, wherein the grounding electrode is arranged on the covering layer and is positioned between the excitation electrode and the induction electrode, the grounding electrode, the excitation electrode and the induction electrode are identical in size, the distance between the grounding electrode and the excitation electrode is equal to the distance between the grounding electrode and the induction electrode, and the grounding electrode is grounded.
2. The silicon waveguide admittance detecting system of claim 1, wherein the distance between the excitation electrode and the ground electrode is 100 μm, the distance between the sensing electrode and the ground electrode is 100 μm, the cross-sections of the excitation electrode, the sensing electrode and the ground electrode are all square, and the side length of the square is 100 μm.
3. A silicon waveguide admittance detecting system according to claim 1, wherein said silicon waveguide admittance detecting circuit includes a pre-integrator circuit, a post-amplifier and a low-pass filter;
the pre-integration circuit comprises a first operational amplifier, a first capacitor, a second capacitor and two electronic switches with the same structure, wherein the first operational amplifier is provided with a positive input end, a negative input end, an output end, a power supply end and a grounding end, the electronic switches are provided with a positive control end, a negative control end, an input end and an output end and are respectively called a first electronic switch and a second electronic switch, the input end of the first electronic switch is the input end of the pre-integration circuit, the positive control end of the first electronic switch is connected with the negative control end of the second electronic switch, the connecting end of the positive control end of the first electronic switch is the positive control end of the pre-integration circuit, the negative control end of the first electronic switch is connected with the positive control end of the second electronic switch, and the connecting end of the negative control end of the pre-integration circuit is the negative control end of the pre-integration circuit, the output end of the first electronic switch, the input end of the second electronic switch, and one end of the first capacitor are connected to the negative input end of the first operational amplifier, the positive input end of the first operational amplifier and the ground end of the first operational amplifier are all grounded, the other end of the first capacitor, the output end of the first operational amplifier and one end of the second capacitor are connected, the connection end of the first capacitor and the output end of the first operational amplifier is the output end of the pre-integrator, the other end of the second capacitor is grounded, and the power supply end of the first operational amplifier is connected to an external power supply;
the post amplifier comprises a second operational amplifier, a first resistor, a second resistor and a third capacitor, the second operational amplifier has a positive input terminal, a negative input terminal, an output terminal, a power terminal and a ground terminal, the positive input end of the second operational amplifier and the grounding end of the second operational amplifier are both grounded, the power supply end of the second operational amplifier is connected with an external power supply, one end of the first resistor is the input end of the post amplifier, the other end of the first resistor and one end of the second resistor are connected with the negative input end of the second operational amplifier, the other end of the second resistor, the output end of the second operational amplifier and one end of the third capacitor are connected, the connection end of the second resistor and the output end of the second operational amplifier is the output end of the post-amplifier, and the other end of the third capacitor is grounded;
the low-pass filter comprises a third resistor and a fourth capacitor, one end of the third resistor is an input end of the low-pass filter, the other end of the third resistor is connected with one end of the fourth capacitor, the connection end of the third resistor is an output end of the low-pass filter, and the other end of the fourth capacitor is grounded;
the positive control end of the pre-integration circuit is the positive control end of the silicon waveguide admittance detecting circuit and is connected with a positive control signal, the negative control end of the pre-integration circuit is the negative control end of the silicon waveguide admittance detecting circuit and is connected with a negative control signal, the negative control signal is the inverted signal of a positive control signal, the positive control signal and the negative control signal are used for controlling the on and off of the first electronic switch and the second electronic switch, the input end of the pre-integration circuit is used as the input end of the silicon waveguide admittance detecting circuit, the output end of the pre-integrator circuit is connected with the input end of the post-amplifier, the output end of the post-amplifier is connected with the input end of the low-pass filter, the output end of the low-pass filter is used as the output end of the silicon waveguide admittance detecting circuit.
4. The system according to claim 3, wherein the first operational amplifier comprises a first MOS transistor, a second MOS transistor, a third MOS transistor, a fourth MOS transistor, a fifth MOS transistor, a sixth MOS transistor, a seventh MOS transistor, an eighth MOS transistor, a ninth MOS transistor, a tenth MOS transistor, an eleventh MOS transistor, a twelfth MOS transistor, a thirteenth MOS transistor, a fourteenth MOS transistor, a fifteenth MOS transistor, a sixteenth MOS transistor, a fourth resistor, a fifth capacitor, a sixth capacitor and a dc power supply, the first MOS transistor, the second MOS transistor, the fifth MOS transistor, the sixth MOS transistor, the ninth MOS transistor, the tenth MOS transistor, the eleventh MOS transistor, the fourteenth MOS transistor and the sixteenth MOS transistor are P-type MOS transistors, the third MOS transistor, the fourth MOS transistor, the seventh MOS transistor, the eighth MOS transistor, the ninth MOS resistor, the fifth capacitor, the sixth capacitor and the dc power supply, and the P-type MOS transistors, The twelfth MOS tube, the thirteenth MOS tube and the fifteenth MOS tube are all N-type MOS tubes; the source of the first MOS transistor, the source of the second MOS transistor, the source of the ninth MOS transistor, the source of the fourteenth MOS transistor and the source of the sixteenth MOS transistor are connected, and the connection end is the power supply end of the first operational amplifier, the drain of the first MOS transistor, the gate of the first MOS transistor, the drain of the second MOS transistor, the gate of the second MOS transistor, the drain of the third MOS transistor, the gate of the third MOS transistor, the drain of the fourth MOS transistor, the gate of the ninth MOS transistor, the gate of the fourteenth MOS transistor and the gate of the sixteenth MOS transistor are connected, the source of the third MOS transistor and one end of the fourth resistor are connected, the other end of the fourth resistor, the source of the fourth MOS transistor, the source of the seventh MOS transistor, the gate of the sixth MOS transistor and the gate of the sixteenth MOS transistor are connected, and the other end of the fourth resistor is connected with the source of the fourth resistor, A source of the eighth MOS transistor, a source of the twelfth MOS transistor, a source of the thirteenth MOS transistor, a source of the fifteenth MOS transistor, and a negative electrode of the dc power supply are connected, and a connection end thereof is a ground end of the first operational amplifier, a gate of the fifth MOS transistor is a positive input end of the first operational amplifier, a source of the fifth MOS transistor, a source of the sixth MOS transistor, and a drain of the ninth MOS transistor are connected, a drain of the fifth MOS transistor, a drain of the seventh MOS transistor, a gate of the seventh MOS transistor, and a gate of the eighth MOS transistor are connected, a gate of the sixth MOS transistor is a negative input end of the first operational amplifier, a drain of the sixth MOS transistor, a drain of the eighth MOS transistor, a gate of the tenth MOS transistor, and one end of the fifth capacitor are connected, the source of the tenth MOS transistor, the source of the eleventh MOS transistor and the drain of the fourteenth MOS transistor are connected, the drain of the tenth MOS transistor, the drain of the twelfth MOS transistor, the gate of the twelfth MOS transistor and the gate of the thirteenth MOS transistor are connected, the drain of the eleventh MOS transistor, the drain of the thirteenth MOS transistor, the gate of the fifteenth MOS transistor and one end of the sixth capacitor are connected, the gate of the eleventh MOS transistor and the positive electrode of the dc power supply are connected, the drain of the fifteenth MOS transistor, the drain of the sixteenth MOS transistor, the other end of the fifth capacitor and the other end of the sixth capacitor are connected, the connection end of the fifteenth MOS transistor is the output end of the first operational amplifier, and the conductance value of the fifteenth MOS transistor is respectively greater than the conductance value of the fifth MOS transistor, and the gate of the fourteenth MOS transistor is connected, the drain of the eleventh MOS transistor and the gate of the fifteenth MOS are connected, the drain of the fifteenth MOS transistor and the other end of the sixth capacitor are connected, and the connection end of, The conductance value of the sixth MOS tube, the conductance value of the tenth MOS tube and the conductance value of the eleventh MOS tube.
5. The system according to claim 3, wherein the electronic switch comprises a seventeenth MOS transistor and an eighteenth MOS transistor, and the seventeenth MOS transistor is a P-type MOS transistor. The eighteenth MOS tube is an N-type MOS tube; the source electrode of the seventeenth MOS tube is connected with the source electrode of the eighteenth MOS tube, the connecting end of the seventeenth MOS tube is the input end of the electronic switch, the drain electrode of the seventeenth MOS tube is connected with the drain electrode of the eighteenth MOS tube, the connecting end of the seventeenth MOS tube is the output end of the electronic switch, the grid electrode of the seventeenth MOS tube is the negative control end of the electronic switch, and the grid electrode of the eighteenth MOS tube is the positive control end of the electronic switch.
6. The system of claim 3, wherein the second operational amplifier comprises a nineteenth MOS transistor, a twentieth MOS transistor, a twenty-first MOS transistor, a twenty-twelfth MOS transistor, a twenty-thirteenth MOS transistor, a twenty-fourteenth MOS transistor, a twenty-fifth MOS transistor, a twenty-sixth MOS transistor, a twenty-seventh MOS transistor, a twenty-eighteen MOS transistor, a twenty-ninth MOS transistor, a thirty-sixth MOS transistor, a thirty-eleventh MOS transistor, a thirty-twelfth MOS transistor, a fifth resistor and a seventh capacitor, the nineteenth MOS transistor, the twentieth MOS transistor, the twenty-fifth MOS transistor, the twenty-sixth MOS transistor, the twenty-seventh MOS transistor and the thirty-fifth MOS transistor are P-type MOS transistors, the twenty-first MOS transistor, the twenty-twelfth MOS transistor, the twenty-thirteenth MOS transistor, the twenty-fourteenth MOS transistor, the twenty-eighteenth MOS transistor, The twenty-ninth MOS tube, the thirty-first MOS tube and the thirty-second MOS tube are all N-type MOS tubes; the source electrode of the nineteenth MOS tube, the source electrode of the twentieth MOS tube, the source electrode of the twenty-fifth MOS tube and the source electrode of the thirtieth MOS tube are connected, and the connection end of the source electrode of the twenty-fifth MOS tube and the source electrode of the thirtieth MOS tube is the power supply end of the second operational amplifier; the gate of the nineteenth MOS transistor, the drain of the nineteenth MOS transistor, the gate of the twentieth MOS transistor, the drain of the twenty-first MOS transistor, the gate of the twenty-fifth MOS transistor and the gate of the thirty-first MOS transistor are connected, the drain of the twentieth MOS transistor, the gate of the twenty-first MOS transistor, the gate of the twenty-twelfth MOS transistor, the drain of the twenty-twelfth MOS transistor and the gate of the thirty-eleventh MOS transistor are connected, the source of the twenty-first MOS transistor and the drain of the twenty-thirteenth MOS transistor are connected, the source of the twenty-twelfth MOS transistor, the gate of the twenty-thirteenth MOS transistor, the gate of the twenty-fourteenth MOS transistor and the drain of the twenty-fourteenth MOS transistor are connected, the source of the twenty-thirteenth MOS transistor and one end of the fifth resistor are connected, the other end of the fifth resistor is connected, The source of the twenty-fourth MOS transistor, the source of the twenty-eighth MOS transistor, the source of the twenty-ninth MOS transistor and the source of the third twelfth MOS transistor are connected, and the connection end is the ground end of the second operational amplifier, the drain of the twenty-fifth MOS transistor, the source of the twenty-sixth MOS transistor and the source of the twenty-seventh MOS transistor are connected, the gate of the twenty-sixth MOS transistor is the positive input end of the second operational amplifier, the drain of the twenty-sixth MOS transistor, the drain of the twenty-eighteen MOS transistor, the gate of the twenty-eighteen MOS transistor and the gate of the twenty-ninth MOS transistor are connected, the gate of the twenty-seventh MOS transistor is the negative input end of the second operational amplifier, the drain of the twenty-seventh MOS transistor, the drain of the twenty-ninth MOS transistor, the drain of the thirty-ninth MOS transistor and the gate of the twelfth MOS transistor are connected, the drain electrode of the thirty-third MOS transistor, one end of the seventh capacitor and the drain electrode of the thirty-second MOS transistor are connected, the connection end of the seventh capacitor is the output end of the second operational amplifier, and the other end of the seventh capacitor is connected with the source electrode of the thirty-first MOS transistor.
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