CN110661531A

CN110661531A - Suppression of metastability in a noise shaping control loop using differential delay feedback

Info

Publication number: CN110661531A
Application number: CN201910579869.9A
Authority: CN
Inventors: A·马丁·马林森
Original assignee: Silicon Valley Intervention Co Ltd
Current assignee: Silicon Valley Intervention Co Ltd
Priority date: 2018-06-28
Filing date: 2019-06-28
Publication date: 2020-01-07
Anticipated expiration: 2039-06-28
Also published as: CN110661531B

Abstract

Described herein are sigma delta modulators with improved metastability, wherein the control loop remains stable. In one embodiment, the Σ Δ modulator utilizes feedback of different delays to successive integrators of the control loop to suppress the metastability error without compromising the stability of the control loop. This is achieved by including one or more quantizers in the control loop. The technique may be applied to a control loop of at least two orders, i.e. having two or more integrator stages, where at least one feedback term after the first integrator is non-zero.

Description

Suppression of metastability in a noise shaping control loop using differential delay feedback

This application claims priority from U.S. provisional application No.62/691,533 filed on 28.6.2018, which is incorporated herein by reference in its entirety.

Technical Field

The present invention relates generally to sigma delta modulators and more particularly to sigma delta modulators with improved metastability.

Background

The analog-to-digital conversion may be performed in a control loop using quantized feedback. An analog-to-digital converter (ADC) having such characteristics is commonly referred to as a sigma delta converter or sigma delta modulator, the term "modulator" referring to an output digital data stream having a certain symbol pattern or modulation applied thereto by a control loop. The terms "Σ Δ modulator" and "noise shaping control loop" are often used interchangeably in the art, although the latter is more descriptive. Circuit designers often prefer to use such sigma delta modulators because, in many cases, such sigma delta modulators may be easier to design and less costly to manufacture than other types of ADCs.

In such a noise shaping control loop, a continuous analog signal is applied at the input and a digital pattern representing the signal appears from the output. The digital signal is generated by controlling one or more quantization elements in the loop, for example by a non-linear element in the loop, such as a flip-flop or comparator, having a discrete set of non-continuous output values for any given continuous input quantity.

Σ Δ modulation works by constraining the feedback parameter to one of a set of at least two specific values, and a control loop of arbitrary order ensures that the average feedback value is equal to the input. The instantaneous deviation from the ideal continuous feedback that the quantising element must introduce represents noise and a complex, possibly high order, control loop can suppress or "shape" this noise. "shaping" the noise means filtering it, usually so that it does not occur in certain frequency bands. Thus, the loop operates to suppress this noise in certain frequency bands of interest, usually at the expense of increased noise in application-independent frequency bands. Therefore, the Σ Δ modulator is sometimes also referred to as a "noise shaping loop".

A known problem with quantization control loops is that the timing of the feedback can vary depending on the metastability of the quantization element. Metastability refers to the variation in time required to obtain the output of a D-type flip-flop (DFF) or similar quantizer.

Ideally, a DFF receives a clock signal (commonly referred to as "Clk") and momentarily provides an output (referred to as "Q") at one of two levels, a high level if the input (referred to as "D") is above a certain threshold, or a low level if the D input is below the threshold. In practice, because the DFF includes physical components, a finite amount of time is required to determine whether the D input exceeds the threshold, and thus the Q output is slightly after the Clk signal. This finite time delay is commonly referred to as the "Clk to Q" delay.

Thus, metastability is the variation of the Clk to Q delay of a DFF or other quantizer. One factor in this variation is that if the D input is almost exactly at the threshold level, the DFF or other quantizer cannot quickly determine the appropriate output level. In principle, the Clk-to-Q delay may become infinite in this case; in practice, however, thermal agitation of the circuit will result in decisions being made for a limited amount of time, which may be much longer than the nominal Clk to Q delay of the quantizer.

One solution to the meta-stability problem is to use multiple DFFs (or other quantizers) in series. However, this introduces an extra time delay between the input of the first DFF and the output of the last DFF; for example, using two DFFs will add one clock cycle to the delay. Adding delay in the control loop through cascaded quantizers reduces the phase margin needed to ensure loop stability and requires a reduction in loop bandwidth and therefore reduced performance.

For these reasons, a simple and inexpensive method of reducing metastability in a Σ Δ modulator without reducing stability or performance would be useful.

Disclosure of Invention

An apparatus and method for improving the performance of a sigma delta modulator by improving metastability without compromising the stability of the control loop is described herein.

An embodiment describes an apparatus comprising: a first comparator configured to receive an input signal and a first feedback signal and generate a first error signal, the first error signal being a difference between the input signal and the first feedback signal; a first integrator configured to receive the first error signal and to integrate the first error signal; a second comparator configured to receive the integrated error signal and a second feedback signal from the first integrator and generate a second error signal, the second error signal being a difference between the integrated first error signal and the second feedback signal; a second integrator configured to receive the second error signal and to integrate the second error signal; a first quantizer configured to receive the integrated second error signal from the second integrator and generate an output signal; a feedback loop for generating a first feedback signal and a second feedback signal, comprising: a digital-to-analog converter configured to receive the output signal and generate a modified output signal; a second quantizer configured to receive the modified output signal and generate a quantized modified output signal; a first weighting element configured to receive and weight the quantized modified output signal to generate a first feedback signal; a second weighting element configured to receive the modified output signal and to weight it to generate a second feedback signal.

Another embodiment describes an apparatus comprising: a first comparator configured to receive an input signal and a first feedback signal and generate a first error signal, the first error signal being a difference between the input signal and the first feedback signal; a first integrator configured to receive the first error signal and to integrate the first error signal; a second comparator configured to receive the integrated error signal and a second feedback signal from the first integrator and generate a second error signal, the second error signal being a difference between the integrated first error signal and the second feedback signal; a second integrator configured to receive the second error signal and to integrate the second error signal; a third comparator configured to receive the integrated error signal and a third feedback signal from the second integrator and generate a third error signal, the third error signal being a difference between the integrated second error signal and the third feedback signal; a third integrator configured to receive the third error signal and integrate the third error signal; a first quantizer configured to receive the integrated third error signal from the third integrator and generate an output signal; a feedback loop for generating a first feedback signal and a second feedback signal, comprising: a digital-to-analog converter configured to receive the output signal and generate a modified output signal; a second quantizer configured to receive the modified output signal and generate a quantized modified output signal; a first weighting element configured to receive and weight the quantized modified output signal to generate a first feedback signal; a second weighting element configured to receive and weight the quantized modified output signal to generate a second feedback signal; a third weighting element configured to receive the modified output signal and to weight it to generate a third feedback signal.

Yet another embodiment describes an apparatus comprising: a first comparator configured to receive an input signal and a first feedback signal and generate a first error signal, the first error signal being a difference between the input signal and the first feedback signal; a first integrator configured to receive the first error signal and to integrate the first error signal; a second comparator configured to receive the integrated error signal and a second feedback signal from the first integrator and generate a second error signal, the second error signal being a difference between the integrated first error signal and the second feedback signal; a second integrator configured to receive the second error signal and to integrate the second error signal; a third comparator configured to receive the integrated error signal and a third feedback signal from the second integrator and generate a third error signal, the third error signal being a difference between the integrated second error signal and the third feedback signal; a third integrator configured to receive the third error signal and integrate the third error signal; a first quantizer configured to receive the integrated third error signal from the third integrator and generate an output signal; a feedback loop for generating a first feedback signal and a second feedback signal, comprising: a digital-to-analog converter configured to receive the output signal and generate a modified output signal; a second quantizer configured to receive the modified output signal and generate a quantized modified output signal; a third quantizer configured to receive the quantized modified output signal and generate a further quantized modified output signal; a first weighting element configured to receive and weight the further quantized modified output signal to generate a first feedback signal; a second weighting element configured to receive and weight the quantized modified output signal to generate a second feedback signal; a third weighting element configured to receive the modified output signal and to weight it to generate a third feedback signal.

Drawings

FIG. 1 is a diagram of a pair of cascaded D-type flip-flops (DFFs) as known in the prior art.

Fig. 2 is a diagram of a typical high-order Σ Δ modulator known in the prior art.

Fig. 3 is a diagram of a Σ Δ modulator with improved metastability, according to one embodiment.

Fig. 4 is a diagram of a Σ Δ modulator with improved metastability according to another embodiment.

Fig. 5 is a diagram of a Σ Δ modulator with improved metastability according to yet another embodiment.

Detailed Description

Described herein are sigma delta modulators with improved metastability, wherein the control loop remains stable. In one embodiment, the Σ Δ modulator utilizes different delay feedback to successive integrators of the control loop to suppress the metastability error without compromising the stability of the control loop. This is achieved by including one or more quantizers in the control loop. The technique may be applied to a control loop of at least two orders, (i.e. a control loop with two or more integrator stages, where at least one feedback term after the first integrator is non-zero.

The Σ Δ loop quantizes the feedback both in time and in amplitude. That is, the feedback is forced to a certain level and held at that level for a defined period of time. The average of the quantized values is balanced with the continuous input value; however, this is only valid if the defined time period of each quantized value is the same. Typically, the defined time period is the interval from one clock cycle to the next. More specifically, the limited hold period is from one Clk to Q output to the next Clk to Q output, since the feedback is connected to the Q output of the quantizer, which is clocked by the clock. If any of these Clk to Q outputs are not the same, the hold time of the feedback signal will vary from cycle to cycle.

A sigma delta modulator that relies on the integration of the quantization level over time will exhibit errors due to this variation in the Clk to Q time. As described above, if a plurality of DFFs connected in series are used, the influence of metastability can be greatly reduced. This is because the probability that the output of a DFF is at exactly the same metastable point as its input is very low, and therefore, even if the first DFF in the chain is metastable, the second DFF in the chain is unlikely to be metastable. This property of multiple DFFs in series is known in the art; see, e.g., Xilinx Application Note XAPP077, "Metastaviability Considerations", 1 month 1997, version 1.0.

Fig. 1 (which is fig. 3 from page 2 to page 57 of the cited Xilinx reference) shows how two DFFs can be placed in series in this way to obtain a stable output state.

However, also as mentioned above, cascaded DFFs (i.e., DFFs connected in series) create a problem in that the time delay from the input of the first DFF to the output of the last DFF is now at least one clock cycle, so stabilizing the control loop of the Σ Δ modulator by using a DFF chain or other quantizer with at least one clock delay therein requires reducing the loop bandwidth and thus the performance of the circuit.

Furthermore, when optimized, the Σ Δ modulator operates at the edge of stability, and the delay per clock cycle caused by adding another DFF increases the phase delay instability of the circuit (as known in the art, unlike the metastability of DFFs). Thus, the problem becomes how to solve the meta-stability problem without compromising the stability of the control loop.

An example of a higher order Σ Δ modulator can be found in r.schreier, The Delta-Sigma Design Toolbox Version 7.1, Analog Devices, 12/11/2004.

The circuit 200 of fig. 2 shows a typical Σ Δ high order modulator (this is a CIFB (integrator feedback cascade) even order circuit from page 21 of The Delta-Sigma Design Toolbox) as known in The art.

As is known in the art, in such a Σ Δ modulator, the input signal u (n) is applied and compared with a fed-back weighted signal by a comparator at various points. (as used herein, the term "comparator" includes any type of comparator, adder, summer, or differential element; one skilled in the art will recognize that the use of certain devices requires inverting the feedback signals to obtain a comparison, as shown in FIG. 2.) in circuit 200, two feedback signals are generated by passing output signal v (n) through a digital-to-analog converter (DAC) and weighting the output signal v (n) by weighting elements a1 and a 2. (the other feedback temporary signal g1 inserts zeros to limit noise and may be ignored here.) the result of each comparison, which represents an error in the signal, is integrated and the final result is quantized to generate the output signal. The DACs in the feedback path have as many output levels as there are quantizers in the forward path. (amplifiers c1 and c2 allow for the desired coefficients; these coefficients are typically 1.)

As is well known, a sigma delta modulator may have a higher order than shown in fig. 2, i.e. there may be more integrators and taps where the fed back output signal is weighted and compared with the signal as it is processed. In some embodiments, the input signal may be applied to the front end of the circuit 200 only as input b1, so that inputs b2 and b3 may be zero.

A Σ Δ modulator such as circuit 200 satisfies the above conditions using the described technique of reducing metastability; that is, it has at least two integrators, and at least one feedback term after the first integrator is non-zero (which means that both the a1 and a2 feedback terms are non-zero).

Given these conditions, in the described embodiments, to reduce metastability, one or more quantizers are added to some, but not all, of the feedback terms, such that at least one of the feedback terms has no additional time delay.

Fig. 3 is a circuit diagram illustrating one embodiment of the present method in which a high-order Σ Δ modulator 300 has a single metastability-reduced quantizer in the control loop. The illustrated embodiment of circuit 300 is similar to the embodiment of circuit 200 of fig. 2, but with at least two significant differences. First, as mentioned above, it is assumed here that the inputs b2 and b3 are zero, so the inputs b2 and b3 are not present in fig. 3. (Again, feedback signal g1, although shown, is for noise purposes and may be ignored for the present method.)

In addition, the quantizer 302 is placed in the control loop. Since the a1 feedback term is one that is balanced against its input b1 (i.e., compared to the a1 feedback term), this is the case where no meta-stability feedback is desired, and therefore, as shown, a quantizer is added before the a1 weighting element.

The a1 feedback term is the output of the quantizer 302, which is a "delayed" quantizer like the second DFF in fig. 1, which is compared to the original input signal b 1. As shown in fig. 1, there are now two quantizers in the circuit; because of the low metastability of the quantizer 302 (i.e., the second quantizer), errors in the circuit 300 due to metastability are greatly reduced, as shown in fig. 1.

As mentioned above, it is also important to maintain stability of the control loop. The stability of the loop is controlled largely by the value of the higher order term, e.g., the value of weighting element a2 in circuit 300, which is not delayed and is used as a damping factor in the control loop. Typically, the elements after the first integrator are used to control loop stability, since feedback to successive integrator stages is used to control the phase shift near the cross-over point (cross-over), thereby optimizing the closed loop bandwidth and gain.

The elements after the first integrator (e.g., the term a2 in circuit 300) will suffer from metastability because these elements will not benefit from the cascade of quantizers; thus, metastability may exist at the input to the quantizer 302, but is suppressed at the output of the quantizer 302. However, while metastability in the elements after the first integrator does not significantly reduce the phase and damping characteristics of the loop, if this metastability exists at the first integrator input, it can greatly affect the accuracy of circuit 300.

The influence of metastability effects in the control loop after the first integrator on the overall accuracy is reduced. This can be appreciated by observing that term a2 in circuit 300 balances the integrals of the inputs; therefore, the error at this point in the loop (back to the reference input) is distinctive. Any effect of metastability present at the output of a2 in circuit 300 is reduced in its effect on frequency when referenced to the input. Thus, metastability in a2 is "shaped" in its effect on signal transfer characteristics in a similar manner to noise shaping of a loop. In particular, metastability at the output of a2 is first order noise shaped into the signal band.

The output level of the DAC is discrete and the voltage used by the quantizer 302 deviates from the DAC output, so there is no metastability in the quantizer 302. The quantizer 302 may be as simple as a DFF if the output of the DAC is 0 or 1.

Fig. 4 is a circuit diagram of a third order Σ Δ modulator 400 of the present method, in which the technique is again used to achieve a significant reduction in metastability. Typically, a higher order control loop will cause greater suppression of quantizer noise.

In circuit 400, there are two

additional quantizers

402 and 404 in the control loop, thereby creating two additional delays to the input stage in comparison to the signal; the quantizer 402 precedes the a1 feedback term, and the quantizer 404 precedes the a2 feedback term.

Now, the metastability present at the output of a3 relates to the input via the two integrators, since the signal at a3 is being added to the quadratic integration of the input. Thus, the metastability error related to the input is now second order noise shaping, greatly suppressing any effect of metastability. The already greatly improved metastability present at the output of the quantizer 404 is suppressed by the first order, as described above with respect to the circuit 300 of fig. 3. Due to the cascade of three quantizers, i.e., DAC, quantizer 404, and quantizer 402, there is substantially no metastability at the first integrator input. In practice, element 402 may be omitted, since it is generally considered that two cascaded quantizers are sufficient to eliminate any metastability.

As in circuit 300, in circuit 400, input b2 and the higher order inputs are assumed to be zero and are therefore not shown in fig. 4. However, while the performance of the Σ Δ modulator is typically high, the performance of the Σ Δ modulator is typically not necessarily high if the control loop enters only those integrators before the additional quantizer in the feedback with non-zero feed forward stages.

Fig. 5 is a circuit diagram of a third order Σ Δ modulator 500 of the present method, in which b2 and higher feed forward stages are non-zero, with two

additional quantizers

502 and 504 in the control loop. Note that any non-zero feed forward term applied to the integrator with additional delay will benefit from metastability reduction.

However, the feed forward term b4 will not benefit from metastability reduction because it feeds an integrator without additional delay elements in its feedback path. Nevertheless, the use of

quantizers

502 and 504 reduces the meta-stability problem to some extent, since the input signal is not applied entirely via b 4.

By using this technique, a Σ Δ modulator in which metastability is reduced without deteriorating the stability of the control loop can be constructed. One skilled in the art will recognize that sigma delta modulators of any order may be constructed in accordance with the principles and methods described herein.

The specific components that may be used in a sigma delta modulator are known in the art. Various types of clocks capable of generating clock signals of different phases are available, as are various devices suitable for use as quantizers. For example, the flip-flop may be used as a simple quantizer; the comparator will quantize the input level more accurately, but will typically still provide its output to the flip-flop to hold the output value for an appropriate period of time. The integrator may be a switched capacitor integrator or other known device. Other options will be apparent to those skilled in the art in light of the teachings herein.

The disclosed system has been described above with reference to several embodiments. Other embodiments will be apparent to those skilled in the art in view of this disclosure. Certain aspects of the described methods and apparatus may be implemented using configurations other than, or in combination with, the components described in the embodiments above.

For example, various options will be apparent to those skilled in the art as will be appreciated. Further, the illustrations of feedback loops, integrators, quantizers, etc. are exemplary; those skilled in the art will be able to select the appropriate type and number of elements to suit a particular application.

These and other variations of embodiments are intended to be covered by the present invention, which is limited only by the appended claims.

In addition, the present disclosure includes, but is not limited to, the following technical solutions:

scheme 1. an apparatus comprising:

a first comparator configured to receive an input signal and a first feedback signal and generate a first error signal, the first error signal being a difference between the input signal and the first feedback signal;

a first integrator configured to receive the first error signal and to integrate the first error signal;

a second comparator configured to receive the integrated first error signal and a second feedback signal from the first integrator and generate a second error signal, the second error signal being a difference between the integrated first error signal and the second feedback signal;

a second integrator configured to receive the second error signal and to integrate the second error signal;

a first quantizer configured to receive the integrated second error signal from the second integrator and generate an output signal;

a feedback loop for generating the first feedback signal and the second feedback signal, comprising:

a digital-to-analog converter configured to receive the output signal and generate a modified output signal;

a second quantizer configured to receive the modified output signal and generate a quantized modified output signal;

a first weighting element configured to receive and weight the quantized modified output signal to generate the first feedback signal;

a second weighting element configured to receive and weight the modified output signal to generate the second feedback signal.

Scheme 2. the apparatus of scheme 1, wherein the second quantizer comprises a flip-flop.

Scheme 3. the apparatus of scheme 1, wherein the second quantizer comprises a comparator and a flip-flop.

Scheme 4. the method of scheme 1, wherein the first integrator is a switched capacitor integrator.

Scheme 5. the apparatus of scheme 1, wherein the second integrator is a switched capacitor integrator.

Scheme 6. the apparatus of scheme 1, further comprising: a third weighting element configured to receive and weight the input signal to generate a weighted input signal, and wherein the second comparator is further configured to receive the weighted input signal and add the weighted input signal to a difference between the integrated first error signal and the second feedback signal to generate the second error signal.

Scheme 7. the apparatus of scheme 1, further comprising:

a third weighting element configured to receive the input signal and weight it to generate a weighted input signal; and an adder configured to add the weighted input signal to the integrated second error signal prior to receiving and quantizing the integrated second error signal by the first quantizer.

Scheme 8. an apparatus comprising:

a third comparator configured to receive the integrated second error signal and a third feedback signal from the second integrator and generate a third error signal, the third error signal being a difference between the integrated second error signal and the third feedback signal;

a third integrator configured to receive the third error signal and to integrate the third error signal;

a first quantizer configured to receive the integrated third error signal from the third integrator and generate an output signal;

a feedback loop for generating the first, second, and third feedback signals, comprising:

a second weighting element configured to receive and weight the quantized modified output signal to generate the second feedback signal;

a third weighting element configured to receive and weight the modified output signal to generate the third feedback signal.

Scheme 9. the apparatus of scheme 8, wherein the second quantizer comprises a flip-flop.

Scheme 10. the apparatus of scheme 8, wherein the second quantizer comprises a comparator and a flip-flop.

The apparatus of scheme 11. the apparatus of scheme 8 wherein one or more of the first integrator, the second integrator, and the third integrator are switched capacitor integrators.

Scheme 12. the apparatus of scheme 8, further comprising: a fourth weighting element configured to receive and weight the input signal to generate a weighted input signal, and wherein the second comparator is further configured to receive the weighted input signal and add the weighted input signal to a difference between the integrated first error signal and the second feedback signal to generate the second error signal.

Scheme 13. the apparatus of scheme 8, further comprising: a fourth weighting element configured to receive and weight the input signal to generate a weighted input signal, and wherein the third comparator is further configured to receive the weighted input signal and add the weighted input signal to a difference between the integrated second error signal and the third feedback signal to generate the second error signal.

Scheme 14. the apparatus of scheme 8, further comprising:

a fourth weighting element configured to receive the input signal and weight it to generate a first weighted input signal;

a fifth weighting element configured to receive the input signal and weight it to generate a second weighted input signal;

and wherein the one or more of the one,

the second comparator is further configured to receive the first weighted input signal and add the first weighted input signal to a difference between the integrated first error signal and the second feedback signal to generate the second error signal; and is

The third comparator is further configured to receive the second weighted input signal and add the second weighted input signal to a difference between the integrated second error signal and the third feedback signal to generate the third error signal.

Scheme 15. an apparatus comprising:

a third quantizer configured to receive the quantized modified output signal and generate a further quantized modified output signal;

a first weighting element configured to receive and weight the further quantized modified output signal to generate the first feedback signal;

a second weighting element configured to receive and weight the quantized modified output signal to generate the second feedback signal.

Scheme 16. the apparatus of scheme 15, wherein either or both of the second quantizer and the third quantizer comprise a flip-flop.

The apparatus of scheme 17. the apparatus of scheme 15, wherein either or both of the second quantizer and the third quantizer comprise a comparator and a flip-flop.

The apparatus of scheme 18. the apparatus of scheme 15, wherein one or more of the first integrator, the second integrator, and the third integrator are switched capacitor integrators.

The apparatus of aspect 15, further comprising: a fourth weighting element configured to receive and weight the input signal to generate a weighted input signal, and wherein the second comparator is further configured to receive the weighted input signal and add the weighted input signal to a difference between the integrated first error signal and the second feedback signal to generate the second error signal.

Scheme 20. the apparatus of scheme 15, further comprising: a fourth weighting element configured to receive and weight the input signal to generate a weighted input signal, and wherein the third comparator is further configured to receive the weighted input signal and add the weighted input signal to a difference between the integrated second error signal and the third feedback signal to generate the second error signal.

Scheme 21. the apparatus of scheme 15, further comprising:

and wherein the one or more of the one,

Claims

1. An apparatus, comprising:

a second comparator configured to receive the integrated error signal and a second feedback signal from the first integrator and generate a second error signal, the second error signal being a difference between the integrated first error signal and the second feedback signal;

2. The apparatus of claim 1, wherein the second quantizer comprises a flip-flop.

3. The apparatus of claim 1, wherein the second quantizer comprises a comparator and a flip-flop.

4. The method of claim 1, wherein the first integrator is a switched capacitor integrator.

5. The apparatus of claim 1, wherein the second integrator is a switched capacitor integrator.

6. The apparatus of claim 1, further comprising: a third weighting element configured to receive and weight the input signal to generate a weighted input signal, and wherein the second comparator is further configured to receive the weighted input signal and add the weighted input signal to a difference between the integrated first error signal and the second feedback signal to generate the second error signal.

7. The apparatus of claim 1, further comprising:

8. An apparatus, comprising:

a third comparator configured to receive the integrated error signal and a third feedback signal from the second integrator and generate a third error signal, the third error signal being a difference between the integrated second error signal and the third feedback signal;

9. The apparatus of claim 8, wherein the second quantizer comprises a flip-flop.

10. The apparatus of claim 8, wherein the second quantizer comprises a comparator and a flip-flop.

11. The apparatus of claim 8, wherein one or more of the first integrator, the second integrator, and the third integrator are switched capacitor integrators.

12. The apparatus of claim 8, further comprising: a fourth weighting element configured to receive and weight the input signal to generate a weighted input signal, and wherein the second comparator is further configured to receive the weighted input signal and add the weighted input signal to a difference between the integrated first error signal and the second feedback signal to generate the second error signal.

13. The apparatus of claim 8, further comprising: a fourth weighting element configured to receive and weight the input signal to generate a weighted input signal, and wherein the third comparator is further configured to receive the weighted input signal and add the weighted input signal to a difference between the integrated second error signal and the third feedback signal to generate the second error signal.

14. The apparatus of claim 8, further comprising:

and wherein the one or more of the one,

15. An apparatus, comprising:

16. The apparatus of claim 15, wherein either or both of the second quantizer and the third quantizer comprise a flip-flop.

17. The apparatus of claim 15, wherein either or both of the second quantizer and the third quantizer comprise a comparator and a flip-flop.

18. The apparatus of claim 5, wherein one or more of the first integrator, the second integrator, and the third integrator are switched capacitor integrators.

19. The apparatus of claim 15, further comprising: a fourth weighting element configured to receive and weight the input signal to generate a weighted input signal, and wherein the second comparator is further configured to receive the weighted input signal and add the weighted input signal to a difference between the integrated first error signal and the second feedback signal to generate the second error signal.

20. The apparatus of claim 15, further comprising: a fourth weighting element configured to receive and weight the input signal to generate a weighted input signal, and wherein the third comparator is further configured to receive the weighted input signal and add the weighted input signal to a difference between the integrated second error signal and the third feedback signal to generate the second error signal.

21. The apparatus of claim 15, further comprising:

and wherein the one or more of the one,