CN110661517A

CN110661517A - Starting-up circuit and terminal thereof

Info

Publication number: CN110661517A
Application number: CN201810688112.9A
Authority: CN
Inventors: 刘春辉; 宋建峰
Original assignee: ZTE Corp
Current assignee: ZTE Corp
Priority date: 2018-06-28
Filing date: 2018-06-28
Publication date: 2020-01-07
Anticipated expiration: 2038-06-28
Also published as: WO2020001479A1; CN110661517B

Abstract

The invention discloses a startup circuit and a terminal thereof, and belongs to the technical field of startup. The startup circuit comprises: the D trigger is used for identifying whether the terminal is in a G3 state or an S5 state currently, so that the nuclear power VNN is powered on automatically when the terminal is in a G3 state currently, or the nuclear power VNN is controlled to be powered on through a power-on timing control signal SLP _ S3 and a MOS (metal oxide semiconductor) tube when the terminal is in an S5 state currently; and the MOS tube is used for controlling the nuclear power VNN to be powered on according to the power-on timing control signal SLP _ S3 and the output level of the Q pin of the D trigger. According to the technical scheme, two different electrifying sequence requirements of the terminal of the Apollo Lake platform can be met through the D trigger and the MOS tube, and the Apollo Lake platform has the advantages of low cost, simple circuit and the like.

Description

Starting-up circuit and terminal thereof

Technical Field

The invention relates to the technical field of startup, in particular to a startup circuit and a terminal thereof.

Background

At present, for thin terminals designed based on the Intel Apollo Lake platform, the power-on sequence has the following requirements: 1. the terminal is changed from the G3 state to the power-on state; when the user unplugs the power adapter, the terminal enters the G3 state, and the power-on sequence of this case is: g3, power adapter insertion, terminal part circuit power-up, nuclear power VNN power-up, user pressing power button, CPU output SLP _ S3 high, terminal power-on. 2. The terminal is changed from the state of S5 to the power-on state; when the user performs a normal power-off (the user selects power-off through the terminal desktop menu) operation but does not unplug the power adapter, the terminal proceeds to the S5 state. The power up sequence for this case is: s5 (terminal part circuit is powered on) - > user presses start button- > CPU outputs SLP _ S3 high- > nuclear power VNN is powered on- > terminal starts.

Based on the above two requirements, there are two common methods in the industry: 1. a special power management chip is used, and the power management chip can only be used with the Apollo Lake platform, in other words, if another platform is used, another power management chip needs to be selected again. It is clear that this solution is too costly and not versatile. 2. And (3) designing a special logic program by using the CPLD to meet the special power-on sequence requirement of the Apollo Lake platform. However, the disadvantages of this solution are obvious, one is that the CPLD is expensive, and the other is that the logic program needs to be designed, and the complexity is increased.

Disclosure of Invention

The invention mainly aims to provide a starting-up circuit and a terminal thereof, aims to realize two different electrifying sequence requirements of the terminal of an Apollo Lake platform through a D trigger and an MOS tube, and has the advantages of low cost, simple circuit and the like.

In order to achieve the above object, the present invention provides a boot startup circuit, including: the D trigger is used for identifying whether the terminal is in a G3 state or an S5 state currently, so that the nuclear power VNN is powered on automatically when the terminal is in a G3 state currently, or the nuclear power VNN is controlled to be powered on through a power-on timing control signal SLP _ S3 and a MOS (metal oxide semiconductor) tube when the terminal is in an S5 state currently; and the MOS tube is used for controlling the nuclear power VNN to be powered on according to the power-on timing control signal SLP _ S3 and the output level of the Q pin of the D trigger.

In addition, in order to achieve the above object, the present invention further provides a terminal, where the terminal includes the above power-on start circuit.

The startup circuit comprises a D trigger and an MOS (metal oxide semiconductor) tube, wherein the D trigger is used for identifying whether the terminal is in a G3 state or an S5 state currently, so that the nuclear power VNN is powered on automatically when the terminal is in a G3 state currently, or the nuclear power VNN is controlled to be powered on through a power-on time sequence control signal SLP _ S3 and the MOS tube when the terminal is in an S5 state currently. The MOS transistor is used for controlling the power-on of the nuclear power VNN according to the power-on timing control signal SLP _ S3 and the output level of the Q pin of the D flip-flop. Therefore, the starting circuit and the terminal thereof can meet two different power-on sequence requirements of the terminal of the Apollo Lake platform through the D trigger and the MOS tube, and have the advantages of low cost, simple circuit and the like.

Drawings

Fig. 1 is a schematic circuit diagram of a power-on start-up circuit according to an embodiment of the present invention.

Fig. 2 is a schematic diagram of another circuit of the power-on circuit shown in fig. 1.

The implementation, functional features and advantages of the objects of the present invention will be further explained with reference to the accompanying drawings.

Detailed Description

It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

In the following description, suffixes such as "module", "component", or "unit" used to denote elements are used only for facilitating the explanation of the present invention, and have no specific meaning in itself. Thus, "module", "component" or "unit" may be used mixedly.

The following is an explanation of some terms appearing in the examples of the present invention:

(1) the G3 state refers to a state in which the terminal is completely unpowered, i.e., an external power adapter is not plugged into the terminal.

(2) The state of S5 means that the terminal portion circuit is powered, but the nuclear power VNN is not powered.

(3) The power-on state refers to a state in which the terminal is powered on and normal operation can be performed by a user.

(4) And normally shutting down means that a user performs shutdown operation through a desktop menu of the terminal.

(5) SLP _ S3 signal, Apollo Lake platform power-on timing control signal. This signal is sent by the CPU and is high at power-on and low at S5. When the terminal is switched from the S5 state to the power-on state, SLP _ S3 goes from low to high. When the terminal is switched from the power-on state to the S5 state, SLP _ S3 goes from high to low.

(6) The power supply is powered off in G3 and S5 states and powered on in a starting state, and mainly supplies power to a key circuit in the CPU.

(7) And the VNN _ ON network is a power-ON control signal of the nuclear power VNN, when the VNN _ ON is high, the nuclear power VNN is powered ON, and when the VNN _ ON is low, the nuclear power VNN is powered off.

Example one

As shown in fig. 1, an embodiment of the invention provides a power-on circuit, which includes a D flip-flop D1 and a MOS transistor VT 1. The D flip-flop D1 is mainly used to identify whether the terminal is currently in a G3 state or an S5 state, so that the nuclear VNN is powered on by itself when the terminal is currently in the G3 state, or the nuclear VNN is controlled to be powered on by a power-on timing control signal SLP _ S3 and a MOS transistor VT1 when the terminal is currently in the S5 state. The MOS transistor VT1 is used to control the power-on of the core VNN according to the power-on timing control signal SLP _ S3 and the output level of the Q pin of the D flip-flop.

In this embodiment, as shown in FIG. 1, the D flip-flop D1 includes a CLK pin, a D pin, a PRE^*Pin, CLR^*Pin and Q pin. The pin D is a preset end, the pin Q is an output end, and the pin CLK is a trigger edge. If the level of the CLK pin changes from low to high (rising edge), the level of the D pin is output to the Q pin (i.e., Q ═ D). If the level of the CLK pin is unchanged or goes from high to low (falling edge), the level of the Q pin remains unchanged and passes through the PRE^*Pin and CLR^*The input level of the pin sets the default output level of the Q pin. The specific setting method comprises the following steps: 1. when the D flip-flop D1 is powered up, if PRE is detected^*The input level of the pin is low, CLR^*The input level of the pin is high, and the output level of the Q pin is high. 2. If PRE^*The input level of the pin is high, CLR^*The input level of the pin is low, and the output level of the Q pin is low. 3. If PRE^*The input level to the pin is high,CLR^*the input level of the pin is also high, and the output level of the Q pin remains unchanged.

As shown in fig. 1, the D pin of the D flip-flop D1 is connected to a +3.3V power supply through a pull-up resistor R3. PRE of D flip-flop D1^*The pin is connected with a +3.3V power supply through a pull-up resistor R1 to realize PRE^*Setting of the input level of the pin. CLR of D flip-flop D1^*The pin realizes the CLR through an RC circuit^*The input level of the pin is set, the RC circuit comprises a capacitor C1 and a resistor R2, wherein the capacitor C1 is connected with the CLR^*A resistor R2 connected between the pin and the ground^*Pin and +3.3V power supply. When D flip-flop D1 is powered up, PRE^*The input level of the pin is set high by pull-up resistor R1, and CLR^*The pin is connected with an external RC circuit to cause CLR^*The input level to the pin is initially low and CLR completes as the charging of capacitor C1 completes^*The input level to the pin goes high and then remains high. Thus, when power up is complete, the CLR^*Input level of pin is low, PRE^*The input level of the pin is high so that the Q pin outputs a low level.

As shown in FIG. 1, the D flip-flop D1 further includes a CLK pin, Q^*A pin, a GND pin and a VCC pin, the CLK pin is connected to a power-on timing control signal SLP _ S3, Q^*The pin is vacant, and the VCC pin is connected with a +3.3V power supply. In this embodiment, the MOS transistor VT1 is an N-channel MOS transistor, a gate (G) pin of the N-channel MOS transistor is connected to a Q pin of the D-flip-flop D1, a drain (D) pin of the N-channel MOS transistor is connected to the power-ON timing control signal SLP _ S3, and a source (S) pin of the N-channel MOS transistor is connected to the VNN _ ON network unit 100. Specifically, the VNN _ ON network unit 100 includes a VNN _ ON terminal connected to the source (S) pin of the N-channel MOS transistor, the VNN _ ON terminal is connected to the +3.3V power source through a pull-up resistor R4, and the VNN _ ON terminal is connected to the ground terminal through a capacitor C3.

In operation, as shown in fig. 1, if the current terminal state is the G3 state, after the power adapter is plugged in, the power supply + V3.3_ S4 is powered on, the Q pin of the D1 flip-flop outputs a low level, the MOS transistor VT1 is an N-channel MOS transistor, and at this time, the gate (G) pin of the MOS transistor VT1 is a low level, and the drain (D) pin is also a low level, so the MOS transistor VT1 is turned off. The VNN _ ON terminal is pulled up to + V3.3_ S4 from resistor R4, which is high, so that the power VNN is powered up. After the user presses the power-on key, the CPU pulls up the power-on timing control signal SLP _ S3, and then the terminal is powered on. It should be noted that the power-on timing control signal SLP _ S3 is connected to the CLK pin of the D-flip-flop D1, so during the power-on process, the CLK pin of the D-flip-flop D1 changes from low to high, and then the state of the D-flip-flop D1 changes, so that the level of the Q pin is equal to the level of the D pin, that is, the Q pin outputs high level.

If the current terminal state is the S5 state, as described above, the S5 state is realized by the normal shutdown operation of the user, during the normal shutdown process, the CPU will pull down the power-on timing control signal SLP _ S3, and since the CLK pin of the D flip-flop D1 is valid at the rising edge, the Q pin of the D flip-flop D1 remains at the high level during the shutdown process. When the power-on timing control signal SLP _ S3 is pulled low by the CPU, the gate (G) pin of the MOS transistor VT1 is at a high level, the drain (D) pin is at a low level, and the voltage of the gate (G) pin is higher than the voltage of the drain (D) pin and is greater than 1V. Therefore, the MOS transistor VT1 is turned ON, and then the VNN _ ON access terminal is pulled low, so that the nuclear power VNN is powered down.

In the state of S5, the power-up timing control signal SLP _ S3 is low, the Q pin of the D flip-flop D1 outputs high level, the power supply + V3.3_ S4 is powered, the MOS transistor VT1 is turned on, and the core power VNN is unpowered. Therefore, in the state of S5, after the user presses the power key, the CPU will pull up the power-on timing control signal SLP _ S3, and the CLK pin of the D flip-flop D1 will go from low to high, but the Q pin remains high since the D pin continues to remain high. At this time, the gate (G) pin of the MOS transistor VT1 is at a high level, and the drain (D) pin is also at a high level, so the MOS transistor VT1 is turned off, the VNN _ ON connection terminal is changed to a high level by pulling up, the nuclear power VNN is powered ON, and the terminal is turned ON.

Therefore, the embodiment of the invention can realize two different power-on sequence requirements of the Apollo Lake platform by only adopting one D trigger D1 and one MOS tube with an N channel, and has the advantages of low cost, simple circuit and the like.

For those skilled in the art, the MOS transistor mentioned in the above embodiment may also be a P-channel MOS transistor, in this case, as shown in fig. 2, the MOS transistor VT2 is a P-channel MOS transistor, a gate (G) pin of the P-channel MOS transistor is connected to a Q pin of the D flip-flop D1, a drain (D) pin of the P-channel MOS transistor is connected to the power-ON timing control signal SLP _ S3, a source (S) pin of the P-channel MOS transistor is connected to the VNN _ ON network unit, and a VNN _ ON access terminal of the VNN _ ON network unit is connected to a source (S) pin of the P-channel MOS transistor.

Meanwhile, as shown in FIG. 2, the D pin of D1 of D flip-flop is grounded, and PRE of D1 of D flip-flop^*Pin and CLR^*External circuit switching of pins, i.e. CLR of D1 flip-flop^*The pin is connected with a +3.3V power supply through a pull-up resistor R1 to realize CLR^*Setting of the input level of the pin. PRE of D flip-flop D1^*Pin for realizing PRE through RC circuit^*The input level of the pin is set, the RC circuit comprises a capacitor C1 and a resistor R2, wherein the capacitor C1 is connected to PRE^*A resistor R2 connected between the pin and ground^*Pin and +3.3V power supply. When D flip-flop D1 is powered up, CLR^*The input level of the pin is set high by pull-up resistor R1, and PRE^*The pins are connected with an external RC circuit to cause PRE^*The input level to the pin is initially low, PRE following the completion of the charging of capacitor C1^*The input level to the pin goes high and then remains high. Thus, when power up is completed, PRE^*The input level of the pin is low, CLR^*The input level of the pin is high so that the Q pin outputs a high level.

In operation, as shown in fig. 1, if the current terminal state is the G3 state, after the power adapter is plugged in, the power supply + V3.3_ S4 is powered on, the Q pin of the D1 flip-flop outputs a high level, the MOS transistor VT2 is a P-channel MOS transistor, at this time, the gate (G) pin of the MOS transistor VT2 is at a high level, the source (S) pin is also at a high level, and therefore the MOS transistor VT2 is turned off. The VNN _ ON terminal is pulled up to + V3.3_ S4 from resistor R4, which is high, so that the power VNN is powered up. After the user presses the power-on key, the CPU pulls up the power-on timing control signal SLP _ S3, and then the terminal is powered on. It should be noted that the power-on timing control signal SLP _ S3 is connected to the CLK pin of the D-flip-flop D1, so during the power-on process, the CLK pin of the D-flip-flop D1 changes from low to high, and then the state of the D-flip-flop D1 changes over, so that the level of the Q pin is equal to the level of the D pin, that is, the Q pin outputs low.

If the current terminal state is the S5 state, as described above, the S5 state is realized by the normal shutdown operation of the user, during the normal shutdown process, the CPU will pull down the power-on timing control signal SLP _ S3, and since the CLK pin of the D flip-flop D1 is valid at the rising edge, the Q pin of the D flip-flop D1 remains at the low level during the shutdown process. When the power-on timing control signal SLP _ S3 is pulled low by the CPU, the gate (G) pin of the MOS transistor VT2 is at a low level, the source (S) pin is at a high level, and the voltage of the gate (G) pin is lower than the voltage of the source (S) pin and is greater than 1V. Therefore, the MOS transistor VT2 is turned ON, and then the VNN _ ON access terminal is pulled low, so that the nuclear power VNN is powered down.

In the state of S5, the power-up timing control signal SLP _ S3 is low, the Q pin of the D flip-flop D1 outputs a low level, the power supply + V3.3_ S4 is powered, the MOS transistor VT2 is turned on, and the core power VNN is unpowered. Therefore, in the state of S5, after the user presses the power key, the CPU will pull up the power-on timing control signal SLP _ S3, and the CLK pin of the D flip-flop D1 will go from low to high, but the Q pin will remain low since the D pin is kept low. At this time, the gate (G) pin of the MOS transistor VT2 is at a low level, and the source (S) pin is at a high level, so the MOS transistor VT2 is turned ON, and the power-up timing control signal SLP _ S3 is already pulled high, so the VNN _ ON terminal becomes a high level, the nuclear power VNN is powered up, and the terminal is turned ON.

Example two

As shown in fig. 1, a second embodiment of the present invention provides a terminal, which is mainly a thin client designed based on an Intel Apollo Lake platform, and may also be other terminals designed based on the Intel Apollo Lake platform and having the same power-on sequence requirement. The terminal comprises a power-on starting circuit shown in fig. 1, wherein the power-on starting circuit comprises a D flip-flop D1 and a MOS transistor VT 1. The D flip-flop D1 is mainly used to identify whether the terminal is currently in a G3 state or an S5 state, so that the nuclear VNN is powered on by itself when the terminal is currently in the G3 state, or the nuclear VNN is controlled to be powered on by a power-on timing control signal SLP _ S3 and a MOS transistor VT1 when the terminal is currently in the S5 state. The MOS transistor VT1 is used to control the power-on of the core VNN according to the power-on timing control signal SLP _ S3 and the output level of the Q pin of the D flip-flop.

In this embodiment, as shown in FIG. 1, the D flip-flop D1 includes a CLK pin, a D pin, a PRE^*Pin, CLR^*Pin and Q pin. The pin D is a preset end, the pin Q is an output end, and the pin CLK is a trigger edge. If the level of the CLK pin changes from low to high (rising edge), the level of the D pin is output to the Q pin (i.e., Q ═ D). If the level of the CLK pin is unchanged or goes from high to low (falling edge), the level of the Q pin remains unchanged and passes through the PRE^*Pin and CLR^*The input level of the pin sets the default output level of the Q pin. The specific setting method comprises the following steps: 1. when the D flip-flop D1 is powered up, if PRE is detected^*The input level of the pin is low, CLR^*The input level of the pin is high, and the output level of the Q pin is high. 2. If PRE^*The input level of the pin is high, CLR^*The input level of the pin is low, and the output level of the Q pin is low. 3. If PRE^*The input level of the pin is high, CLR^*The input level of the pin is also high, and the output level of the Q pin remains unchanged.

As shown in fig. 1, the D pin of the D flip-flop D1 is connected to a +3.3V power supply through a pull-up resistor R3. PRE of D flip-flop D1^*The pin is connected with a +3.3V power supply through a pull-up resistor R1 to realize PRE^*Setting of the input level of the pin. CLR of D flip-flop D1^*The pin realizes the CLR through an RC circuit^*The input level of the pin is set, the RC circuit comprises a capacitor C1 and a resistor R2, wherein the capacitor C1 is connected with the CLR^*A resistor R2 connected between the pin and the ground^*Pin and +3.3V power supply. When D flip-flop D1 is powered up, PRE^*The input level of the pin is set high by pull-up resistor R1And CLR^*The pin is connected with an external RC circuit to cause CLR^*The input level to the pin is initially low and CLR completes as the charging of capacitor C1 completes^*The input level to the pin goes high and then remains high. Thus, when power up is complete, the CLR^*Input level of pin is low, PRE^*The input level of the pin is high so that the Q pin outputs a low level.

Meanwhile, as shown in FIG. 2, the D pin of D1 of D flip-flop is grounded, and PRE of D1 of D flip-flop^*Pin and CLR^*External circuit switching of pins, i.e. CLR of D1 flip-flop^*The pin is connected to a +3.3V power supply through a pull-up resistor R1,to realize CLR^*Setting of the input level of the pin. PRE of D flip-flop D1^*Pin for realizing PRE through RC circuit^*The input level of the pin is set, the RC circuit comprises a capacitor C1 and a resistor R2, wherein the capacitor C1 is connected to PRE^*A resistor R2 connected between the pin and ground^*Pin and +3.3V power supply. When D flip-flop D1 is powered up, CLR^*The input level of the pin is set high by pull-up resistor R1, and PRE^*The pins are connected with an external RC circuit to cause PRE^*The input level to the pin is initially low, PRE following the completion of the charging of capacitor C1^*The input level to the pin goes high and then remains high. Thus, when power up is completed, PRE^*The input level of the pin is low, CLR^*The input level of the pin is high so that the Q pin outputs a high level.

The startup circuit comprises a D trigger and an MOS (metal oxide semiconductor), wherein the D trigger is used for identifying whether the terminal is in a G3 state or an S5 state currently, so that the nuclear power VNN is powered on automatically when the terminal is in a G3 state currently, or the nuclear power VNN is controlled to be powered on by a power-on time sequence control signal SLP _ S3 and the MOS when the terminal is in an S5 state currently. The MOS transistor is used for controlling the power-on of the nuclear power VNN according to the power-on timing control signal SLP _ S3 and the output level of the Q pin of the D flip-flop. Therefore, the starting circuit and the terminal thereof can meet two different power-on sequence requirements of the terminal of the Apollo Lake platform through the D trigger and the MOS tube, and have the advantages of low cost, simple circuit and the like.

It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.

The above-mentioned serial numbers of the embodiments of the present invention are merely for description and do not represent the merits of the embodiments.

Through the above description of the embodiments, those skilled in the art will clearly understand that the method of the above embodiments can be implemented by software plus a necessary general hardware platform, and certainly can also be implemented by hardware, but in many cases, the former is a better implementation manner. Based on such understanding, the technical solutions of the present invention may be embodied in the form of a software product, which is stored in a storage medium (such as ROM/RAM, magnetic disk, optical disk) and includes instructions for enabling a terminal device (such as a mobile phone, a computer, a server, an air conditioner, or a network device) to execute the method according to the embodiments of the present invention.

The above description is only a preferred embodiment of the present invention, and not intended to limit the scope of the present invention, and all modifications of equivalent structures and equivalent processes, which are made by using the contents of the present specification and the accompanying drawings, or directly or indirectly applied to other related technical fields, are included in the scope of the present invention.

Claims

1. A power-on circuit, comprising:

the D trigger is used for identifying whether the terminal is in a G3 state or an S5 state currently, so that the nuclear power VNN is powered on automatically when the terminal is in a G3 state currently, or the nuclear power VNN is controlled to be powered on through a power-on timing control signal SLP _ S3 and a MOS (metal oxide semiconductor) tube when the terminal is in an S5 state currently;

and the MOS tube is used for controlling the nuclear power VNN to be powered on according to the power-on timing control signal SLP _ S3 and the output level of the Q pin of the D trigger.

2. The power-on startup circuit of claim 1, wherein the D flip-flop comprises a CLK pin,D Pin, PRE^*Pin, CLR^*A pin and a Q pin; the D pin is a preset end, the Q pin is an output end, and the CLK pin is a trigger edge; if the level of the CLK pin is changed from low to high, the level of the D pin is output to the Q pin; if the level of the CLK pin is unchanged or changed from high to low, pass PRE^*Pin and CLR^*The input level of the pin sets the default output level of the Q pin.

3. The power-on startup circuit of claim 2 wherein when the D flip-flop is powered up, if PRE is completed^*The input level of the pin is low, CLR^*If the input level of the pin is high level, the output level of the Q pin is high level; if PRE^*The input level of the pin is high, CLR^*If the input level of the pin is low level, the output level of the Q pin is low level; if PRE^*The input level of the pin is high, CLR^*The input level of the pin is also high level, and the output level of the Q pin is kept unchanged.

4. The power-ON start-up circuit of claim 2, wherein the MOS transistor is an N-channel MOS transistor, a gate pin of the N-channel MOS transistor is connected to a Q pin of the D flip-flop, a drain pin of the N-channel MOS transistor is connected to the power-ON timing control signal SLP _ S3, and a source pin of the N-channel MOS transistor is connected to the VNN _ ON network unit.

5. The power-on startup circuit of claim 4, wherein the PRE is configured to be coupled to the power-on startup circuit^*The pin is connected with a +3.3V power supply through a pull-up resistor to realize the PRE^*Setting of input level of pin, CLR^*The CLR is realized by a pin through an RC circuit^*And the input level of the pin is set, and the RC circuit comprises a capacitor and a resistor.

6. The power-ON start-up circuit of claim 2, wherein the MOS transistor is a P-channel MOS transistor, a gate pin of the P-channel MOS transistor is connected to a Q pin of the D flip-flop, a drain pin of the P-channel MOS transistor is connected to the power-ON timing control signal SLP _ S3, and a source pin of the P-channel MOS transistor is connected to the VNN _ ON network unit.

7. The power-on startup circuit of claim 6 wherein the CLR^*The pin is connected with a +3.3V power supply through a pull-up resistor to realize the CLR^*Setting of input level of pin, PRE^*Pin implementation of the PRE through an RC circuit^*And the input level of the pin is set, and the RC circuit comprises a capacitor and a resistor.

8. The power-on start circuit of claim 2, wherein the D flip-flop further comprises a CLK pin, Q^*A pin, a GND pin and a VCC pin, the CLK pin is connected to the power-on timing control signal SLP _ S3, the Q^*The pin is vacant, and the VCC pin is connected with a +3.3V power supply.

9. A power-ON startup circuit as claimed in claim 4 or 6, wherein the VNN _ ON network unit comprises a VNN _ ON access terminal, the VNN _ ON access terminal is connected to the source terminal of the N-channel MOS transistor or the P-channel MOS transistor, the VNN _ ON access terminal is connected to a +3.3V power supply through a pull-up resistor, and the VNN _ ON access terminal is connected to a ground terminal through a capacitor.

10. A terminal, characterized in that it comprises a power-on startup circuit according to any of claims 1-9.