CN110660726A

CN110660726A - Semiconductor device and method of forming the same

Info

Publication number: CN110660726A
Application number: CN201910243387.6A
Authority: CN
Inventors: 陈靖怡; 卢炜业; 陈泓旭; 张志维
Original assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Current assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority date: 2018-06-29
Filing date: 2019-03-28
Publication date: 2020-01-07
Anticipated expiration: 2039-03-28
Also published as: CN110660726B

Abstract

The present disclosure relates to semiconductor devices and methods of forming the same. A nitrogen plasma treatment is used on the adhesion layer of the contact plug, with the result that nitrogen is incorporated into the adhesion layer. When the contact plug is deposited in the opening, a metal nitride intermediate layer is formed between the contact plug and the adhesion layer. A nitrogen plasma treatment is used on the opening in the insulating layer, with the result that nitrogen is incorporated into the insulating layer at the opening. When the contact plug is deposited in the opening, a metal nitride intermediate layer is formed between the contact plug and the insulating layer.

Description

Semiconductor device and method of forming the same

Technical Field

Embodiments of the present invention relate generally to semiconductor manufacturing technology, and more particularly, to a method for increasing adhesion of a conductive plug of a semiconductor device and a semiconductor device formed thereby.

Background

Semiconductor devices are used in various electronic applications such as personal computers, cellular phones, digital cameras, and other electronic devices. Semiconductor devices are typically fabricated by sequentially depositing layers of insulating or dielectric materials, conductive materials, and semiconductor materials on a semiconductor substrate, and patterning the various material layers using photolithographic techniques to form circuit components and elements on the semiconductor substrate.

The semiconductor industry continues to improve the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continuing to shrink the minimum feature size, which allows more components to be integrated into a given area. However, as the minimum feature size shrinks, other problems arise that need to be overcome.

Disclosure of Invention

According to some embodiments, a method of forming a semiconductor device is provided. The method includes forming an opening in an insulating layer of a structure and depositing an adhesion layer in the opening. The method also includes incorporating nitrogen atoms into the adhesion layer, and depositing a metal into the opening, the metal forming an intermediate layer between the metal plug and the adhesion layer, the intermediate layer comprising a compound of metal and nitrogen.

According to some embodiments, a method of forming a semiconductor device is provided. The method includes forming an opening in an insulating layer, the opening having sidewalls and a bottom, and treating the sidewalls and the bottom of the opening with a nitrogen-based plasma process that incorporates free nitrogen atoms into the sidewalls and the bottom of the opening. The method also includes forming a metal plug in the opening, the metal plug comprising a metal that bonds with free nitrogen atoms to form an intermediate layer between the metal plug and the sidewalls and bottom of the opening.

According to some embodiments, a semiconductor device is provided. The semiconductor device includes a target region, and an insulating layer over the target region. The semiconductor device further includes a metal plug disposed within the insulating layer, the metal plug extending from a top of the insulating layer to the target region, the metal plug comprising a first material. The semiconductor device also includes an intermediate layer disposed between the metal plug and the insulating layer, the intermediate layer including a compound of the first material and nitrogen, the intermediate layer being surrounded by free nitrogen atoms.

Drawings

In order that the embodiments of the invention may be more readily understood, reference should now be made to the following detailed description taken in conjunction with the accompanying drawings. It should be noted that, according to industry standard practice, various components are not necessarily drawn to scale. In fact, the dimensions of the various elements may be arbitrarily expanded or reduced for clarity of discussion.

Fig. 1 is a three-dimensional schematic diagram of an example of a fin field effect transistor (FinFET).

Fig. 2A-23C illustrate various intermediate stages of a process of forming a finfet, according to some embodiments.

Fig. 24 is a graph illustrating the wetting state of some exemplary materials being treated, and illustrating in percentage dewetting by the process of some embodiments versus dewetting when the process of embodiments is not in use, according to some embodiments.

Fig. 25-32 illustrate various intermediate stages of forming a metal on an insulating layer, according to some embodiments.

Fig. 33 is a graph illustrating material properties of a contact according to some embodiments.

Description of reference numerals:

30-fin field effect transistors (finfets);

50-substrate;

52-semiconductor strips;

54-an isolation region;

56-fins;

53. 62, 72-shade;

53A, 62A-a first mask layer;

53B, 62B-a second mask layer;

55-groove;

H₀-a height;

W₀-a width;

58-virtual dielectric layer;

60-dummy gate layer;

70-virtual grid electrode;

75-lightly doped source/drain (LDD) regions;

80-gate spacer layer;

80A to a first gate spacer layer;

80B to a second gate spacer layer;

80C to a third gate spacer layer;

82-source/drain regions;

83-silicide;

87-etching stop layer;

88. 96-interlayer dielectric (ILD);

90-groove;

92-gate dielectric;

94-gate electrode;

100-area;

102. 104-contact opening;

106. 107, 430, 440-metal layers;

108-metal nitride layer;

110. 330, 420-plasma treatment process;

112-nitrogen-rich metal nitride layer;

113. 345, 435 thin film intermediate layers;

114. 340-contact plug;

116. 118, 320, 350-contact;

122-a spacer;

124-sinking;

D₁-depth;

205. 210, 215, 220-elements;

300. 400-film stacking;

310. 315, 410 to film layer;

325-opening;

335. 425 processing areas;

225. 230, 235, 240-line;

245. 250, 255-band.

Detailed Description

The following provides many different embodiments or examples to implement different features (features) of embodiments of the invention. Specific examples of components and arrangements are described below to simplify the present embodiments. These are, of course, merely examples and are not intended to limit embodiments of the invention. For example, reference in the following description to the formation of a first feature over or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features are formed between the first and second features, such that the first and second features may not be in direct contact. In addition, embodiments of the present invention may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Additionally, spatially relative terms, such as "below …," "below …," "lower," "above …," "above," "higher," and the like, may be used herein for ease of describing the relationship of one element or component to another element or component as illustrated in the figures. These spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be oriented in other directions (rotated 90 degrees or at other orientations) and the spatially relative descriptors used in the description may be interpreted accordingly.

Some embodiments are described in detail herein that relate to a particular context of fin field effect transistor (FinFET) devices and methods of forming the same. Embodiments may form a conductive plug and provide increased adhesion between the conductive plug and its surrounding and underlying materials. However, those skilled in the art will appreciate that the techniques described in detail below with respect to fin field effect transistor (FinFET) devices may also be applied in other contexts.

Discussion of embodiments in the context of fin field effect transistors (finfets) is not intended to limit application of these techniques in any way. The formation of the finfets discussed herein, including the source/drain regions, gate structures and channel regions of the finfets, is exemplary and these processes may be varied within the contemplation of the embodiments discussed.

Devices formed on semiconductor substrates are sometimes provided with electrical connections through metal plugs or contacts disposed in dielectric or semiconductor layers, such as interlayer dielectric (ILD) or similar materials. As the size of devices shrinks, the allowable contact size decreases. An adhesive layer is sometimes used between the contact plug and the contact target area to increase the adhesion between the contact plug and the contact target area, which results in reduced electrical resistance and reduced leakage problems. Interfacial bonding is important for reliable microelectronic and nanoelectronic devices.

In a typical contact formation process, a TiN adhesion layer may be used in the contact opening. When the deposition technique of TiN layers as adhesion layers (also called glue layers) for Ti and/or Co contact plugs produces crystalline films, such as with Atomic Layer Deposition (ALD), good adhesion performance is shown due to its high crystalline TiN (111) orientation. Subsequently formed Ti and/or Co contact plugs may be deposited by, for example, Physical Vapor Deposition (PVD).

As dimensions shrink and other deposition processes are employed, for example, some deposition techniques such as Chemical Vapor Deposition (CVD) type processes produce amorphous films, TiN or Ti layers may suffer from poor adhesion. However, it may still be technically considered to use CVD deposition techniques, thereby providing a high selectivity for deposition on the underlying material.

The processes of the embodiments described herein use plasma treatment on the adhesion layer to provide improved adhesion of the adhesion layer. Performing nitrogen gas (N) on the adhesive layer₂/H₂) Plasma treatment, nitrogen (N)₂/H₂) Nitrogen is incorporated as a result of the plasma treatmentInto the treated adhesive layer, which increases the adhesion of the subsequently formed contact plug. When the metal plug is deposited on the adhesion layer, an ultra-thin MxN layer (nitride of metal M) is formed at the interface of the metal plug and the adhesion layer by the combination of available nitrogen in the treated material and metal M. Details of this process are described below with reference to various embodiments.

Since there is only a small lattice mismatch between a face centered cubic (fcc) structure of a metal nitride (MxN) (e.g., a crystal structure in which M is Co, cox n) and a face centered cubic (fcc) structure of a metal M (e.g., a crystal structure of a Co plug), the metal nitride (MxN) material has strong adhesion to metals.

This N is₂/H₂The plasma treatment can also be applied directly to the SiO or SiN substrate, thereby allowing direct attachment without the need for an adhesion layer. In other words, nitrogen plasma treatment can be used for a glue-layer-free process, and gap filling of contacts (e.g., Co contacts) does not require additional film deposition.

Fig. 1 shows an example illustrating a fin field effect transistor (FinFET)30 in a three-dimensional schematic view, the fin field effect transistor (FinFET)30 may be similar to the FinFET (some components omitted) formed in the region 100 shown in fig. 23A, 23B and 23C. Finfet 30 includes a fin 56 on substrate 50, fin 56 extending from a base (also referred to as a semiconductor strip) 52 thereof, wherein fin 56 or a portion of fin 56 may be formed from substrate 50. Substrate 50 includes isolation regions 54 and fins 56 protrude above isolation regions 54 from between adjacent isolation regions 54. Gate dielectric 92 is along the sidewalls of fin 56 and over the top surface of fin 56, and gate electrode 94 is over gate dielectric 92. Source/drain regions 82 are disposed on opposite sides of fin 56 relative to gate dielectric 92 and gate electrode 94. Fig. 1 also shows a reference cross-section used in subsequent figures, section a-a spanning the channel, gate dielectric 92 and gate electrode 94 of finfet 30; section C-C is in a plane parallel to section A-A and spans fin 56 outside the channel; cross-section BB is perpendicular to cross-section AA, along the longitudinal axis of fin 56, and in the direction of current flow between, for example, source/drain regions 82. For clarity, the subsequent figures refer to these reference profiles.

Fig. 2A-23C are cross-sectional schematic diagrams of intermediate stages in fabricating a fin field effect transistor (FinFET), according to some embodiments. In fig. 2A to 23A-23C, the figures ending with the "a" mark are shown along the reference section a-a shown in fig. 1; the figures ending with the "B" mark are shown along the reference section B-B shown in FIG. 1; and the figures ending with the "C" mark are shown along the reference section C-C shown in fig. 1. In some cases, the cross-sectional views in certain steps are omitted, for example, if the omitted cross-section is not specifically discussed.

Fig. 2A illustrates a substrate 50, where the substrate 50 may be a semiconductor substrate, such as a bulk semiconductor (bulk) substrate, a semiconductor-on-insulator (SOI) substrate, or the like, and the substrate 50 may be doped (e.g., with p-type or n-type dopants) or undoped. The substrate 50 may be a wafer, such as a silicon wafer. Typically, SOI substrates comprise a layer of semiconductor material formed on an insulator layer. The insulator layer may be, for example, a Buried Oxide (BOX) layer, a silicon oxide layer, or the like. The insulator layer is disposed on a substrate, typically a silicon or glass substrate. Other substrates, such as multilayer or gradient substrates, may also be used. In some embodiments, the semiconductor material of the substrate 50 may comprise silicon; germanium; a compound semiconductor comprising silicon carbide, gallium arsenide, gallium phosphide, indium arsenide, and/or indium antimonide; an alloy semiconductor comprising SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and/or GaInAsP; or a combination of the foregoing.

Substrate 50 may also include integrated circuit devices (not shown), and it will be understood by those skilled in the art that various integrated circuit devices, such as transistors, diodes, capacitors, resistors, similar devices, or combinations of the foregoing, may be formed in and/or on substrate 50 to produce the structural and functional requirements desired for the design of a fin field effect transistor (FinFET), and that any suitable method may be used to form the integrated circuit devices.

In some embodiments, the substrate 50 may include a plurality of regions, such as region 100. Some regions may be used to form n-type devices, such as n-type metal oxide semiconductor (NMOS) transistors, such as n-type fin field effect transistors (FinFETs). Other regions may be used to form p-type devices, such as p-type metal oxide semiconductor (PMOS) transistors, such as p-type FinFETs. Thus, region 100 may be an NMOS or PMOS region. The steps described herein may be used to mask the PMOS region, for example, when forming the NMOS region, and then remove the mask; the NMOS region is masked and then the PMOS region is formed. Alternatively, the PMOS region may be formed first, followed by the NMOS region, although other types of transistors, or other active or passive devices are contemplated.

Fig. 2A shows a mask 53 formed over the substrate 50, the mask 53 being used in a subsequent etching step to pattern the substrate 50 (see fig. 3A). In some embodiments, the mask 53 may include a first mask layer 53A and a second mask layer 53B. The first mask layer 53A may be a hard mask layer. In some embodiments, the first masking layer 53A may comprise silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, combinations thereof, or the like, and may be formed using any suitable process, such as Atomic Layer Deposition (ALD), Physical Vapor Deposition (PVD), Chemical Vapor Deposition (CVD), combinations thereof, or the like. The first masking layer 53A may be used to prevent or minimize etching of the substrate 50 underlying the first masking layer 53A during subsequent etching steps (see fig. 3A). The second masking layer 53B may comprise photoresist and, in some embodiments, may be used to pattern the first masking layer 53A for the subsequent etching steps discussed above. The second mask layer 53B may be formed by using a spin coating technique, and may be patterned using an appropriate photolithography technique. In some embodiments, mask 53 may comprise three or more mask layers.

Fig. 3A illustrates the formation of a semiconductor strip 52 in a substrate 50. First, the mask layers 53A and 53B may be patterned, and openings in the mask layers 53A and 53B expose areas of the substrate 50 where the trenches 55 are to be formed. Next, an etching process may be performed, the etching processTrenches 55 are created in the substrate 50 through the openings in the mask 53, forming a plurality of semiconductor strips 52 in the remaining portion of the substrate 50 under the patterned mask 53. The etching may be performed by any suitable etching process, such as Reactive Ion Etching (RIE), Neutral Beam Etching (NBE), similar processes, or combinations thereof, which may be anisotropic. In some embodiments, the semiconductor strips 52 may have a height H between about 50nm and about 60nm₀And a width W between about 6nm and about 8nm₀。

Fig. 4A illustrates the formation of an insulating material within trenches 55 (see fig. 3A) between adjacent semiconductor strips 52 to form isolation regions 54. The insulating material may be an oxide, such as silicon oxide; nitrides, such as silicon nitride; like materials or combinations of the foregoing, and may be formed by high density plasma chemical vapor deposition (HDP-CVD), Flowable Chemical Vapor Deposition (FCVD) (e.g., CVD-based material deposition in a remote plasma system and post-cure to convert it to another material, such as an oxide), like processes, or combinations of the foregoing, although other insulating materials formed by any suitable process may be used.

Furthermore, in some embodiments, the isolation region 54 may include a liner (not shown) formed on the sidewalls and bottom surface of the trench 55 (see fig. 3A) prior to filling the trench 55 with the insulating material of the isolation region 54. In some embodiments, the liner layer may comprise a semiconductor (e.g., silicon) nitride, a semiconductor (e.g., silicon) oxide, a thermal oxide of a semiconductor (e.g., silicon), a semiconductor (e.g., silicon) oxynitride, a polymer dielectric, a combination of the foregoing, or the like. The formation of the liner layer may comprise any suitable method, such as ALD, CVD, HDP-CVD, PVD, combinations of the foregoing, or the like.

Still referring to fig. 4A, a planarization process, such as Chemical Mechanical Polishing (CMP), may remove any excess insulating material of the isolation regions 54 such that the top surfaces of the isolation regions 54 and the top surfaces of the semiconductor strips 52 are coplanar (within process variations). In some embodiments, Chemical Mechanical Polishing (CMP) may also remove the mask 53. In other embodiments, a wet clean process separate from chemical mechanical polishing may be used to remove the mask 53.

Fig. 5A illustrates the recessing of the isolation regions 54 to form Shallow Trench Isolation (STI) regions. Isolation regions 54 are recessed such that fins 56 protrude between adjacent isolation regions 54 (which are separated by semiconductor strips 52). Further, the top surface of isolation region 54 may have a flat surface as shown, a convex surface, a concave surface (e.g., a dish), or a combination of the foregoing, and the top surface of isolation region 54 may be formed flat, convex, and/or concave by suitable etching. The isolation regions 54 may be recessed using a suitable etch process, such as an etch process that is selective to the material of the isolation regions 54.

The process described above with respect to fig. 2A-5A is but one example of how fin 56 may be formed. Embodiments include other suitable processes for forming fin 56 including, for example, epitaxially growing a homoepitaxial or heteroepitaxial structure within a recess formed in a mask over substrate 50.

In fig. 6A and 6B, a dummy (dummy) dielectric layer 58 is formed over fin 56. The dummy dielectric layer 58 may be, for example, silicon oxide, silicon nitride, combinations thereof or the like, and may be deposited (using, for example, CVD, PVD, combinations thereof or the like) or thermally grown (using, for example, thermal oxidation or the like) according to a suitable technique. A dummy gate layer 60 is formed over dummy dielectric layer 58 and a mask 62 is formed over dummy gate layer 60. In some embodiments, dummy gate layer 60 may be deposited over dummy dielectric layer 58 and then planarized, for example using a CMP process. Mask 62 may be deposited over dummy gate layer 60. Dummy gate layer 60 may be made of, for example, polysilicon, but other materials having a high etch selectivity to the material of isolation region 54 may also be used. Mask 62 may comprise one or more layers such as silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, the like, or combinations thereof. In one embodiment, mask 62 comprises a first masking layer 62A formed of silicon nitride and a second masking layer 62B formed of silicon oxide. In some embodiments, the first masking layer 62A may have a thickness between about 18nm and about 22nm, and the second masking layer 62B may have a thickness between about 50nm and about 90 nm. In some embodiments, dummy dielectric layer 58 may have a thickness between about 11nm and about 15nm, and dummy gate layer 60 may have a thickness between about 50nm and about 80nm, although other dimensions are contemplated and used. In some embodiments, dummy dielectric layer 58 may be omitted.

Still referring to fig. 6A and 6B, an appropriate doped well region (not shown) may be formed in fin 56, semiconductor strip 52, and/or substrate 50. The well region may be formed before or after the dummy gate 70 is formed (described below with reference to fig. 7A, 7B, and 7C). In some embodiments, a well region is formed prior to forming dummy gate 70, for example, a well region may be formed prior to forming dummy dielectric layer 58. For example, a P-well region (for NMOS devices) or an N-well region (for PMOS devices) may be formed. Suitable impurities may be used, for example n-type impurities corresponding to phosphorus, arsenic or the like, and also boron, BF₂Or p-type impurities like impurities, the well regions (if any) are formed by masking and implantation techniques. After implantation of the appropriate impurities, an anneal may be performed to activate the implanted p-type and/or n-type impurities. In some embodiments, the material of fin 56 may be doped in-situ during the deposition process.

In fig. 7A, 7B and 7C, mask 62 (see fig. 6A and 6B) may be patterned using suitable photolithography and etching techniques to form mask 72 in region 100. The mask 72 may then be patterned by a suitable etching technique to the dummy gate layer 60 to form the dummy gate 70. Alternatively, the pattern of mask 72 may be similarly transferred to dummy dielectric layer 58. The dummy gate 70 is patterned to cover the respective channel regions of fin 56 and expose the source/drain regions of fin 56. The length direction of dummy gate 70 may be substantially perpendicular to the length direction of each fin 56. The size of the dummy gates 70 and the spacing between the dummy gates 70 may depend on the die (die) area in which the dummy gates 70 are formed, and in some embodiments, when located in the input/output area of the die (e.g., setting input/output circuitry), the dummy gates 70 may have a larger size and a larger spacing than when located in the logic area of the die (e.g., setting logic circuitry). In some embodiments, dummy gate 70 may have a height between about 135nm and about 175nm, and dummy gate 70 may have a width between about 15nm and about 27nm, although other dimensions for dummy gate 70 are also contemplated and used. Further, although two dummy gates 70 are shown, these are merely exemplary and more or fewer dummy gates may be used in region 100.

In fig. 8A, 8B, and 8C, a gate spacer layer 80 is formed on the exposed surface of dummy gate 70 (see fig. 8A and 8B) and/or on fin 56 (see fig. 8C). The gate spacer layer 80 may be formed using any suitable method, and in some embodiments, the gate spacer layer 80 may be formed using deposition (e.g., CVD, ALD, or the like). In some embodiments, the gate spacer layer 80 may comprise one or more layers, such as silicon nitride (SiN), silicon oxynitride, silicon carbonitride, silicon oxycarbonitride (SiOCN), combinations thereof, or the like. In some embodiments, the gate spacer layer 80 may include a first gate spacer layer 80A, a second gate spacer layer 80B over the first gate spacer layer 80A, and a third gate spacer layer 80C over the second gate spacer layer 80B.

Still referring to fig. 8A, 8B and 8C, after forming the first spacer layer 80A, lightly doped source/drain (LDD) regions 75 may be formed in the region 100 by masking and implantation techniques using processes and materials similar to those described above with respect to fig. 6A and 6B. The resulting LDD region 75 may have a thickness of about 10a¹⁵cm^-3To about 10¹⁶cm^-3And an annealing process may be performed to activate the implanted impurities.

Referring to fig. 9A, 9B, and 9C, an etching process is performed to remove portions of the spacer layer 80. In some embodiments, a mask may be used to protect portions of the spacer layer 80 from the etching process. The etching process may be anisotropic, and after the etching process is performed, lateral portions of the first spacer layer 80A, the second spacer layer 80B, and the third spacer layer 80C over the lightly doped source/drain (LDD) regions 75 and over the isolation regions 54 may be removed to expose the top surface of the fin 56 and the mask 72 for the dummy gate 70. A portion of first spacer layer 80A, second spacer layer 80B, and third spacer layer 80C along the sidewalls of dummy gate 70 and fin 56 may remain and form spacers 122. In some embodiments, spacer layer 80 may also be removed from the sidewalls of fin 56.

Fig. 10A, 10B, 10C, 11A, 11B, and 11C illustrate the formation of epitaxial source/drain regions 82 in region 100, as described in more detail below in subsequent steps. N may be used₂/H₂A plasma treatment process to improve the adhesion of the contacts to the epitaxial source/drain regions 82. Referring to fig. 10A, 10B, and 10C, a patterning process is performed on fin 56 to form recesses 124 in the source/drain regions of fin 56 (and semiconductor strips 52 in some embodiments). The patterning process may be performed in such a manner that a recess 124 is formed between adjacent dummy gates 70, or between one end of fin 56 and dummy gate 70. In some embodiments, the patterning process may include an etching process and use the dummy gate 70, spacers 122, and/or isolation regions 54 as a combinatorial mask. The etching process may be, for example, an anisotropic dry etching process such as Reactive Ion Etching (RIE), Neutral Beam Etching (NBE), the like, or combinations of the foregoing. In some embodiments, inclusion of CH may be used₃F、CH₄、HBr、O₂Ar, combinations thereof or the like to perform an anisotropic etch process. In some embodiments, recess 124 has a depth D measured from the top surface of fin 56₁Between about 45nm and about 65nm, although other dimensions are contemplated and used.

Fig. 11A, 11B and 11C illustrate the formation of epitaxial source/drain regions 82 in recesses 124 of region 100. In some embodiments, the epitaxial source/drain regions 82 are epitaxially grown using metal-organic chemical vapor deposition (MOCVD) epitaxial growth, Molecular Beam Epitaxy (MBE), Liquid Phase Epitaxy (LPE), Vapor Phase Epitaxy (VPE), Selective Epitaxial Growth (SEG), combinations thereof, or the like. Epitaxial source/drain regions 82 may comprise any suitable material, such as any material suitable for an n-type FinFET or a p-type FinFET, depending on the type of FinFET formed. For example, if fin 56 is silicon, epitaxial source/drain regions 82 may comprise silicon, SiC, SiCP, SiP, or the like for an n-type FinFET, or SiGe, SiGeB, Ge, GeSn, or the like for a p-type FinFET. Epitaxial source/drain regions 82 may have surfaces that are raised from respective surfaces of fins 56 and may have facets (facets). Epitaxial source/drain regions 82 are formed in fin 56 such that each dummy gate 70 is disposed between a respective pair of adjacent epitaxial source/drain regions 82. In some embodiments, epitaxial source/drain regions 82 may extend beyond fins 56 and into semiconductor strips 52, as shown in fig. 11B.

Dopants similar to those previously described for forming lightly doped source/drain (LDD) regions 75 may be implanted into the material of epitaxial source/drain regions 82 followed by an anneal (see fig. 8A, 8B, and 8C and their associated description). The impurity concentration of epitaxial source/drain regions 82 may be about 10¹⁹cm^-3To about 10²¹cm^-3The impurities for epitaxial source/drain regions 82 may be any of the n-type dopant impurities or p-type dopant impurities discussed previously, depending on the transistor type. In other embodiments, the material of epitaxial source/drain regions 82 may be doped in situ during growth. In the illustrated embodiment, each source/drain region 82 is physically separated from the other source/drain regions 82. In other embodiments, two or more adjacent source/drain regions 82 may be merged. In some embodiments, two or more than three adjacent source/drain regions 82 may be merged.

Fig. 12A-15C illustrate the replacement of dummy gate 70 with a replacement gate structure including a replacement gate electrode, which may be used as N, described in more detail below in subsequent steps₂/H₂And (3) a plasma treatment process to improve the adhesion of the contact to the replacement gate electrode. In thatIn some embodiments, the replacement gate structure may be a metal gate, such as described below. As described above, although a gate-last process is shown and discussed, those skilled in the art will appreciate that a gate-first process may also be used.

Referring to fig. 12A, 12B and 12C, an etch stop layer 87 and an interlayer dielectric (ILD)88 are deposited over the dummy gate 70 and over the source/drain regions 82. In one embodiment, interlayer dielectric (ILD)88 is a flowable film formed by flowable CVD. In some embodiments, interlayer dielectric (ILD)88 is formed of a dielectric material, such as Phospho-Silicate Glass (PSG), borosilicate Glass (Boro-Silicate Glass, BSG), Boron-Doped Phospho-Silicate Glass (BPSG), Undoped Silicate Glass (USG), or the like, and may be deposited by any suitable method, such as CVD, PECVD, a combination of the foregoing, or the like. In some embodiments, the etch stop layer 87 serves as a stop layer when the patterned interlayer dielectric (ILD)88 is opened for subsequently formed contacts. Accordingly, the material for etch stop layer 87 may be selected such that the material of etch stop layer 87 has a lower etch rate than the material of interlayer dielectric (ILD) 88.

Referring to fig. 13A, 13B and 13C, a planarization process, such as Chemical Mechanical Polishing (CMP), may be performed such that the top surface of the interlayer dielectric (ILD)88 is flush with the top surface of the dummy gate 70. After the planarization process, the top surface of the dummy gate 70 is exposed through an interlayer dielectric (ILD) 88. In some embodiments, Chemical Mechanical Polishing (CMP) may also remove the mask 72 or a portion of the mask 72 over the dummy gate 70.

Referring to fig. 14A, 14B and 14C, the mask 72 and the remaining portion of the dummy gate 70 are removed in an etching step, so that a recess 90 is formed. Each recess 90 exposes the channel region of a respective fin 56. Each channel region is disposed between an adjacent pair of epitaxial source/drain regions 82 in region 100. In some embodiments, dummy dielectric layer 58 may be used as an etch stop during removal, and dummy dielectric layer 58 is exposed when dummy gate 70 is etched. The exposed dummy dielectric layer 58 may then be removed after removing the dummy gate 70. In some embodiments, the portion of the dummy dielectric layer 58 not exposed by the dummy gate 70 removal process may remain, as shown in fig. 14B.

Referring to fig. 15A, 15B and 15C, a gate dielectric layer 92 and a gate electrode 94 are formed as a replacement gate. A gate dielectric layer 92 is formed in recess 90, for example on the top surface and sidewalls of fin 56, on the inner sidewalls of gate spacer 122 (spacer 80A), and on the top surface of interlayer dielectric (ILD) 88. In some embodiments, the deposited gate dielectric layer 92 is a blanket deposition layer. In some embodiments, gate dielectric layer 92 comprises silicon oxide, silicon nitride, or multiple layers of the foregoing. In other embodiments, the gate dielectric layer 92 comprises a high dielectric constant (k) dielectric material, and in such embodiments, the gate dielectric layer 92 may have a k value greater than about 7.0, and may comprise a metal oxide or silicate of Hf, Al, Zr, La, Mg, Ba, Ti, Pb, and combinations thereof. The gate dielectric layer 92 may be formed by Molecular-beam deposition (MBD), ALD, CVD, PECVD, combinations thereof, or the like. In some embodiments, the above formation may result in a conformal deposition layer having a horizontal portion and a vertical (or non-horizontal) portion with substantially the same thickness, e.g., the vertical thickness of the vertical portion of the gate dielectric layer 92 differs from the horizontal thickness of the horizontal portion of the gate dielectric layer 92 by less than 20%. In some embodiments, the gate dielectric 92 may be thermally grown, such as with reference to the dummy dielectric 58 described above.

Next, a material for gate electrode 94 is deposited on respective gate dielectric layers 92 and fills the remaining portions of recess 90. The gate electrode 94 may be made of a metal-containing material such as TiN, TaN, TaC, TiC, TiO, Co, Ru, Al, Ag, Au, W, Ni, Ti, Cu, combinations thereof, or multilayers thereof. After filling gate electrode 94, a planarization process, such as CMP, may be performed to remove excess portions of gate dielectric layer 92 and gate electrode 94 over the top surface of interlayer dielectric (ILD) 88. Thus, the remaining portions of the material of gate electrode 94 and gate dielectric layer 92 form the replacement gate of the FinFET.

Although not shown, the gate electrode 94 may comprise a series of one or more stacked layers (not shown). Stacked layers may be deposited in the recess 90 over the sidewalls and bottom of the gate dielectric layer 92 and over the top surface of the interlayer dielectric (ILD) 88. The stacked layers may be formed by a blanket deposition method, such as ALD or CVD, and have a thickness that is substantially uniform over process variations. In some embodiments, the formation of the gate electrode 94 may result in a conformal deposited layer having a horizontal portion and a vertical (or non-horizontal) portion of substantially the same thickness, e.g., the vertical thickness of the vertical portion and the horizontal thickness of the horizontal portion of the layers differ by less than 20%. The stack of layers may include a diffusion barrier layer, and one or more work function layers over the diffusion barrier layer. The diffusion barrier layer may be formed of titanium nitride (TiN) or thallium nitride (thallium nitride). The work function layer determines a work function of the gate electrode, and may include at least one layer, or a plurality of layers formed of different materials. The particular material of the work function layer may be selected based on whether the individual FinFET is an n-type FinFET or a p-type FinFET. For example, when the FinFET is an n-type FinFET, the work function layer may comprise a layer of AlTiC. When the FinFET is a p-type FinFET, the work function layer may comprise a layer of AlTiN and/or AlTiC. After depositing the work function layer, a barrier layer (not shown) may be formed, which may be another TiN layer.

Fig. 16A, 16B, and 16C illustrate the formation of a second interlayer dielectric (ILD)96, which is deposited over ILD88 and over the replacement gate. ILD96 may be formed using materials and methods similar to those used to form ILD88, which are described above with reference to fig. 12A, 12B, and 12C, and will not be described again. In some embodiments, ILD88 and ILD96 may be formed of the same material. In other embodiments, ILD88 and ILD96 may be formed of different materials. In some embodiments, ILD96 may be a thick layer (not shown) used in the subsequent removal of ILD88, which may act as a mask.

Fig. 17A, 17B, and 17C illustrate the formation of contact openings 102 through ILD96 to gate electrode 94, and contact openings 104 through ILD96 and ILD88 to source/drain regions 82. Formation of

contact openings

102 and 104 may use any suitable patterning technique, such as photolithography, to form a mask over ILD96 and etch through ILD96 to form contact opening 102 and etch through ILD96 and ILD88 to form contact opening 104. In some embodiments, the formation of the

contact openings

102 and 104 may be done in separate steps. In some embodiments, the formation of

contact openings

102 and 104 may be done simultaneously, using etch stop layer 87 to protect the underlying structures. After forming

contact openings

102 and 104 through ILD96 and through ILD96 and ILD88, respectively, the exposed portions of etch stop layer 87 may be removed by a subsequent etch that is selective to the material of etch stop layer 87.

Referring to fig. 18A-23C, a contact formation process is shown, according to some embodiments. As part of the contact formation process described in more detail below, N may be used₂/H₂And a plasma treatment process to improve adhesion of the contact to the replacement gate electrode, or adhesion of the contact to the source/drain regions. Fig. 18A, 18B, and 18C illustrate the formation of a metal layer 106 in the

contact openings

102 and 104. The metal layer 106 may be formed from one or more layers of titanium, nickel, cobalt, tungsten, platinum, molybdenum, tantalum, the like, or combinations of the foregoing. The metal layer 106 may be formed by PVD, CVD, ALD, sputter deposition, similar processes, or combinations of the foregoing, to a thickness of aboutTo about

The metal layer 106 may be suitably thinner or thicker. In some embodiments, the metal layer 106 may comprise titanium or other suitable metal, which is formed by a CVD process or the like.

Fig. 19A, 19B and 19C illustrate the formation of a metal layer 107 in

contact openings

102 and 104, which is subjected to a process corresponding to fig. 19A, 19B and 19C, in accordance with some embodimentsInstead of the formation of the metal layer 106 as shown in fig. 18A, 18B, and 18C. Accordingly, fig. 19A, 19B, and 19C begin with the process flow of fig. 17A, 17B, and 17C, respectively. In some technology nodes, the metal layer 107 may be formed on non-vertical surfaces of the insulating layer and the source/drain regions 82. In such embodiments, the metal layer 107 may be formed from one or more layers of titanium, nickel, cobalt, tungsten, platinum, molybdenum, tantalum, the like, or combinations of the foregoing. Metal layer 107 may be formed by a suitable deposition process, such as by PVD, sputter deposition, the like, or combinations of the foregoing, which is formed from about

To about

But metal layer 107 may also be suitably thinner or thicker. For example, in some embodiments, metal layer 107 may comprise titanium or other suitable metal, which is formed by a PVD process or the like.

After forming the metal layer 106 of fig. 18A, 18B, and 18C, or the metal layer 107 of fig. 19A, 19B, and 19C, silicide 83 may be formed in the source/drain regions 82. Silicide 83 may be formed from metal layer 106 or metal layer 107, and the formation of silicide 83 includes performing an annealing process such that silicide 83 is formed from a reaction between metal layer 106 or metal layer 107 and the material of source/drain regions 82. In some embodiments, the annealing process is performed using rapid thermal annealing, thermal soak, spike annealing, flash annealing, laser annealing, microwave annealing, the like, or a combination of the foregoing. In some embodiments, the annealing process may be performed at a temperature greater than about 500 ℃ to about 950 ℃, although other temperatures are contemplated and may be suitably used.

In some embodiments, either metal layer 106 or metal layer 107 may be consumed in the silicidation process. In some embodiments, if any metal remains unreacted, the remaining

metal layer

106 or 107 may be removed. In other embodiments, another metal layer may be deposited by using processes and materials similar to metal layer 106 or metal layer 107 to restore the metal layer (see fig. 18A, 18B, and 18C and fig. 19A, 19B, and 19C); in other embodiments, unreacted portions of metal layer 106 or metal layer 107 may remain.

The following description with respect to fig. 20A to 23C illustrates an embodiment using the metal layer 106, the metal layer 106 being described with reference to fig. 18A, 18B, and 18C described above. However, it is to be understood that the metal layer 107 of fig. 19A, 19B, and 19C may replace the metal layer 106 in fig. 20A to 23C described below.

Referring to fig. 20A, 20B, and 20C, formation of a metal nitride layer 108 in

contact openings

102 and 104 is shown, according to some embodiments. The metal nitride layer 108 may comprise titanium nitride, tantalum nitride, similar materials, or combinations of the foregoing, and the metal nitride layer 108 may be a metal nitride of the metal used in the metal layer 106. The metal nitride layer 108 may be formed by PVD, CVD, ALD, the like, or combinations of the foregoing, to a thickness of about

To about

Other thicknesses are contemplated and used. In some embodiments, the metal nitride layer 108 may comprise titanium nitride formed by a CVD process or the like. The metal nitride layer 108 may be formed so as not to have a crystal structure, or in other words, the metal nitride layer 108 may be amorphous (amorphus). In such embodiments, the subsequently deposited contact plug has poor adhesion to the metal nitride layer 108, at least in part because the metal nitride layer 108 is amorphous.

In some embodiments, the formation of the silicide may be performed after the formation of the metal nitride layer 108. In such embodiments, metal nitride layer 108 may serve as a capping layer to reduce the loss of metal layer 106 or metal layer 107 during the annealing process for silicide formation.

FIG. 21A, FIG. 21B and FIG. 21C illustrate the application toPlasma treatment process 110 of region 100. N may be used in a process chamber₂/H₂The plasma treatment process performs a plasma treatment process 110 whereby nitrogen atoms are introduced into the metal nitride layer 108 to change the metal nitride layer 108 into a nitrogen-rich metal nitride layer 112, leaving free (unbound) nitrogen atoms available for bonding with subsequently deposited contact plug material. The concentration of free nitrogen atoms at the surface of the nitrogen-rich metal nitride layer 112 may be greatest and may decrease with depth into the nitrogen-rich metal nitride layer 112. The plasma treatment process 110 may use N₂And H₂As the process gas, other process gases may be used as appropriate. N is a radical of₂/H₂The plasma treatment process 110 may be performed at a temperature between about 250 c to about 800 c, such as about 300 c, with a bias of 0W for compliant treatment, and at a pressure of about 1torr (torr) to about 100torr, such as about 3torr, although other process conditions are contemplated and suitably used. The plasma treatment process may also remove oxides that may have formed in previous processes for pre-cleaning subsequent contact plugs.

In some embodiments, N may be present at one or more times₂/H₂Silane (SiH) before and/or after plasma treatment₄) And (5) soaking. The silane soak may also provide free silicon atoms at the surface of the nitrogen-rich metal nitride layer 112, thereby enhancing N₂/H₂Effectiveness of plasma treatment, which may be used to subsequently form an intermediate layer between the contact plug and the nitrogen-rich metal nitride layer 112. The silane soak may be performed in the same chamber as the plasma processing process 110, and in some embodiments, the process gas may comprise any silicon-containing gas, such as Silane (SiH)₄) Dichlorosilane (DCS), Disilane (DS), Trichlorosilane (TCS), combinations of the foregoing, or the like. The silane soak may be conducted at a temperature between about 250 ℃ and about 800 ℃, such as about 300 ℃, at a pressure between about 1torr and about 100torr, such as about 35torr, at aboutAt a flow rate of between 300 standard cubic centimeters per minute (sccm) and 600sccm, such as at about 450sccm for a period of about 60 seconds to about 120 seconds, such as about 100 seconds, although other process conditions are contemplated and suitably employed.

Fig. 22A, 22B, and 22C illustrate forming contact plugs 114 in contact openings 102 to gate electrodes 94 and forming contact plugs 114 in contact openings 104 to source/drain regions 82, in accordance with some embodiments. The conductive material of the contact plug 114 may include cobalt, copper alloy, silver, tungsten, aluminum, nickel, or the like. In some embodiments, the conductive material of the contact plug 114 is cobalt. The contact plugs 114 may be formed in the

contact openings

102 and 104 by any suitable technique, such as by PVD, ALD, CVD, plating, and other like processes. The contact plugs 114 may extend over the

contact openings

102 and 104 and over an upper surface of the insulating layer (also referred to as ILD) 96. In some embodiments, a separate pre-clean cycle may be performed prior to forming contact plug 114, such as a separate N₂/H₂Plasma treatment, which may further increase free nitrogen atoms at the surface of the nitrogen-rich metal nitride layer 112.

As the conductive material of the contact plug 114 is formed within the

contact openings

102 and 104, some of the available free nitrogen in the nitrogen-rich metal nitride layer 112 will combine with the conductive material of the contact plug 114 to form a thin film interlayer 113 (single layer) at the interface of the contact plug 114 and the nitrogen-rich metal nitride layer 112. In embodiments where silicon is available at the surface of the nitrogen-rich metal nitride layer 112, the thin film interlayer 113 may comprise a compound of a metal having covalent bonds, nitrogen, and silicon (M-N-Si), where the metal is the material of the contact plug 114; silicon may be obtained, for example, by diffusion from the silicide 83 and/or source/drain regions 82, through the nitrogen-rich metal nitride layer 112, and/or as a result of the silane soak (if performed) described above. In some embodiments, the thin film interlayer 113 may comprise a compound of metal and nitrogen (MxN) of the contact plug 114 in cases where silicon is not available, such as when the underlying substrate is TiN and no silane immersion is performed. Some of the nitrogen atoms and/or silicon atoms around the contact plug 114 may remain unbonded. Some embodiments may have both compounds comprising M-N-Si and compounds comprising MxN.

In some embodiments, the thin film interlayer 113 may be less than about 1nm thick, such as about 0.5nm to about 1nm thick, although the thin film interlayer 113 may be thicker or thinner. Furthermore, when the contact plug 114 is formed using an epitaxial deposition process or other crystal growth process, the thin film interlayer 113 will have a crystal structure similar to that of the contact plug 114, the thin film interlayer 113 will have a crystal structure with a first lattice constant, and the conductive material of the contact plug 114 will have a crystal structure with a second lattice constant. Also, the mismatch between the first lattice constant and the second lattice constant is small (because they share a common conductive material). When the two materials have a small lattice mismatch, i.e., less than about 2% or less than 1%, the two materials have better adhesion. For example, in the case where the material of the contact plug 114 is cobalt, the difference between the lattice constants of Co and cox n is about 0.08%.

The resulting interface between the contact plug 114 and the nitrogen-rich metal nitride layer 112 (by way of the thin film interlayer 113) provides strong adhesion between the layers, even when the nitrogen-rich metal nitride layer 112 is amorphous. The thin film interlayer 113 may be formed in part by the underlying nitrogen-rich metal nitride layer 112, with some of the metal of the contact plug 114 embedded in the underlying layer. The thin film interlayer 113 may also be formed in part from nitrogen atoms available at or near the surface of the underlying nitrogen-rich metal nitride layer 112 in combination with the metal of the contact plug 114 above the underlying layer. The thin film interlayer 113 may also be formed in part from silicon atoms available at or near the surface of the underlying nitrogen-rich metal nitride layer 112 in combination with the metal of the contact plug 114, or from silicon atoms available at the silicide 83 or source/drain regions 82 in combination with the metal of the contact plug 114.

In the case of poor adhesion, the two films will show de-wetting (separation) after they are subjected to a subsequent process using a thermal process, such as annealing. The higher the dewetting, the poorer the adhesion. In an exemplary process, the de-wetting of the bond may be from about 0% to about 20%, such as about 1%. The crystal structure of M (and MxN or M-N-Si thin film interlayer 113) depends on the metal selected to form contact plug 114. Some metals may form a body-centered-cubic (bcc) structure, while other metals may form a face-centered-cubic (fcc) structure or a hexagonal closest-packed (hcp) structure. The metals should be selected such that the nitrides of the selected metals have the same crystal structure (except for the small lattice mismatch as described above).

After forming the contact plug 114, some of the free nitrogen atoms are used to form the thin film interlayer 113, and some of the free nitrogen atoms may not bond with the material of the contact plug 114 and may still surround the contact plug 114, for example, in the nitrogen-rich metal nitride layer 112.

In one embodiment, the metal layer 106 may be Ti, the metal nitride layer 108 may be TiN, and the conductive material of the contact plug 114 may be Co. In N₂/H₂After the plasma treatment of (a), the deposition of Co forms a crystalline layer of cox N and/or C0-N-Si between the Co contact plug 114 and the TiN nitrogen-rich metal nitride layer 112. The thickness of the CoxN layer and/or the Co-N-Si layer may be less than 1nm, for example, between about 0.5nm and about 1nm, although other thicknesses are also contemplated and used. The Co contact plug 114 deposition and the CoxN layer and/or Co-N-Si layer are both face centered cubic (fcc) oriented crystalline structures and, although there is a lattice mismatch due to the inclusion of N atoms and/or Si atoms of the CoxN structure and/or Co-N-Si structure, as compared to the absence of N atoms₂/H₂The similarity of the lattice structure provides improved adhesion by plasma treatment. The thin film interlayer 113 also exhibits good thermal stability, which provides fewer potential problems that may be introduced in subsequent processes. For example, it has been shown that the thin film interlayer 113 remains after annealing at 400 ℃ for 30 minutes.

Fig. 23A, 23B, and 23C illustrate that a planarization process, such as Chemical Mechanical Polishing (CMP), may be performed to remove excess material from the top surface of the interlayer dielectric (ILD)96, and may also remove excess portions of the nitrogen-rich metal nitride layer 112 and the metal layer 106, according to some embodiments. The remaining nitrogen-rich metal nitride layer 112 and conductive material form a contact 116 to gate electrode 94, and a contact 118 to source/drain region 82.

Fig. 24 shows the wet state of some exemplary materials to compare the adhesive layer that was not treated using the process of the example and the adhesive layer that was treated using the process of the example. The film stack for this example comprises a silicon substrate, a thermal oxide layer (SiO) of the silicon substrate, and

the TiN layer of (1). In carrying out N₂/H₂In an example of plasma treatment, N was performed on a TiN layer₂/H₂And (4) carrying out plasma treatment. In N₂/H₂After plasma treatment, deposition by CVD

The Co layer of (3). At H₂Annealing was performed at 420 ℃ for 480 seconds in ambient. After this process, a dewetting test may be performed on each example.

Element 205 illustrates an interface comprising an adhesion layer comprising an ALD-formed TiN layer having a Miller index (Miller index) of (111), which was not treated using the treatment process of the example, with a measured dewetting of 6.2%. In other words, about 6.2% of the interface is not wetted. Element 210 illustrates an interface comprising an adhesion layer comprising an ALD-formed TiN layer having a miller index (111) that was treated using the treatment process of the example, measured to have a dewet of less than 1.3%. In other words, less than about 1.3% of the interface is unwetted. Element 215 illustrates an interface including an adhesion layer comprising a CVD-formed TiN layer (using TiCl)₄A precursor as a Ti source, and an N-based precursor such as NH₃Formed as an N source), where the miller index of TiN comprises (111) and (200), which were not treated using the treatment process of the example, measured to be 69% dewetting. In other words, about 69% of the interface is not wetted. Element 220 illustrates a boundary including an adhesive layerThe adhesion layer comprises a TiN layer formed by CVD (using TiCl)₄A precursor as a Ti source, and an N-based precursor such as NH₃Formed as an N source), wherein the miller index of TiN comprises (111) and (200), which were treated using the treatment processes of the examples, measured dewetting of less than 0.1%. In other words, less than about 0.1% of the interface is unwetted.

As shown in the examples, in the case of forming an adhesion layer by an ALD process, N₂/H₂The plasma treatment process can improve dewetting by a factor of about 4. In the case of forming an adhesion layer by a CVD process, N₂/H₂The plasma treatment process may improve de-wetting by a factor of about 700, resulting in substantially complete wetting (or substantially no de-wetting), and the treatment process of embodiments may improve wetting by a factor of about 4 to 700.

Fig. 25-32 illustrate the use of N on other materials, according to some embodiments₂/H₂And (3) a plasma treatment process. Rather than depositing a metal nitride layer, such as metal nitride layer 108 of fig. 20A, 20B, and 20C, in an opening formed within a dielectric material, in some embodiments, a treatment process may be applied directly to a layer, such as an insulating layer or a substrate comprising TiN, SiO, SiN, or other suitable material.

Fig. 25 illustrates a film layer 310 of a film stack 300, the film layer 310 may comprise one or more layers of TiN, SiO, SiN, or other suitable material, in accordance with some embodiments. The film layer 315 may be a substrate or dielectric material in which the contacts 320 are formed. The contact 320 may be electrically coupled to a device. In some embodiments, the film stack 300 may be part of an interconnect, such as a redistribution structure. In some embodiments, the film stack 300 may be part of a structure having an embedded device formed therein.

Fig. 26 illustrates the formation of an opening 325 in the film layer 310, the opening 325 exposing the contact 320. The openings 325 may be formed by any suitable process, such as by photolithographic techniques.

FIG. 27 illustrates N according to some embodiments₂/H₂Application of the plasma treatment process 330, the plasma treatment process 330 may be used as described above with respect to FIG. 21A. The plasma treatment process 110 of fig. 21B and 21C is performed using similar processes and materials as discussed herein and will not be repeated. The exposed portion of the film 310 is processed to obtain a processing region 335 in which unbound nitrogen atoms are incorporated into the material of the film 310, resulting in a concentration of free nitrogen atoms in the processing region 335. The concentration of nitrogen atoms may be greatest at the surface of film layer 310 and may extend into the underlying material to about 2 nm; the nitrogen atom concentration may have a uniform concentration gradient throughout the processing region 335 using a zero bias of N₂/H₂The plasma treatment process may provide a uniform nitrogen distribution.

Fig. 28 illustrates the deposition of contact plug 340 in opening 325. contact plug 340 may be formed using similar materials and processes as described above with respect to contact plug 114 of fig. 22A, 22B, and 22C, and will not be repeated here.

As the conductive material of the contact plug 340 is formed within the opening 325, some of the unbound nitrogen in the processing region 335 may combine with the conductive material of the contact plug 340 to form a thin film interlayer 345 at the interface of the contact plug 340 and the processing region 335. The thin film interlayer 345 may include a layer containing an MxN compound and/or an M-N-Si compound, where M is a conductive material of the contact plug 340. The resulting thin film interlayer 345 provides strong adhesion to the contact plug 340 in a process similar to that of fig. 22A, 22B, and 22C described above. Some nitrogen atoms around the contact plug 340 may remain unbound.

Fig. 29 illustrates forming a contact 350 by planarizing the contact plug 340, according to some embodiments. A planarization process, such as a CMP process, may be used to planarize the top surface of contact 350 with the top surface of film layer 310.

Fig. 30 illustrates a film layer 410 of a film stack 400 according to some embodiments, the film layer 410 may comprise one or more layers of TiN, SiO, SiN, or other suitable materials. Can carry out N₂/H₂ Plasma treatment process 420, plasma treatment process 420 may be performed using processes and materials similar to those discussed above for plasma treatment process 110 of fig. 21A, 21B, and 21C, and will not be repeated here. Treating the film layer 410 to obtain a treated partThe processing region 425, the processing region 425 may be similar to the processing region 335 of fig. 27, with unbound nitrogen atoms being concentrated in the processing region 425.

Fig. 31 illustrates the deposition of a metal layer 430 of a film stack over the processing region 425. the metal layer 430 may be formed using materials and processes similar to those described above for the contact plug 114 of fig. 22A, 22B, and 22C and will not be repeated.

When forming the conductive material of the metal layer 430, some of the unbound nitrogen in the processing region 425 may combine with the conductive material of the metal layer 430 to form a thin film interlayer 435 at the interface of the metal layer 430 and the processing region 425. The thin film interlayer 435 may comprise a layer containing an MxN compound and/or an M-N-Si compound, where M is the conductive material of the metal layer 430. The resulting thin film interlayer 435 provides strong adhesion to the metal layer 430 in a process similar to that described above with respect to fig. 22A, 22B, and 22C. Some of the nitrogen atoms under metal layer 430 may remain unbound.

Fig. 32 illustrates planarizing the metal layer 430 to form a metal layer 440 with a planar top surface, in accordance with some embodiments. A planarization process, such as a CMP process, may be used to planarize the top surface of metal layer 430. After the planarization process, the top surface of the metal layer 440 may be coplanar with surrounding structures (not shown).

FIG. 33 illustrates a graph of material properties of contacts according to some embodiments. In one exemplary embodiment, Co contacts in a SiO base are used to provide concentrations of various materials at various depths of the contact. As N₂/H₂As a result of the plasma treatment process, an intermediate layer comprising cox N and/or Co-N-Si is formed between the substrate and the Co contact. Line 225 is shown atCo concentration at various depths in units. Line 230 is shown as

In units of oxygen concentration at various depths. Line 235 is shown as

In units of silicon concentration at various depths. Line 240 is shown as

Is the nitrogen concentration in units at various depths. The band 245 is indicated by a dashed line, which represents the approximate depth of the middle layer. Band 250 represents the approximate depth of the Co contact. The strip 255 represents the underlying SiO substrate. As shown in fig. 33, in the intermediate layer, the concentration of Co gradually decreases from the Co contact through the intermediate layer to the SiO substrate under. In some cases, Si may also be present to form a co (Si) N material. The depth of the intermediate layer may vary depending on the thickness of the metal of the contact. For a Co contact, the thickness of the intermediate layer may be less than 1nm, for example, between about 0.5nm and about 1nm, although other dimensions are also contemplated and used.

In another embodiment, the substrate may be TiN. The dewetting of the Co contact may be between about 40% and 50% at the edge of the contact, and approximately 0% at the center of the contact. In silane soak and N₂/H₂After plasma treatment, the dewetting of the Co contact is approximately 0% at the edge of the contact and at the center of the contact. In another embodiment, the substrate may be SiO. The dewetting of the Co contact may be approximately 0% at the edge of the contact and approximately 0% at the center of the contact. In another embodiment, the substrate may be SiN. The dewetting of the Co contact may be approximately 0% at the edge of the contact and approximately 0% at the center of the contact. Those skilled in the art to which the invention pertains will appreciate that these are exemplary only and are not intended to limit all embodiments. However, it can be observed that the process of the embodiment described above provides improved wetting of the contacts.

Embodiments provide improved wetting of contacts formed in a substrate. Instead of dewetting occurring between a contact such as a contact plug and a substrate in which the contact is formed, the process of the embodimentImproved wetting of the contacts may be provided such that the contacts are substantially fully wetted. In some embodiments, the contact may wet 4 to 700 times more thoroughly, resulting in better adhesion, than a process without an embodiment. Example Using N₂/H₂Plasma treatment to incorporate excess N atoms at the surface of the layer below the contact. When the contact is subsequently formed, a cross-linked layer is formed between the contact material and the material under the contact due to similar crystallinity between the contact material and the nitride of the contact material.

One embodiment is a method of forming a semiconductor device, the method comprising forming an opening in an insulating layer of a structure, depositing an adhesion layer in the opening, incorporating nitrogen atoms into the adhesion layer, depositing a metal into the opening, the metal forming an intermediate layer between the metal plug and the adhesion layer, the intermediate layer comprising a compound of the metal and nitrogen.

In some embodiments, the adhesion layer comprises TiN in an amorphous state. In some embodiments, the metal of the metal plug comprises Co. In some embodiments, the step of incorporating nitrogen atoms into the adhesion layer comprises applying N to the adhesion layer₂/H₂And (4) carrying out plasma treatment.

In some embodiments, the method further comprises immersing the structure in silane prior to depositing the metal, the compound comprising silicon. In some embodiments, the method further comprises depositing a metal layer in the opening and forming a silicide prior to depositing the adhesion layer. In some embodiments, the adhesion layer is a nitride of the metal layer.

In some embodiments, the intermediate layer of metal nitride comprises a first crystal structure, the metal plug comprises a second crystal structure, and the lattice mismatch of the first crystal structure and the second crystal structure is less than 2%.

Another embodiment is a method of forming a semiconductor device, the method comprising forming an opening in an insulating layer, the opening having sidewalls and a bottom. The sidewalls and bottom of the opening are treated with a nitrogen-based plasma process that incorporates free nitrogen atoms into the sidewalls and bottom of the opening. A metal plug is formed in the opening, the metal plug comprising a metal that bonds with free nitrogen atoms to form an intermediate layer between the metal plug and the sidewalls and bottom of the opening.

In some embodiments, the insulating layer comprises SiO or SiN. In some embodiments, the metal of the metal plug comprises Co. In some embodiments, the processing includes applying N to the sidewalls and bottom of the opening₂/H₂Plasma is generated. In some embodiments, the method further comprises forming an adhesion layer in the opening prior to processing the opening, the adhesion layer comprising a metal nitride.

In some embodiments, the intermediate layer comprises a first crystal structure, the metal plug comprises a second crystal structure similar to the first crystal structure, and the first crystal structure and the second crystal structure have different lattice constants.

Another embodiment is a semiconductor device comprising a target region and an insulating layer on the target region. A metal plug is disposed within the insulating layer, the metal plug extending from a top of the insulating layer to the target area, the metal plug comprising a first material. An intermediate layer is disposed between the metal plug and the insulating layer, the intermediate layer comprising a compound of the first material and nitrogen, and free nitrogen atoms surrounding the intermediate layer.

In some embodiments, the first material comprises Co. In some embodiments, the insulating layer comprises SiO or SiN, and the compound of the intermediate layer contains silicon.

In some embodiments, the intermediate layer comprises a first crystal structure having a first lattice constant, the metal plug comprises a second crystal structure having a second lattice constant different from the first lattice constant, and both the first crystal structure and the second crystal structure are face centered cubic lattices.

In some embodiments, the semiconductor device further includes an adhesion layer interposed between the intermediate layer and the insulating layer, the adhesion layer including a metal nitride, and the free nitrogen atoms being in the metal nitride.

In some embodiments, the semiconductor device further comprises source/drain regions of the finfet, wherein the target region comprises the source/drain regions; and a metal layer interposed between the adhesion layer and the insulation layer, the metal layer containing a metal material of a metal nitride of the adhesion layer.

The components of several embodiments are summarized above so that those skilled in the art to which the present invention pertains may more clearly understand the concepts of the embodiments of the present invention. Those skilled in the art should appreciate that they may readily use the present embodiments as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same benefits of the embodiments introduced herein. It should also be understood by those skilled in the art that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that various changes, substitutions, and alterations can be made herein without departing from the spirit and scope of the present disclosure. Therefore, the protection scope of the present invention should be determined by the following claims.

Claims

1. A method of forming a semiconductor device, comprising:

forming an opening in an insulating layer of a structure;

depositing an adhesive layer in the opening;

incorporating nitrogen atoms into the adhesion layer; and

depositing a metal into the opening, the metal forming an intermediate layer between a metal plug and the adhesion layer, the intermediate layer comprising a compound of the metal and nitrogen.

2. The method of claim 1, wherein incorporating nitrogen atoms into the adhesion layer comprises applying N to the adhesion layer₂/H₂And (4) carrying out plasma treatment.

3. The method for forming a semiconductor device according to claim 2, further comprising:

prior to depositing the metal, the structure is immersed in silane, wherein the compound contains silicon.

4. The method for forming a semiconductor device according to claim 1, further comprising:

depositing a metal layer in the opening before depositing the adhesion layer; and

a silicide is formed.

5. The method of claim 1, wherein said intermediate layer of metal nitride comprises a first crystal structure, said metal plug comprises a second crystal structure, and wherein said first crystal structure and said second crystal structure have a lattice mismatch of less than 2%.

6. A method of forming a semiconductor device, comprising:

forming an opening in an insulating layer, the opening having sidewalls and a bottom;

treating the sidewalls and bottom of the opening with a nitrogen-based plasma process that incorporates a free nitrogen atom into the sidewalls and bottom of the opening; and

forming a metal plug in the opening, the metal plug comprising a metal that bonds with the free nitrogen atoms to form an intermediate layer between the metal plug and the sidewalls and bottom of the opening.

7. The method for forming a semiconductor device according to claim 6, further comprising:

an adhesion layer is formed in the opening prior to processing the opening, the adhesion layer comprising a metal nitride.

8. A semiconductor device, comprising:

a target area;

an insulating layer over the target region;

a metal plug disposed within the insulating layer, the metal plug extending from a top of the insulating layer to the target region, the metal plug comprising a first material; and

an intermediate layer disposed between the metal plug and the insulating layer, the intermediate layer comprising a compound of the first material and nitrogen, wherein a free nitrogen atom surrounds the intermediate layer.

9. The semiconductor device of claim 8, further comprising an adhesion layer between said intermediate layer and said insulating layer, wherein said adhesion layer comprises a metal nitride, and wherein said free nitrogen atoms are in said metal nitride.

10. The semiconductor device according to claim 9, further comprising:

a source/drain region of a finfet, wherein the target region comprises the source/drain region; and

a metal layer interposed between the adhesion layer and the insulating layer, the metal layer including a metal material of the metal nitride of the adhesion layer.