CN110660667B - IGBT manufacturing method and IGBT - Google Patents

IGBT manufacturing method and IGBT Download PDF

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CN110660667B
CN110660667B CN201810712335.4A CN201810712335A CN110660667B CN 110660667 B CN110660667 B CN 110660667B CN 201810712335 A CN201810712335 A CN 201810712335A CN 110660667 B CN110660667 B CN 110660667B
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CN110660667A (en
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王学良
刘建华
郎金荣
闵亚能
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SHANGHAI ADVANCED SEMICONDUCTO
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234Bipolar junction transistors [BJT]
    • H01L29/66325Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
    • H01L29/66333Vertical insulated gate bipolar transistors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H01L29/167Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table further characterised by the doping material
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70Bipolar devices
    • H01L29/72Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7395Vertical transistors, e.g. vertical IGBT
    • H01L29/7398Vertical transistors, e.g. vertical IGBT with both emitter and collector contacts in the same substrate side

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Abstract

The invention discloses an IGBT manufacturing method and an IGBT. The IGBT is a planar IGBT or a trench IGBT, and the IGBT manufacturing method comprises the following steps: manufacturing a front-side structure of the IGBT, wherein the manufacturing method comprises the steps of doping first ions in silicon to form a p+ region, and the diffusion coefficient of the first ions is higher than that of boron ions; and manufacturing a back structure of the IGBT. According to the invention, when the p+ region is manufactured, the first ion with the doping larger than the boron ion diffusion coefficient, such as aluminum ion or gallium ion, is adopted to replace the boron ion doping in the prior art, and a PN junction deeper, wider and gradually changed than the boron ion diffusion mode can be formed in a lower temperature and shorter time, so that compared with the traditional IGBT, the manufactured IGBT further improves the latch-up resistance, has higher reverse breakdown voltage and shorter storage time, improves the stability of the IGBT, and has certain cost advantage.

Description

IGBT manufacturing method and IGBT
Technical Field
The invention belongs to the field of semiconductors, and particularly relates to a manufacturing method of an Insulated Gate Bipolar Transistor (IGBT) and the IGBT.
Background
The IGBT is a composite fully-controlled voltage-driven power semiconductor device composed of a BJT (bipolar Transistor) and a MOS (insulated gate field effect Transistor), and has the advantages of both high input impedance of the MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) and low on-voltage drop of the GTR (Giant Transistor). The GTR saturation voltage is reduced, the current carrying density is high, but the driving current is high; the MOSFET has small driving power, high switching speed, large conduction voltage drop and small current carrying density. The IGBT combines the advantages of the two devices, and has small driving power and reduced saturation voltage. The device is very suitable for being applied to the fields of variable current systems with the direct current voltage of 600V (volts) or more, such as alternating current motors, frequency converters, switching power supplies, lighting circuits, traction transmission and the like.
Fig. 1 shows a structure of a conventional planar IGBT, which includes an n-drift region 101, a p-well 102 (p-well), an n+ source region 103, a p+ region 104, a p+ Layer 105, an n+ electric Field Stop Layer 106, an emitter E, a gate G, and a collector C. Fig. 2 shows a structure of another conventional planar IGBT, which omits the n+ electric field cut-off layer 106 compared to the structure shown in fig. 1. Fig. 3 shows a structure of a conventional trench IGBT, which includes an n-drift region 201, a p-type base region 202 (p-base), an n+ source region 203, a p+ region 204, an n+ electric field cut-off layer 205, a p+ layer 206, an emitter E, a gate G, and a collector C. Fig. 4 shows a structure of another conventional trench type IGBT, which omits the n+ electric field cut-off layer 205 compared to the structure shown in fig. 3.
In the prior art, when manufacturing the IGBT with the above structure, a p+ region is usually formed by adopting a boron ion diffusion (diffusion or implantation) manner, and the diffusion time and the temperature are relatively long, the formed PN junction is relatively steep, the reverse breakdown voltage is relatively low, the storage time is relatively long, and the latch-up resistance is insufficient, so that the performance of the manufactured IGBT is unstable.
Disclosure of Invention
The invention aims to overcome the defects of lower reverse breakdown voltage, longer storage time and insufficient latch-up resistance of an IGBT caused by the formation of a p+ region by injecting boron ions in the prior art, and provides an IGBT manufacturing method capable of improving the reverse breakdown voltage, the storage time and the latch-up resistance of the IGBT and the IGBT.
The invention solves the technical problems through the following technical scheme:
an IGBT manufacturing method, wherein the IGBT is a planar IGBT or a trench IGBT, the IGBT manufacturing method includes:
manufacturing a front-side structure of the IGBT, wherein the manufacturing method comprises the steps of doping first ions in silicon to form a p+ region, and the diffusion coefficient of the first ions is higher than that of boron ions;
and manufacturing a back structure of the IGBT.
Preferably, doping the first ions includes diffusing aluminum ions.
Preferably, the temperature of the diffused aluminum ions is 1000 ℃ to 1300 ℃.
Preferably, the temperature of the diffused aluminum ions is 1250 ℃.
Preferably, the aluminum ions are diffused for 14 hours so that the diffusion depth of the aluminum ions reaches 250 micrometers; or, aluminum ions were diffused for 4 hours so that the diffusion depth of aluminum ions reached 25 μm.
Preferably, doping the first ions includes implanting aluminum ions.
Preferably, doping the first ions comprises diffusing gallium ions.
Preferably, the temperature of the diffused gallium ions is 800-1200 ℃.
Preferably, the temperature of the diffused gallium ions is 1100 ℃.
Preferably, the gallium ions are diffused for 19 hours so that the diffusion depth of the gallium ions reaches 60 μm.
The IGBT is a planar IGBT or a trench IGBT, and is manufactured by the IGBT manufacturing method.
On the basis of conforming to the common knowledge in the field, the above preferred conditions can be arbitrarily combined to obtain the preferred examples of the invention.
The invention has the positive progress effects that: according to the invention, when the p+ region is manufactured, the first ion with the doping larger than the diffusion coefficient of the boron ion, such as aluminum ion or gallium ion, is adopted to replace the boron ion diffusion in the prior art, and a PN junction deeper, wider and gradually changed than the boron ion diffusion mode can be formed in a lower temperature and shorter time, so that compared with the traditional IGBT, the manufactured IGBT further improves the latch-up resistance, has higher reverse breakdown voltage and shorter storage time, improves the stability of the IGBT, and has certain cost advantage.
Drawings
Fig. 1 is a schematic structural diagram of a planar IGBT according to the prior art;
fig. 2 is a schematic structural diagram of another planar IGBT according to the prior art;
fig. 3 is a schematic structural diagram of a trench IGBT according to the prior art;
fig. 4 is a schematic structural diagram of another trench IGBT according to the prior art;
fig. 5 is a flowchart of a method of fabricating the IGBT shown in fig. 1 according to embodiment 1 of the invention;
fig. 6 is a flowchart of a method of fabricating the IGBT shown in fig. 2 according to embodiment 3 of the invention;
fig. 7 is a flowchart of a method of fabricating the IGBT shown in fig. 3 according to embodiment 5 of the invention;
fig. 8 is a flowchart of a method of fabricating the IGBT shown in fig. 4 according to embodiment 7 of the invention.
Detailed Description
The invention is further illustrated by means of the following examples, which are not intended to limit the scope of the invention. The experimental methods, in which specific conditions are not noted in the following examples, were selected according to conventional methods and conditions, or according to the commercial specifications.
Example 1
The embodiment provides a manufacturing method of the planar IGBT shown in fig. 1. As shown in fig. 5, the manufacturing method includes:
step 11, manufacturing a front surface structure of a planar IGBT, wherein the front surface structure comprises doping first ions in silicon to form a p+ region 104, wherein the diffusion coefficient of the first ions is higher than that of boron ions;
and step 12, manufacturing a back structure of the planar IGBT.
Wherein p+ region 104 is formed within p-well 102 and is located on one side of n+ source region 103.
Step 11 further specifically includes, but is not limited to, the following steps: 1) A step of forming an n-drift region 101; 2) A step of forming an n+ electric field cut-off layer 106; 3) A step of forming a p-well 102; 4) A step of forming an n+ source region 103; 5) The step of forming the metal electrode includes an emitter E and a gate G. The above steps are all conventional steps for fabricating a planar IGBT, and are not described herein. Wherein the step of doping the silicon with first ions to form the p+ region 104 is typically performed after the formation of the n+ source region 103 and before the formation of the metal electrode. In addition, a further layer of boron may be deposited over the p+ region 104 formed by doping with the first ions.
Step 12 specifically includes, but is not limited to, the following steps: 1) Thinning the back; 2) A back-side implantation step to form a p+ layer 105; 3) A step of back surface cleaning; 4) A step of forming a metal electrode, i.e., a collector C. The above steps are all conventional steps for fabricating a planar IGBT, and are not described herein.
The steps of doping the first ions to form the p+ region 104 are further described below:
in a first embodiment, doping the first ions may include diffusing aluminum ions. Wherein, for the temperature of diffusion, the temperature of the diffused aluminum ions can be selected from 1000 ℃ to 1300 ℃, and preferably, the temperature of the diffused aluminum ions is 1250 ℃. For the diffusion time, aluminum ions were diffused for 14 hours so that the diffusion depth of aluminum ions reached 250 μm; or, aluminum ions were diffused for 4 hours so that the diffusion depth of aluminum ions reached 25 μm.
In a second embodiment, doping the first ions may include implanting aluminum ions.
In a third embodiment, doping the first ions may include diffusing gallium ions. Wherein, for the diffusion temperature, the temperature of the diffused gallium ions can be selected to be 800-1200 ℃, and preferably, the temperature of the diffused gallium ions is 1100 ℃. For the diffusion time, gallium ions were diffused for 19 hours so that the diffusion depth of gallium ions reached 60 μm.
In this embodiment, since the diffusion coefficient of aluminum ion or gallium ion is greater than that of aluminum ion, by means of diffusing aluminum ion, implanting aluminum ion or diffusing gallium ion, deeper, wider and gradually-changed PN junction can be formed at a lower temperature in a shorter time, so that compared with the existing IGBT, the fabricated IGBT further improves the latch-up resistance, has a higher reverse breakdown voltage, a shorter storage time, improves the stability of the IGBT, and has a certain cost advantage.
Example 2
The embodiment provides a planar IGBT, which is manufactured by adopting the manufacturing method of embodiment 1, and has a structure shown in fig. 1, and includes an n-drift region 101, a p-well 102, an n+ source region 103, a p+ region 104, a p+ layer 105, an n+ electric field stop layer 106, an emitter E, a gate G, and a collector C. Wherein, the p-well 102 is located in the n-drift region 101, the n+ source region 103 and the p+ region 104 are both formed in the p-well 102, the n+ electric field cut-off layer 106 is located under the n-drift region 101, the p+ layer 105 is located under the n+ electric field cut-off layer 106, the emitter E and the gate G are located on the front side of the planar IGBT, and the collector C is located on the back side of the planar IGBT.
Example 3
The embodiment provides a manufacturing method of the planar IGBT shown in fig. 2. As shown in fig. 6, the manufacturing method includes:
step 21, manufacturing a front surface structure of a planar IGBT, wherein the front surface structure comprises doping first ions in silicon to form a p+ region 104, wherein the diffusion coefficient of the first ions is higher than that of boron ions;
and step 22, manufacturing a back structure of the planar IGBT.
Wherein p+ region 104 is formed within p-well 102 and is located on one side of n+ source region 103.
Step 21 further specifically includes, but is not limited to, the following steps: 1) A step of forming an n-drift region 101; 2) A step of forming a p-well 102; 3) A step of forming an n+ source region 103; 4) The step of forming the metal electrode includes an emitter E and a gate G. The above steps are all conventional steps for fabricating a planar IGBT, and are not described herein. Wherein the step of doping the silicon with first ions to form the p+ region 104 is typically performed after the formation of the n+ source region 103 and before the formation of the metal electrode. In addition, a further layer of boron may be deposited over the p+ region 104 formed by doping with the first ions.
Step 22 specifically includes, but is not limited to, the following steps: 1) Thinning the back; 2) A back-side implantation step to form a p+ layer 105; 3) A step of back surface cleaning; 4) A step of forming a metal electrode, i.e., a collector C. The above steps are all conventional steps for fabricating a planar IGBT, and are not described herein.
The steps of doping the first ions to form the p+ region 104 are further described below:
in a first embodiment, doping the first ions may include diffusing aluminum ions. Wherein, for the temperature of diffusion, the temperature of the diffused aluminum ions can be selected from 1000 ℃ to 1300 ℃, and preferably, the temperature of the diffused aluminum ions is 1250 ℃. For the diffusion time, aluminum ions were diffused for 14 hours so that the diffusion depth of aluminum ions reached 250 μm; or, aluminum ions were diffused for 4 hours so that the diffusion depth of aluminum ions reached 25 μm.
In a second embodiment, doping the first ions may include implanting aluminum ions.
In a third embodiment, doping the first ions may include diffusing gallium ions. Wherein, for the diffusion temperature, the temperature of the diffused gallium ions can be selected to be 800-1200 ℃, and preferably, the temperature of the diffused gallium ions is 1100 ℃. For the diffusion time, gallium ions were diffused for 19 hours so that the diffusion depth of gallium ions reached 60 μm.
In this embodiment, since the diffusion coefficient of aluminum ion or gallium ion is greater than that of aluminum ion, by means of diffusing aluminum ion, implanting aluminum ion or diffusing gallium ion, deeper, wider and gradually-changed PN junction can be formed at a lower temperature in a shorter time, so that compared with the existing IGBT, the fabricated IGBT further improves the latch-up resistance, has a higher reverse breakdown voltage, a shorter storage time, improves the stability of the IGBT, and has a certain cost advantage.
Example 4
The embodiment provides a planar IGBT, which is manufactured by adopting the manufacturing method of embodiment 3, and has a structure shown in fig. 2, and includes an n-drift region 101, a p-well 102, an n+ source region 103, a p+ region 104, a p+ layer 105, an emitter E, a gate G, and a collector C. Wherein, the p-well 102 is located in the n-drift region 101, the n+ source region 103 and the p+ region 104 are both formed in the p-well 102, the p+ layer 105 is located under the n-drift region 101, the emitter E and the gate G are located on the front side of the planar IGBT, and the collector C is located on the back side of the planar IGBT.
Example 5
The embodiment provides a manufacturing method of the trench type IGBT shown in fig. 3. As shown in fig. 7, the manufacturing method includes:
step 31, manufacturing a front surface structure of a trench IGBT, wherein the manufacturing method comprises the steps of doping first ions in silicon to form a p+ region 204, wherein the diffusion coefficient of the first ions is higher than that of boron ions;
and 32, manufacturing a back structure of the groove type IGBT.
Wherein p+ region 204 is formed in p-type base region 202 and is located on one side of n+ source region 203.
Step 31 further specifically includes, but is not limited to, the following steps: 1) A step of forming an n-drift region 201; 2) A step of forming an n+ electric field cut-off layer 205; 3) A step of forming a p-type base region 202; 4) A step of forming an n+ source region 203; 5) The step of forming the metal electrode includes an emitter E and a gate G. The above steps are all conventional steps for manufacturing the trench IGBT, and are not described herein. Wherein the step of doping the silicon with first ions to form the p+ region 204 is typically performed after the formation of the n+ source region 203 and before the formation of the metal electrode. In addition, a further layer of boron may be deposited over the p+ region 204 formed by doping with the first ions.
Step 32 specifically includes, but is not limited to, the following steps: 1) Thinning the back; 2) A back side implantation step to form a p+ layer 206; 3) A step of back surface cleaning; 4) A step of forming a metal electrode, i.e., a collector C. The above steps are all conventional steps for manufacturing the trench IGBT, and are not described herein.
The steps of doping the first ions to form the p+ region 204 are further described below:
in a first embodiment, doping the first ions may include diffusing aluminum ions. Wherein, for the temperature of diffusion, the temperature of the diffused aluminum ions can be selected from 1000 ℃ to 1300 ℃, and preferably, the temperature of the diffused aluminum ions is 1250 ℃. For the diffusion time, aluminum ions were diffused for 14 hours so that the diffusion depth of aluminum ions reached 250 μm; or, aluminum ions were diffused for 4 hours so that the diffusion depth of aluminum ions reached 25 μm.
In a second embodiment, doping the first ions may include implanting aluminum ions.
In a third embodiment, doping the first ions may include diffusing gallium ions. Wherein, for the diffusion temperature, the temperature of the diffused gallium ions can be selected to be 800-1200 ℃, and preferably, the temperature of the diffused gallium ions is 1100 ℃. For the diffusion time, gallium ions were diffused for 19 hours so that the diffusion depth of gallium ions reached 60 μm.
In this embodiment, since the diffusion coefficient of aluminum ion or gallium ion is greater than that of aluminum ion, by means of diffusing aluminum ion, implanting aluminum ion or diffusing gallium ion, deeper, wider and gradually-changed PN junction can be formed at a lower temperature in a shorter time, so that compared with the existing IGBT, the fabricated IGBT further improves the latch-up resistance, has a higher reverse breakdown voltage, a shorter storage time, improves the stability of the IGBT, and has a certain cost advantage.
Example 6
The present embodiment provides a trench IGBT, which is fabricated by using the fabrication method of embodiment 5, and has a structure shown in fig. 3, and includes an n-drift region 201, a p-type base region 202, an n+ source region 203, a p+ region 204, an n+ electric field stop layer 205, a p+ layer 206, an emitter E, a gate G, and a collector C. The p-type base region 202 is located on the n-drift region 201, a trench, an n+ source region 203 and a p+ region 204 are formed in the p-type base region 202, an n+ electric field cut-off layer 205 is located below the n-drift region 201, a p+ layer 206 is located below the n+ electric field cut-off layer 205, an emitter E and a gate G (led out from the trench) are located on the front surface of the trench type IGBT, and a collector C is located on the back surface of the trench type IGBT.
Example 7
The embodiment provides a manufacturing method of the trench type IGBT shown in fig. 4. As shown in fig. 8, the manufacturing method includes:
step 41, manufacturing a front surface structure of a trench IGBT, wherein the front surface structure comprises doping first ions in silicon to form a p+ region 204, wherein the diffusion coefficient of the first ions is higher than that of boron ions;
and 42, manufacturing a back structure of the groove type IGBT.
Wherein p+ region 204 is formed in p-type base region 202 and is located on one side of n+ source region 203.
Step 41 also specifically includes, but is not limited to, the following steps: 1) A step of forming an n-drift region 201; 2) A step of forming a p-type base region 202; 3) A step of forming an n+ source region 203; 4) The step of forming the metal electrode includes an emitter E and a gate G. The above steps are all conventional steps for manufacturing the trench IGBT, and are not described herein. Wherein the step of doping the silicon with first ions to form the p+ region 204 is typically performed after the formation of the n+ source region 203 and before the formation of the metal electrode. In addition, a further layer of boron may be deposited over the p+ region 204 formed by doping with the first ions.
Step 42 specifically includes, but is not limited to, the following steps: 1) Thinning the back; 2) A back side implantation step to form a p+ layer 206; 3) A step of back surface cleaning; 4) A step of forming a metal electrode, i.e., a collector C. The above steps are all conventional steps for manufacturing the trench IGBT, and are not described herein.
The steps of doping the first ions to form the p+ region 204 are further described below:
in a first embodiment, doping the first ions may include diffusing aluminum ions. Wherein, for the temperature of diffusion, the temperature of the diffused aluminum ions can be selected from 1000 ℃ to 1300 ℃, and preferably, the temperature of the diffused aluminum ions is 1250 ℃. For the diffusion time, aluminum ions were diffused for 14 hours so that the diffusion depth of aluminum ions reached 250 μm; or, aluminum ions were diffused for 4 hours so that the diffusion depth of aluminum ions reached 25 μm.
In a second embodiment, doping the first ions may include implanting aluminum ions.
In a third embodiment, doping the first ions may include diffusing gallium ions. Wherein, for the diffusion temperature, the temperature of the diffused gallium ions can be selected to be 800-1200 ℃, and preferably, the temperature of the diffused gallium ions is 1100 ℃. For the diffusion time, gallium ions were diffused for 19 hours so that the diffusion depth of gallium ions reached 60 μm.
In this embodiment, since the diffusion coefficient of aluminum ion or gallium ion is greater than that of aluminum ion, by means of diffusing aluminum ion, implanting aluminum ion or diffusing gallium ion, deeper, wider and gradually-changed PN junction can be formed at a lower temperature in a shorter time, so that compared with the existing IGBT, the fabricated IGBT further improves the latch-up resistance, has a higher reverse breakdown voltage, a shorter storage time, improves the stability of the IGBT, and has a certain cost advantage.
Example 8
The present embodiment provides a trench IGBT, which is fabricated by using the fabrication method of embodiment 7, and has a structure shown in fig. 4, and includes an n-drift region 201, a p-type base region 202, an n+ source region 203, a p+ region 204, a p+ layer 206, an emitter E, a gate G, and a collector C. The p-type base region 202 is located on the n-drift region 201, a trench, an n+ source region 203 and a p+ region 204 are formed in the p-type base region 202, the p+ layer 206 is located below the n-drift region 201, the emitter E and the gate G (led out from the trench) are located on the front surface of the trench type IGBT, and the collector C is located on the back surface of the trench type IGBT.
Of course, the present invention is not limited to manufacturing IGBTs as shown in fig. 1-4, and other structures of IGBTs are equally applicable.
While specific embodiments of the invention have been described above, it will be appreciated by those skilled in the art that these are by way of example only, and the scope of the invention is defined by the appended claims. Various changes and modifications to these embodiments may be made by those skilled in the art without departing from the principles and spirit of the invention, but such changes and modifications fall within the scope of the invention.

Claims (11)

1. The IGBT manufacturing method is characterized in that the IGBT is a planar IGBT or a trench IGBT, and comprises the following steps:
manufacturing a front-side structure of the IGBT, wherein the manufacturing method comprises the steps of doping first ions in silicon to form a p+ region, and the diffusion coefficient of the first ions is higher than that of boron ions;
manufacturing a back structure of the IGBT;
the step of doping the silicon with the first ions is performed after the formation of the n+ source region and before the formation of the metal electrode;
wherein, for the planar IGBT, the p+ region is formed in the p-well of the planar IGBT and is positioned outside the n+ source region of the planar IGBT;
for the groove type IGBT, the p+ region is formed in a p-type base region of the groove type IGBT and is positioned outside an n+ source region of the groove type IGBT;
the IGBT manufacturing method further comprises the following steps:
and covering a layer of boron on the p+ region formed by doping the first ions.
2. The IGBT manufacturing method of claim 1 wherein doping the first ions comprises diffusing aluminum ions.
3. The IGBT manufacturing method of claim 2 wherein the temperature of the diffused aluminum ions is 1000 ℃ to 1300 ℃.
4. The method of manufacturing an IGBT of claim 3 wherein the temperature of the diffused aluminum ions is 1250 ℃.
5. The IGBT manufacturing method according to any one of claims 2 to 4, wherein aluminum ions are diffused for 14 hours so that the diffusion depth of aluminum ions reaches 250 μm; or, aluminum ions were diffused for 4 hours so that the diffusion depth of aluminum ions reached 25 μm.
6. The IGBT manufacturing method of claim 1 wherein doping the first ions includes implanting aluminum ions.
7. The IGBT fabrication method of claim 1 wherein doping the first ions comprises diffusing gallium ions.
8. The IGBT manufacturing method of claim 7 wherein the temperature of the diffused gallium ions is 800 ℃ to 1200 ℃.
9. The IGBT manufacturing method of claim 8 wherein the temperature of the diffused gallium ions is 1100 ℃.
10. The IGBT manufacturing method according to any one of claims 7 to 9, wherein gallium ions are diffused for 19 hours so that the diffusion depth of gallium ions reaches 60 μm.
11. An IGBT, characterized in that the IGBT is a planar IGBT or a trench IGBT, the IGBT being manufactured by the IGBT manufacturing method according to any one of claims 1 to 10.
CN201810712335.4A 2018-06-29 2018-06-29 IGBT manufacturing method and IGBT Active CN110660667B (en)

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Publication number Priority date Publication date Assignee Title
JP2006086414A (en) * 2004-09-17 2006-03-30 Fuji Electric Holdings Co Ltd Reverse blocking insulated gate semiconductor device and its manufacturing method
CN105957898A (en) * 2016-07-05 2016-09-21 安徽工业大学 Low-power consumption 4H-SiC voltage control-type power semiconductor device and preparation method thereof
CN107481929A (en) * 2016-06-08 2017-12-15 中芯国际集成电路制造(上海)有限公司 A kind of semiconductor devices and its manufacture method, electronic installation

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006086414A (en) * 2004-09-17 2006-03-30 Fuji Electric Holdings Co Ltd Reverse blocking insulated gate semiconductor device and its manufacturing method
CN107481929A (en) * 2016-06-08 2017-12-15 中芯国际集成电路制造(上海)有限公司 A kind of semiconductor devices and its manufacture method, electronic installation
CN105957898A (en) * 2016-07-05 2016-09-21 安徽工业大学 Low-power consumption 4H-SiC voltage control-type power semiconductor device and preparation method thereof

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