CN110660366A - Multi-core synchronous processing device and synchronous control method thereof - Google Patents
Multi-core synchronous processing device and synchronous control method thereof Download PDFInfo
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- CN110660366A CN110660366A CN201810696776.XA CN201810696776A CN110660366A CN 110660366 A CN110660366 A CN 110660366A CN 201810696776 A CN201810696776 A CN 201810696776A CN 110660366 A CN110660366 A CN 110660366A
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
Abstract
The invention discloses a synchronous control method which is suitable for controlling a plurality of processing sub-circuits to synchronously drive a display device. The processing sub-circuits define a master controller and a slave controller. The synchronization control method comprises the following steps: encoding a plurality of synchronous signals by the main controller to form an encoded synchronous signal; providing the encoded synchronization signal to the slave controller; encoding a plurality of control signals by the main controller to form an encoded control signal; providing the encoded control signal to the slave controller; and the master controller and the slave controller respectively drive different display areas of the display device to provide different parts of an image synchronously according to the coding synchronous signal and the coding control signal. The invention also discloses a multi-core synchronous processing device.
Description
Technical Field
The present invention relates to a multi-core processing apparatus and a control method thereof, and more particularly, to a multi-core synchronous processing apparatus and a synchronous control method thereof.
Background
With the development of technology, the functions of the current electronic products are becoming more complex to provide better experience for users, so that manufacturers must expend more effort in controlling or testing the electronic products. For example, in recent years, the resolution of video display is increasingly multiplied and new specifications are introduced into the market, so that the drawing core of the testing equipment needs to be modified again and again corresponding to new products corresponding to different specifications. However, since the core of the drawing is the heart of the product, once the core of the drawing changes, other related modules need to be changed, and thus a lot of complicated work is derived.
Generally, the core component of the testing device is a Field Programmable Gate Array (FPGA), and the mainstream architecture in the market at present is a single engine structure, if it is required to output high resolution, the internal operating frequency will be correspondingly increased, and higher-level components must be used. But this significantly increases the cost of testing and thus the cost of the product.
Disclosure of Invention
The invention provides a multi-core synchronous processing device and a synchronous control method, which can perform more complex test or control through the current architecture, thereby avoiding increasing the test cost.
The invention discloses a multi-core synchronous processing device which comprises a transmission module and an FPGA circuit. The FPGA circuit is electrically connected with the transmission module and is used for electrically connecting a display device. The FPGA circuit includes two processing sub-circuits. The processing sub-circuits define a master controller and a slave controller. The master controller and the slave controller are respectively electrically connected with the transmission module, the master controller is used for coding a plurality of control signals to form a coding control signal, the master controller is used for coding a plurality of synchronous signals to form a coding synchronous signal, and the master controller is used for providing the coding control signal and the coding synchronous signal to the slave controller through the transmission module. The master controller and the slave controller are used for respectively and synchronously driving different display areas of the display device to provide different parts of an image according to the coding control signal and the coding synchronous signal.
The invention discloses a synchronous control method which is suitable for controlling a plurality of processing sub-circuits to synchronously drive a display device. The processing sub-circuits define a master controller and a slave controller, and the synchronous control method comprises the following steps: encoding a plurality of synchronous signals by the main controller to form an encoded synchronous signal; providing the encoded synchronization signal to the slave controller; encoding a plurality of control signals by the main controller to form an encoded control signal; providing the encoded control signal to the slave controller; and the master controller and the slave controller respectively drive different display areas of the display device to provide different parts of an image synchronously according to the coding synchronous signal and the coding control signal.
The foregoing summary of the invention, as well as the following detailed description of the embodiments, is provided to illustrate and explain the principles and spirit of the invention, and to provide further explanation of the invention as claimed.
Drawings
FIG. 1A is a block diagram of a multi-core synchronous processing device according to an embodiment of the invention.
FIG. 1B is a flowchart illustrating steps of a synchronization control method according to an embodiment of the invention.
FIG. 2 is a functional block diagram of a processing sub-circuit according to an embodiment of the present invention.
FIG. 3 is a functional block diagram of a processing sub-circuit according to another embodiment of the present invention.
FIG. 4 is a functional block diagram of a processing sub-circuit according to yet another embodiment of the present invention.
FIG. 5 is a functional block diagram of a processing sub-circuit according to yet another embodiment of the present invention.
Wherein, the reference numbers:
1 Transmission Module
3 FPGA circuit
32a, 32b processing sub-circuit
321 processor
323 synchronizing signal generator
325 Coder
3251 mapping circuit
3253 LVDS conversion circuit
327 decoder
329 driving signal generator
DA multi-core synchronous processing device
DB display device
Detailed Description
The detailed features and advantages of the present invention are described in detail in the following embodiments, which are sufficient for those skilled in the art to understand the technical contents of the present invention and to implement the same, and the related objects and advantages of the present invention can be easily understood by those skilled in the art from the disclosure of the present specification, claims and drawings. The following examples further illustrate aspects of the present invention in detail, but are not intended to limit the scope of the present invention in any way.
Referring to fig. 1A, fig. 1A is a functional block diagram of a multi-core synchronous processing device according to an embodiment of the invention. As shown in fig. 1A, the multi-core synchronous processing device DA has a transmission module 1 and an FPGA circuit 3. The FPGA circuit 3 is electrically connected to the transmission module 1, and the FPGA circuit 3 is further electrically connected to a display device DB. The transmission module 1 is, for example, a bus (bus) or a hub (hub) with a compliant specification. The display device DB is, for example, a liquid crystal display or an organic light emitting diode display, and the type of the display device DB is not limited herein.
The FPGA circuit 3 comprises processing sub-circuits 32a, 32 b. In practice, the FPGA circuit 3 may include more than two processing sub-circuits, which are exemplified only by the processing sub-circuits 32a, 32 b. The processing sub-circuits 32a, 32b are, for example, a Graphics Processing Unit (GPU) and its related circuits. The processing sub-circuits 32a, 32b define a master controller (master) and a slave controller (slave). In this embodiment, the processing sub-circuit 32a is taken as a master controller and the processing sub-circuit 32b is taken as a slave controller for explanation.
Referring to fig. 1B, fig. 1B is a flowchart illustrating a synchronization control method according to an embodiment of the invention. The master controller (processing sub-circuit 32a) and the slave controller (processing sub-circuit 32b) are electrically connected to the transmission module 1, respectively. The main controller is used for encoding a plurality of synchronization signals to form an encoded synchronization signal (step S101), and the main controller is used for encoding a plurality of control signals to form an encoded control signal (step S103). The master controller is used for providing the encoding control signal and the encoding synchronization signal to the slave controller through the transmission module 1 (step S103 and step S107). The master controller and the slave controller are used for driving different display areas of the display device DB to provide different portions of an image respectively and synchronously according to the encoding control signal and the encoding synchronization signal (step S109). The synchronization signals are, for example, Hsync, Vsync, H-Display, V, Data-Enable, etc. signals commonly used in the art for controlling a Display panel to provide a picture, and the control signals are information related to the transmission timing, transmission buffer, or information required when each synchronization signal is used on the Display panel, such as zero delay (zero delay), buffer setting, or image setting. The foregoing is exemplary only and is not intended to be limiting.
The control signals are represented by a plurality of first bits (bits), and the encoded control signal is represented by a second bit that is less than the sum of the first bits of the control signals. The synchronous signals are respectively expressed by a plurality of third digits, and the coded synchronous signal is expressed by a fourth digit which is smaller than the sum of the third digits of the synchronous signals. Wherein each first digit may be the same or different and each third digit may be the same or different. In one embodiment, the first, second, third and fourth bits are all one bit. That is, in this embodiment, the master controller is configured to encode the plurality of control signals represented by one bit into a single encoded control signal represented by one bit, and the master controller is configured to encode the plurality of synchronization signals represented by one bit into a single encoded synchronization signal represented by one bit. That is, compared with transmitting the control signal or the synchronization signal, the FPGA circuit 3 can transmit the code control signal or the code synchronization signal with fewer input/output pins. In other words, in this architecture, the user can select the FPGA circuit 3 with fewer input/output pins, thereby reducing the hardware cost, but having the same performance.
Referring to fig. 2 again for a more detailed description of the multi-core synchronous processing device, fig. 2 is a functional block diagram of a processing sub-circuit according to an embodiment of the invention. In this embodiment, the processing sub-circuit 32a is described, but the processing sub-circuit 32b may have the same circuit configuration as the processing sub-circuit 32 a. In this embodiment, the processing sub-circuit 32a has a processor 321, a synchronization signal generator 323, an encoder 325, a decoder 327, and a driving signal generator 329. The processor 321 is electrically connected to the synchronization signal generator 323, and the processor 321 and the synchronization signal generator 323 are respectively electrically connected to the encoder 325. The driving signal generator 329 is electrically connected to the decoder 1247. The encoder 325 and the decoder 327 are electrically connected to the transmission module 1, respectively. In practice, the encoder 325 is electrically connected to the transmission module 1 through one or more pins of the FPGA circuit 3, and the decoder 327 is electrically connected to the transmission module 1 through another one or more pins of the FPGA circuit 3.
The processor 321 is configured to generate the control signals according to a first driving signal. The first driving signal is obtained by the processor 321 from an external device, for example. In practice, the user may provide the first driving signal to the processor 321 through customized software. The processor 321 is, for example, a Micro Controller Unit (MCU) or a Central Processing Unit (CPU).
The sync signal generator 323 is used for generating the sync signals according to the first driving signal. In one embodiment, the synchronization signal generator 323 obtains the first driving signal from the processor 321. In another embodiment, the synchronization signal generator 323 obtains the first driving signal from an external device similar to the processor 321.
The encoder 325 is used for encoding the control signals to generate encoded control signals, and the encoder 325 is used for encoding the synchronization signals to generate encoded synchronization signals. As mentioned above, the number of bits used to represent the encoded control signals is less than the total number of bits used to represent each control signal, and the number of bits used to represent the encoded synchronization signals is less than the total number of bits used to represent each synchronization signal.
The decoder 327 is used for decoding the encoded control signal provided by the transmission module 1 to obtain a plurality of decoded control signals, and is used for decoding the encoded synchronization signal provided by the transmission module 1 to obtain a plurality of decoded synchronization signals. The driving signal generator 329 is configured to generate a second driving signal according to the decoding control signal and the decoding synchronization signal obtained by the decoder 327, wherein the second driving signal is configured to provide an image corresponding to one of the plurality of display regions of the display device DB.
In one embodiment, the master controller and the slave controller in the FPGA circuit 3 have the architecture of fig. 2. In such an embodiment, the master controller provides the encoding control signal and the encoding synchronization signal to the transmission module 1, and the decoder 327 of the transmission module 1 provides the encoding control signal and the encoding synchronization signal to the master controller and the decoder 327 of the slave controller. In such an embodiment, all of the processing sub-circuits 32a, 32b in the FPGA circuit 3 can be defined as either master or slave depending on the needs of the user, providing considerable design flexibility for the user.
In practice, the processing sub-circuits 32a and 32b may also be provided with storage circuits, or the processing sub-circuits 32a and 32b may access data to the storage circuits in the FPGA circuit 3. The processing sub-circuits 32a and 32b can temporarily store the decoded data in the storage circuit, and then communicate with the main controller, and the main controller issues a driving start instruction to realize synchronous driving. The details of the related control can be freely designed by those skilled in the art after reading the present specification, and are not limited herein.
Referring to fig. 3, fig. 3 is a functional block diagram of a processing sub-circuit according to another embodiment of the invention. In the embodiment shown in fig. 3, the encoder 325 has a mapping circuit 3251 and a Low Voltage Differential Signaling (LVDS) converting circuit 3253. The mapping circuit 3251 is electrically connected to the processor 321 and the synchronization signal generator 323. The LVDS conversion circuit 3253 is electrically connected to the mapping circuit 3251 and is electrically connected to the transmission module 1.
The mapping circuit 3251 generates a first mapping signal according to each control signal and a first mapping table, and the mapping circuit 3251 generates a second mapping signal according to each synchronization signal and a second mapping table.
The LVDS conversion circuit 3253 is configured to LVDS encode the first mapping signal to generate an encoded control signal, and the LVDS conversion circuit 3253 is configured to LVDS encode the second mapping signal to generate an encoded synchronization signal. In other words, the encoded control signal includes one set of differential signals and the encoded synchronization signal includes another set of differential signals.
In the foregoing example, each control signal is represented by one bit, and the signal value of each control signal in one frequency cycle constitutes a first code (code). All bits of the first code are provided in parallel (parallel) to a mapping circuit 3251. The mapping circuit 3251 converts the first code into a second code (e.g., the aforementioned first mapping signal) according to the first lookup table, and provides the second code to the LVDS conversion circuit 3253. The LVDS conversion circuit 3253 generates a corresponding differential signal according to the second code and the LVDS code.
Therefore, the code control signal and the code synchronization signal have excellent anti-noise capability, so that the power noise, crosstalk (crosstalk) or other random noise can be resisted during transmission, and the transmission can be further carried out. In this embodiment, the decoder 327 has corresponding components or circuit structures for decoding the control signals and the synchronization signals before being encoded, relative to the mapping circuit 3251 and the LVDS conversion circuit 3253.
Referring to fig. 4 again, fig. 4 is a functional block diagram of a processing sub-circuit according to still another embodiment of the invention. In this embodiment, the processing sub-circuit 32a, defined as the main controller, has an architecture as shown in fig. 2 or fig. 3. Since the slave does not involve signal encoding, in this embodiment, the processing subcircuit 32b defined as the slave has an architecture as in fig. 4. The processing sub-circuit 32a has a decoder 327 and a driving signal generator 329. The connection and operation of the decoder 327 and the driving signal generator 329 are similar to those of the embodiment shown in fig. 3, and are not repeated herein. Thereby, the circuit architecture of the processing sub-circuit 32 is further simplified.
Referring to fig. 5, fig. 5 is a functional block diagram of a processing sub-circuit according to another embodiment of the invention. In this embodiment, the processing sub-circuit 32b defined as the slave may have the structure as shown in fig. 2 or 3, while the processing sub-circuit 32a defined as the master does not have the decoder 327 and the driving signal generator 329. Therefore, the processing sub-circuit 32a provides the encoding control signal and the encoding synchronization signal to the processing sub-circuit 32b through the transmission module 1, and the processing sub-circuit 32a drives the display device DB directly according to the control signal and the synchronization signal obtained from the external device.
In summary, the present invention provides a multi-core synchronous processing device and a synchronous control method, wherein a master controller generates a coded control signal and a coded synchronization signal, and a transmission module provides the coded control signal and the coded synchronization signal to a slave controller, so that the master controller and the slave controller can synchronously control a display device according to the coded control signal and the coded synchronization signal, and different areas of the display device synchronously display different portions of an image. Therefore, the multi-core synchronous processing device and the synchronous control method can control or test a large-size display panel under the condition of avoiding using a high-connection element.
Although the present invention has been described with reference to the above embodiments, it should be understood that various changes and modifications can be made therein by those skilled in the art without departing from the spirit and scope of the invention.
Claims (9)
1. A multi-core synchronous processing apparatus, comprising:
a transmission module; and
the FPGA circuit comprises two processing sub-circuits, a master controller and a slave controller are defined in the processing sub-circuits, the master controller and the slave controller are respectively electrically connected with the transmission module, the master controller is used for coding a plurality of control signals to form a coding control signal, the master controller is used for coding a plurality of synchronous signals to form a coding synchronous signal, the master controller is used for providing the coding control signal and the coding synchronous signal to the slave controller through the transmission module, and the master controller and the slave controller are used for respectively and synchronously driving different display areas of the display device to provide different parts of an image according to the coding control signal and the coding synchronous signal;
the control signals are respectively expressed by a plurality of first digits, the coding control signal is expressed by a second digit which is smaller than the sum of the first digits, the synchronous signals are respectively expressed by a plurality of third digits, the coding synchronous signal is expressed by a fourth digit which is smaller than the sum of the third digits.
2. The apparatus of claim 1, wherein a first processing sub-circuit of the processing sub-circuits comprises:
a processor for generating the control signals according to a first driving signal;
a synchronous signal generator electrically connected to the processor for generating the synchronous signals according to the first driving signal; and
the encoder is electrically connected with the processor and the synchronous signal generator, and is used for encoding the control signals to generate the encoding control signal and encoding the synchronous signals to generate the encoding synchronous signal.
3. The apparatus of claim 2, wherein the encoder comprises:
a mapping circuit electrically connected to the processor and the synchronization signal generator, the mapping circuit generating a first mapping signal according to the control signals and a first mapping table, and the mapping circuit generating a second mapping signal according to the synchronization signals and a second mapping table; and
a low voltage differential signal LVDS conversion circuit electrically connected to the mapping circuit, the LVDS conversion circuit is used for performing LVDS coding on the first mapping signal to generate the coding control signal, and the LVDS conversion circuit is used for performing LVDS coding on the second mapping signal to generate the coding synchronization signal;
the encoding control signal comprises one set of differential signals, and the encoding synchronization signal comprises another set of differential signals.
4. The apparatus according to claim 3, wherein one of the differential signals of the encoded control signal is represented by the second number of bits and one of the differential signals of the encoded synchronization signal is represented by the fourth number of bits.
5. The apparatus of claim 2, wherein the first of the processing sub-circuits further comprises:
a decoder electrically connected to the transmission module for decoding the encoding control signal provided by the transmission module to obtain a plurality of decoding control signals and for decoding the encoding synchronization signal provided by the transmission module to obtain a plurality of decoding synchronization signals; and
and the driving signal generator is electrically connected with the decoder and used for generating a second driving signal according to the decoding control signals and the decoding synchronous signals acquired by the decoder, and the second driving signal is used for correspondingly driving one of the display areas of the display device to provide images.
6. The apparatus of claim 2, wherein a second processing sub-circuit of the processing sub-circuits comprises:
a decoder electrically connected to the transmission module for decoding the encoding control signal provided by the transmission module to obtain a plurality of decoding control signals and for decoding the encoding synchronization signal provided by the transmission module to obtain a plurality of decoding synchronization signals; and
a driving signal generator electrically connected to the decoder for generating a second driving signal according to the decoding control signals and the decoding synchronization signals obtained by the decoder, the second driving signal being used for providing an image corresponding to one of the display regions of the display device;
wherein the second processing sub-circuit is defined as the slave controller.
7. A synchronous control method is suitable for controlling a plurality of processing sub-circuits to synchronously drive a display device, wherein a master controller and a slave controller are defined in the processing sub-circuits, and the synchronous control method comprises the following steps:
encoding a plurality of synchronous signals by the main controller to form an encoded synchronous signal;
providing the encoded synchronization signal to the slave controller;
encoding a plurality of control signals by the main controller to form an encoded control signal;
providing the encoded control signal to the slave controller; and
driving different display areas of the display device synchronously to provide different parts of an image by the master controller and the slave controller according to the coding synchronous signal and the coding control signal respectively;
the control signals are respectively expressed by a plurality of first digits, the coding control signal is expressed by a second digit which is smaller than the sum of the first digits, the synchronous signals are respectively expressed by a plurality of third digits, the coding synchronous signal is expressed by a fourth digit which is smaller than the sum of the third digits.
8. The synchronization control method according to claim 7, characterized by comprising:
obtaining the coding control signal and the coding synchronization signal from the main controller by a transmission module;
providing the coding control signal and the coding synchronization signal to the master controller and the slave controller respectively by the transmission module;
decoding the coding control signal and the coding synchronization signal provided by the transmission module by the main controller to obtain a plurality of decoding control signals and a plurality of decoding synchronization signals;
decoding the encoded control signal and the encoded synchronization signal provided by the transmission module by the slave controller to obtain another plurality of decoded control signals and another plurality of decoded synchronization signals; and
and synchronously driving different display areas of the display device to provide different parts of an image by the master controller and the slave controller according to the coding synchronous signals, the coding control signals, the other coding synchronous signals and the other coding control signals respectively.
9. The synchronization control method according to claim 7, characterized by comprising:
generating a first mapping signal according to the control signals and a first mapping table;
generating a second mapping signal according to the synchronization signals and a second mapping table;
performing Low Voltage Differential Signaling (LVDS) encoding on the first mapping signal to generate the encoding control signal; and
the second mapping signal is subjected to Low Voltage Differential Signaling (LVDS) encoding to generate the encoded synchronization signal.
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| CN1670806A (en) * | 2004-03-17 | 2005-09-21 | 京东方显示器科技公司 | Driving circuit for liquid crystal display device |
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| KR20110029979A (en) * | 2009-09-17 | 2011-03-23 | 주식회사 디지털존 | System and method for displaying synchronized video |
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Application publication date: 20200107 |