CN110649932B

CN110649932B - Wireless signal receiver

Info

Publication number: CN110649932B
Application number: CN201910870179.9A
Authority: CN
Inventors: 欧曦; 白俊华; 董俊丽; 王颢熹; 鲁显卓
Original assignee: Beijing Vip Infinite Intelligent Technology Co ltd
Current assignee: Beijing Vip Infinite Intelligent Technology Co ltd
Priority date: 2019-09-12
Filing date: 2019-09-12
Publication date: 2021-03-19
Anticipated expiration: 2039-09-12
Also published as: CN110649932A

Abstract

The embodiment of the invention relates to a wireless signal receiver, which is characterized by comprising: a storage module; an antenna; a wireless signal receiving module; a digital signal muting module; the micro-control processing module group comprises a micro-control main process processing module, a micro-control multi-code decoding module and a micro-control function execution module; the upper computer communication module group comprises a first upper computer communication module, a second upper computer communication module, a third upper computer communication module and a fourth upper computer communication module; a first data bus; a second data bus. The wireless signal receiver provided by the invention realizes the receiving and identification of multi-code system signals on one receiver, adds a digital signal noise suppression module which adopts code system signal logic judgment, improves the compatibility of equipment and reduces the cost of system equipment.

Description

Wireless signal receiver

Technical Field

The present invention relates to the field of wireless communication technologies, and in particular, to a wireless signal receiver.

Background

The wireless signal receiving equipment is widely used in the fields of internet of things, industrial production and manufacturing and even intelligent home. The problems of the common wireless signal receiving device in practical application are as follows: 1. because the distribution density is higher, the wireless signals in the working environment are greatly interfered, and the generated noise signals influence the receiving and processing of the wireless signal receiving equipment on the normal effective signals; 2. conventional wireless transceiver devices only support one signal code scheme, which results in multiple sets of wireless signal receivers being required for controlled remote devices in a multi-application scenario.

Disclosure of Invention

The present invention is directed to a wireless signal receiver, which overcomes the above-mentioned drawbacks. By using the wireless signal receiver provided by the invention, the purpose of multi-code system signal communication can be realized on one receiver, and compared with the original solutions of a plurality of sets of receiving equipment, the purchase, installation and maintenance costs of an application system on the wireless receiving equipment are reduced; the wireless signal receiver provided by the invention is additionally provided with the noise module which judges the signal by means of the code system signal logic besides the noise signal interception of the wireless signal, and the wireless signal receiver can more effectively avoid the error starting of the equipment working module caused by the noise signal and reduce the working power consumption of the equipment.

To achieve the above object, the present invention provides a wireless signal receiver, comprising: the system comprises a storage module, an antenna, a wireless signal receiving module, a digital signal muting module, a micro-control processing module group, an upper computer communication module group, a first data bus and a second data bus;

the storage module is used for storing a first signal energy parameter, a first signal average energy parameter, a first signal time parameter, a first signal average time parameter, a first code system signal total length parameter, a first code system synchronization signal high-low level ratio parameter, a first code system bit 0 signal high-low level ratio parameter, a first code system bit 1 signal high-low level ratio parameter, a current code system parameter, a modulation signal parameter recording file and a digital signal multi-code system parameter recording file required by the wireless signal receiving module, the digital signal muting module and the micro-control main flow processing module of the micro-control processing module group, the storage module is connected with the wireless signal receiving module through the first data bus, the digital signal muting module through the first data bus, and the micro-control main flow processing module of the micro-control processing module group through the first data bus, the second data bus is connected with the upper computer communication module group;

the antenna is used for receiving a first wireless signal sent by an external wireless signal sender, the antenna is connected with the wireless signal receiving module, and the antenna outputs the first wireless signal to the wireless signal receiving module;

the wireless signal receiving module is configured to perform a modulation signal digital signal conversion operation on the first wireless signal according to the first signal energy parameter, the first signal average energy parameter, the first signal time parameter, the first signal average time parameter, and the modulation signal parameter record file to generate a first digital signal, the wireless signal receiving module is connected to the antenna, the digital signal muting module, and the storage module through the first data bus, and the wireless signal receiving module performs a first digital signal output operation on the first digital signal to the digital signal muting module;

the digital signal squelch module is used for performing digital signal squelch operation on the first digital signal according to the current code system parameter, the total length parameter of the first code system signal, the length parameter of the first code system synchronous signal, the high-low level ratio parameter of the first code system bit 0 signal, the high-low level ratio parameter of the first code system bit 1 signal and the multi-code system parameter record file of the digital signal to generate a second digital signal, the digital signal squelch module is connected with the wireless signal receiving module, connected with the micro-control main process processing module of the micro-control processing module group and connected with the storage module through the first data bus, the digital signal squelch module outputs the second digital signal to the micro-control main flow processing module of the micro-control processing module group to perform a second digital signal output operation;

the micro-control processing module group comprises a micro-control main flow processing module, a micro-control multi-code decoding module and a micro-control function execution module;

the micro-control main process processing module is used for calling the micro-control multi-code system decoding module to perform digital signal decoding operation on the second digital signal according to the second digital signal, the current code system parameter and the digital signal multi-code system parameter recording file to generate a first instruction code text and calling the micro-control function execution module to perform instruction function execution operation according to the first instruction code text to generate a first instruction execution result, the micro-control main process processing module is connected with the digital signal muting module, the micro-control multi-code system decoding module, the micro-control function execution module and the storage module through the first data bus, the micro-control main process processing module performs decoding data input operation on the second digital signal, the current code system parameter and the digital signal multi-code system parameter recording file to the micro-control multi-code system decoding module and acquires the decoding data from the micro-control multi-code system decoding module The micro-control main process processing module inputs the first instruction code message to the micro-control function execution module and obtains a first instruction execution result from the micro-control function execution module;

the micro-control multi-code system decoding module is used for carrying out digital signal decoding operation on the second digital signal according to the current code system parameter and a digital signal multi-code system parameter recording file to generate the first instruction code text, the micro-control multi-code system decoding module is connected with the micro-control main flow processing module, and the micro-control multi-code system decoding module carries out first instruction code text output operation on the first instruction code text to the micro-control main flow processing module;

the micro-control function execution module is used for calling a function execution unit corresponding to the first instruction code text in the micro-control function execution module to perform instruction function execution operation according to the first instruction code text to generate a first instruction execution result, the micro-control function execution module is connected with the micro-control main flow processing module, and the micro-control function execution module performs first instruction execution result output operation on the first instruction execution result to the micro-control main flow processing module;

the upper computer communication module group is used for processing a data transmission task when an external upper computer performs setting operation on data stored in the storage module, and comprises a plurality of upper computer communication modules, the upper computer communication modules of the upper computer communication module group are respectively connected with the upper computer, and the upper computer communication modules of the upper computer communication module group are respectively connected with the storage module through the second data bus;

the first data bus is used for connecting the wireless signal receiving module, the digital signal muting module, the micro-control main process processing module of the micro-control processing module group and the storage module;

and the second data bus is used for connecting the upper computer communication module group and the storage module.

Further, in the above-mentioned case,

the modulated signal parameter recording file specifically includes: the method comprises the following steps of (1) antenna working frequency, modulation signal mode, total number of waveforms in unit signals, average energy smoothing calculation factor and average time smoothing calculation factor;

the digital signal multi-code system parameter recording file comprises a plurality of code system parameter records, and the code system parameter records comprise: code system identification, total signal length, synchronous signal high-low level ratio, bit 0 signal high-low level ratio, bit 1 signal high-low level ratio and unit bit level signal number;

the antenna is a unidirectional signal output side of the wireless signal receiving module;

the wireless signal receiving module is a unidirectional signal output side of the digital signal muting module;

the digital signal noise-suppressing module is specifically a one-way signal output side of the micro-control main process processing module of the micro-control processing module group;

when the second digital signals are not all low-level signals, the micro-control main process processing module of the micro-control processing module group is switched from a standby state to a working state;

after the micro-control function execution module completes the instruction function execution operation, the micro-control main process processing module of the micro-control processing module group is switched from the working state to the standby state.

Further, in the above-mentioned case,

the wireless signal receiving module is specifically configured to,

after the wireless signal receiving module acquires the first wireless signal from the antenna, the wireless signal receiving module acquires the first signal energy parameter, the first signal average energy parameter, the first signal time parameter, the first signal average time parameter and the modulated signal parameter record file from the storage module;

the wireless signal receiving module is used for carrying out unit signal energy and time judgment operation on the first wireless signal according to the first wireless signal, a first signal energy parameter, a first signal time parameter and a modulation signal parameter record file;

after the unit signal energy and time judgment is successfully executed, the wireless signal receiving module carries out signal average energy and time judgment operation on the first wireless signal according to the first wireless signal, a first signal average energy parameter, a first signal average time parameter and a modulation signal parameter record file;

after the signal average energy and time are judged to be successfully executed, the wireless signal receiving module performs modulation signal digital signal conversion operation on the first wireless signal to generate the first digital signal, and performs first digital signal output operation on the first digital signal to the digital signal muting module.

Preferably, the wireless signal receiving module performs a unit signal energy and time judgment operation on the first wireless signal according to the first wireless signal, the first signal energy parameter, the first signal time parameter, and the modulated signal parameter record file, and specifically includes:

step 41, the wireless signal receiving module initializes a value of the first index to 1, initializes a value of the first state to 0, and initializes a value of the second state to 0;

step 42, the wireless signal receiving module obtains the total number of waveforms in the unit signals of the modulation signal parameter record file to generate a first unit waveform number according to the modulation signal parameter record file;

step 43, the wireless signal receiving module performs rounding calculation on the quotient of the total waveform number of the first wireless signal divided by the number of the first unit waveforms to generate a first total number;

step 44, the wireless signal receiving module extracts a first index unit signal of the first wireless signal according to the first wireless signal to generate a first unit signal, where the total number of waveforms included in the first unit signal is specifically the number of the first unit waveforms;

step 45, the wireless signal receiving module performs signal energy calculation operation on the first unit signal according to the first unit signal in a carrier signal energy calculation mode to generate first unit signal energy, and performs signal time statistics on the first unit signal according to continuous waveform duration to generate first unit signal time;

step 46, the wireless signal receiving module determines whether the first unit signal energy is greater than or equal to the first signal energy parameter, if so, go to step 47, and if not, set the value of the first state to 1 and go to step 50;

step 47, the wireless signal receiving module determines whether the first unit signal time is greater than or equal to the first signal time parameter, if so, goes to step 48, and if not, sets the value of the second state to 1 and goes to step 50;

step 48, the wireless signal receiving module adds 1 to the value of the first index;

step 49, the wireless signal receiving module determines whether the value of the first index is greater than the value of the first total number, if the value of the first index is greater than the value of the first total number, go to step 50, and if the value of the first index is less than or equal to the value of the first total number, go to step 44;

and step 50, judging whether the execution of the unit signal energy and the time is successful when the values of the first state and the second state are both 0.

Preferably, the wireless signal receiving module performs a signal average energy and time judgment operation on the first wireless signal according to the first wireless signal, the first signal average energy parameter, the first signal average time parameter, and the modulated signal parameter record file, and specifically includes:

the wireless signal receiving module initializes the value of the third state to be 0 and initializes the value of the fourth state to be 0;

the wireless signal receiving module acquires the average energy smoothing calculation factor and the average time smoothing calculation factor of the modulation signal parameter record file according to the modulation signal parameter record file;

the wireless signal receiving module carries out signal average energy calculation operation on the first wireless signal according to the first wireless signal and an average energy smoothing calculation factor to generate first average energy;

the wireless signal receiving module carries out signal average time calculation operation on the first wireless signal according to the first wireless signal and the average time smooth calculation factor to generate first average time;

when the value of the first average energy is smaller than the value of the first signal average energy parameter, the wireless signal receiving module sets the value of the third state to 1;

when the value of the first average time is smaller than the value of the first signal average time parameter, the wireless signal receiving module sets the value of the fourth state to 1;

and when the values of the third state and the fourth state are both 0, judging that the execution of the signal average energy and the time is successful.

Further, in the above-mentioned case,

the digital signal squelch module is specifically configured to,

after the digital signal muting module acquires the first digital signal from the wireless signal receiving module, the digital signal muting module acquires a current code system parameter, a total length parameter of the first code system signal, a length parameter of a first code system synchronization signal, a high-low level ratio parameter of the first code system synchronization signal, a high-low level ratio parameter of a first code system bit 0 signal, a high-low level ratio parameter of a first code system bit 1 signal, and a digital signal multi-code system parameter recording file from the storage module;

the digital signal muting module performs digital signal total length verification operation on the first digital signal according to the current code system parameter, the first digital signal, the first code system signal total length parameter and the digital signal multi-code system parameter recording file;

after the total length check of the digital signal is successfully executed, the digital signal muting module performs synchronous signal high-low level ratio check operation on the first digital signal according to the current code system parameter, the first digital signal, the first code system synchronous signal length parameter, the first code system synchronous signal high-low level ratio parameter and the digital signal multi-code system parameter record file;

after the synchronous signal high-low level ratio verification is successfully executed, the digital signal muting module performs code signal high-low level ratio verification operation on the first digital signal according to the current code system parameter, the first digital signal, the first code system synchronous signal length parameter, the first code system bit 0 signal high-low level ratio parameter, the first code system bit 1 signal high-low level ratio parameter and the digital signal multi-code system parameter recording file;

after the code command signal high-low level ratio verification is successfully executed, the digital signal muting module extracts all waveform signals of the first digital signal to generate the second digital signal, and the second digital signal is output to the micro-control main flow processing module of the micro-control processing module group.

Preferably, the digital signal muting module performs a digital signal total length verification operation on the first digital signal according to the current coding parameter, the first digital signal, the first coding signal total length parameter, and the digital signal multi-coding parameter record file, and specifically includes:

the digital signal muting module acquires a code system parameter record corresponding to the current code system parameter in the digital signal multi-code system parameter record file to generate a first record according to the current code system parameter, and extracts the unit bit level signal number of the first record to generate a first unit level total number;

the digital signal muting module acquires the total number of level signals of the first digital signal according to the first digital signal to generate a first total number of levels;

the digital signal squelch module generates a first signal bit length according to the quotient of the first level total divided by the first unit level total;

when the value of the bit length of the first signal is equal to the value of the total length parameter of the first code system signal, the total length verification of the digital signal is successfully executed.

Preferably, the digital signal muting module performs a check operation on the high-low level ratio of the synchronization signal for the first digital signal according to the current code system parameter, the first digital signal, the length parameter of the first code system synchronization signal, the high-low level ratio of the first code system synchronization signal, and the digital signal multi-code system parameter record file, and specifically includes:

the digital signal muting module acquires code system parameter records corresponding to the current code system parameters in the digital signal multi-code system parameter record file to generate second records according to the current code system parameters, and extracts the unit bit level signal number of the second records to generate a second unit level total number;

the digital signal muting module extracts a section of continuous level signals from a first level signal to generate a first code system synchronization signal according to the first digital signal, wherein the total number of the level signals contained in the first code system synchronization signal is specifically the product of the total number of the level signals of the second unit and the length parameter of the first code system synchronization signal;

the digital signal muting module carries out statistical operation on the number of high level signals in the first code system synchronous signal according to the first code system synchronous signal to generate a first high level total number, and carries out statistical operation on the number of low level signals in the first code system synchronous signal to generate a first low level total number;

the digital signal squelch module generates a first high-low level ratio according to the ratio of the first high level total to the first low level total;

and when the first high-low level ratio is equal to the first code system synchronous signal high-low level ratio parameter, the synchronous signal high-low level ratio verification is successfully executed.

Preferably, the digital signal muting module performs code signal high-low level ratio verification operation on the first digital signal according to the current code system parameter, the first digital signal, the first code system synchronization signal length parameter, the first code system bit 0 signal high-low level ratio parameter, the first code system bit 1 signal high-low level ratio parameter, and the digital signal multi-code system parameter record file, and specifically includes:

step 91, initializing a value of a second index to be 1 and a value of a fifth state to be 0 by the digital signal muting module, and acquiring a value of a total number of level signals of the first digital signal to be a second total number;

step 92, the digital signal muting module acquires code system parameter records corresponding to the current code system parameters in the digital signal multi-code system parameter recording file to generate third records according to the current code system parameters, and extracts the unit bit level signal number of the third records to generate a third unit level total number;

step 93, the digital signal squelch module generates a first code order telecommunication signal start bit according to the sum of the product of the third unit level total number multiplied by the first code system synchronous signal length parameter and then 1;

step 94, the digital signal muting module extracts a section of continuous level signal from the level signal corresponding to the start bit of the first code telecommunication signal to the last level signal of the first digital signal according to the first digital signal to generate a first code signal;

step 95, the digital signal muting module extracts the second index bit signal of the first code signaling signal according to the first code signaling signal, where the total number of level signals included in the second index bit signal is specifically the total number of the level signals of the third unit;

step 96, the digital signal muting module performs a statistical operation on the number of high level signals in the second index bit signal to generate a second high level total number according to the second index bit signal, and performs a statistical operation on the number of low level signals in the second index bit signal to generate a second low level total number;

step 97, the digital signal muting module generates a second high-low level ratio according to the ratio of the second high level total to the second low level total;

step 98, when the second high-low level ratio is not equal to the first code system bit 0 signal high-low level ratio parameter, and the second high-low level ratio is not equal to the first code system bit 1 signal high-low level ratio parameter, the digital signal muting module sets the value of the fifth state to 1 and goes to step 101;

step 99, the digital signal muting module adds 1 to the value of the second index;

step 100, the digital signal muting module determines whether the value of the second index is greater than the value of the second total number, and if the value of the second index is greater than the value of the second total number, the process goes to step 101, and if the value of the second index is less than or equal to the value of the second total number, the process goes to step 95;

and 101, when the value of the fifth state is equal to 0, the code command signal is higher or lower than the verification success.

Further, in the above-mentioned case,

the upper computer communication module group comprises a first upper computer communication module, a second upper computer communication module, a third upper computer communication module and a fourth upper computer communication module.

The invention provides a wireless signal receiver, which specifically comprises: the device comprises a storage module, an antenna, a wireless signal receiving module, a digital signal muting module, a micro-control processing module group, an upper computer communication module group, a first data bus and a second data bus. The wireless signal receiving module provides two times of noise signal identification operation, the digital signal muting module provides three times of noise signal identification operation, and only after the received signal is confirmed to be a non-noise signal, the working state of the micro-control processing module group is switched from the standby state to the working state to complete command identification and function execution of the signal. In addition, the receiver provides a multi-code system parameter file, the upper computer can configure the configuration parameters of the receiver through various communication modes, and the identification capability of the receiver for other code system signals is switched by switching the parameters such as the current code system.

Drawings

Fig. 1 is a schematic diagram of a wireless signal receiver according to an embodiment of the present invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention clearer, the present invention will be described in further detail with reference to the accompanying drawings, and it is apparent that the described embodiments are only a part of the embodiments of the present invention, not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

Fig. 1 is a schematic diagram of a wireless signal receiver according to an embodiment of the present invention, and as shown in fig. 1, the wireless signal receiver according to the embodiment of the present invention includes: the device comprises a storage module 1, an antenna 2, a wireless signal receiving module 3, a digital signal muting module 4, a micro-control processing module group 5, an upper computer communication module group 6, a first data bus 7 and a second data bus 8, which are described in detail below.

The storage module 1 is used for storing a first signal energy parameter, a first signal average energy parameter, a first signal time parameter, a first signal average time parameter, a current code system parameter, a first code system signal total length parameter, a first code system synchronous signal high-low level ratio parameter, a first code system bit 0 signal high-low level ratio parameter, a first code system bit 1 signal high-low level ratio parameter, a modulation signal parameter recording file and a digital signal multi-code system parameter recording file required by the wireless signal receiving module 3, the digital signal muting module 4 and the micro-control main flow processing module 51 of the micro-control processing module group 5 through the first data bus 7, is connected with the upper computer communication module group 6 through a second data bus 8;

here, the modulated signal parameter recording file specifically includes: the method comprises the following steps of (1) antenna working frequency, modulation signal mode, total number of waveforms in unit signals, average energy smoothing calculation factor and average time smoothing calculation factor; the digital signal multi-code system parameter record file comprises a plurality of code system parameter records, and each code system parameter record comprises: code system identification, total signal length, synchronous signal high-low level ratio, bit 0 signal high-low level ratio, bit 1 signal high-low level ratio and unit bit level signal number.

The antenna 2 is configured to receive a first wireless signal sent by an external wireless signal transmitter, the antenna 2 is connected to the wireless signal receiving module 3, and the antenna 2 performs a first wireless signal output operation on the first wireless signal to the wireless signal receiving module 3, where the antenna 2 is specifically a unidirectional signal output side of the wireless signal receiving module 3.

The wireless signal receiving module 3 is configured to perform a modulation signal digital signal conversion operation on the first wireless signal according to the first signal energy parameter, the first signal average energy parameter, the first signal time parameter, the first signal average time parameter, and the modulation signal parameter record file to generate a first digital signal; the wireless signal receiving module 3 is connected with the antenna 2, the digital signal muting module 4 and the storage module 1 through a first data bus 7; the wireless signal receiving module 3 outputs the first digital signal to the digital signal muting module 4 for a first digital signal output operation, where the wireless signal receiving module 3 is specifically a unidirectional signal output side of the digital signal muting module 4.

In a specific implementation manner provided in this embodiment, the wireless signal receiving module 3 is specifically configured to, after the wireless signal receiving module 3 acquires the first wireless signal from the antenna 2, the wireless signal receiving module 3 acquires a first signal energy parameter, a first signal average energy parameter, a first signal time parameter, a first signal average time parameter, and a modulated signal parameter record file from the storage module 1;

the wireless signal receiving module 3 performs unit signal energy and time judgment operation on the first wireless signal according to the first wireless signal, the first signal energy parameter, the first signal time parameter and the modulated signal parameter record file, and the specific operation steps include:

step a1, the wireless signal receiving module 3 initializes the value of the first index to 1, initializes the value of the first state to 0, and initializes the value of the second state to 0;

step A2, the wireless signal receiving module 3 obtains the total number of waveforms in the unit signal of the modulated signal parameter record file to generate a first unit waveform number according to the modulated signal parameter record file;

step a3, the wireless signal receiving module 3 performs rounding calculation on the quotient of the total number of waveforms of the first wireless signal divided by the number of waveforms of the first unit to generate a first total number;

step a4, the wireless signal receiving module 3 extracts a first index unit signal of the first wireless signal according to the first wireless signal to generate a first unit signal, where the total number of waveforms included in the first unit signal is specifically the number of first unit waveforms;

step A5, the wireless signal receiving module 3, according to the first unit signal, performs signal energy calculation operation on the first unit signal according to the carrier signal energy calculation mode to generate first unit signal energy, and performs signal time statistics on the first unit signal according to the continuous waveform duration to generate first unit signal time;

step a6, the wireless signal receiving module 3 determines whether the first unit signal energy is greater than or equal to the first signal energy parameter, if the first unit signal energy is greater than or equal to the first signal energy parameter, step a7 is performed, if the first unit signal energy is less than the first signal energy parameter, the value of the first state is set to 1, and step a10 is performed;

step a7, the wireless signal receiving module 3 determines whether the first unit signal time is greater than or equal to the first signal time parameter, if the first unit signal time is greater than or equal to the first signal time parameter, step A8 is performed, if the first unit signal time is less than the first signal time parameter, the value of the second state is set to 1, and step a10 is performed;

step A8, the wireless signal receiving module 3 adds 1 to the value of the first index;

step a9, the wireless signal receiving module 3 determines whether the value of the first index is greater than the value of the first total number, if the value of the first index is greater than the value of the first total number, go to step a10, if the value of the first index is less than or equal to the value of the first total number, go to step a 4;

step A10, when the values of the first state and the second state are both 0, the unit signal energy and time judgment is successfully executed;

here, the wireless signal receiving module 3 performs the first noise signal interception processing on the first wireless signal: judging whether the single waveform signal is noise or not according to the energy value and the duration of the single waveform signal;

here, in another specific implementation manner provided in this embodiment, when the values of the first state and the second state are not all 0, it is stated that at least one of the energy detection and the time detection of the signal does not satisfy the non-noise determination requirement, the wireless signal receiving module 3 will exit the processing flow of the first wireless signal, and will not output any signal to the digital signal muting module 4, and the digital signal muting module 4 will not output a high-level working signal to the micro-control processing module group 5, and the micro-control processing module group 5 still remains in the standby state but in the non-working state;

after the unit signal energy and time judgment is successfully executed, the wireless signal receiving module 3 performs a signal average energy and time judgment operation on the first wireless signal according to the first wireless signal, the first signal average energy parameter, the first signal average time parameter, and the modulated signal parameter record file, and the specific operation steps include:

step B1, the wireless signal receiving module 3 initializes the value of the third state to 0 and initializes the value of the fourth state to 0;

step B2, the wireless signal receiving module 3 obtains the average energy smoothing calculation factor and the average time smoothing calculation factor of the modulated signal parameter recording file according to the modulated signal parameter recording file;

step B3, the wireless signal receiving module 3 performs signal average energy calculation operation on the first wireless signal according to the first wireless signal and the average energy smoothing calculation factor to generate a first average energy;

step B4, the wireless signal receiving module 3 performs signal average time calculation operation on the first wireless signal according to the first wireless signal and the average time smoothing calculation factor to generate a first average time;

step B5, when the value of the first average energy is smaller than the value of the first signal average energy parameter, the wireless signal receiving module 3 sets the value of the third state to 1;

step B6, when the value of the first average time is smaller than the value of the first signal average time parameter, the wireless signal receiving module 3 sets the value of the fourth state to 1;

step B7, when the values of the third state and the fourth state are both 0, the signal average energy and time are judged to be successfully executed;

here, the wireless signal receiving module 3 performs the second noise signal interception processing on the first wireless signal: judging noise according to the average energy value and the average time value of the full waveform signal;

here, in another specific implementation manner provided in this embodiment, when the values of the third state and the fourth state are not all 0, it is stated that at least one of the average energy detection and the average time detection of the signal does not satisfy the non-noise determination requirement, the wireless signal receiving module 3 will exit the processing flow of the first wireless signal, and will not output any signal to the digital signal muting module 4, and the digital signal muting module 4 will not output a high-level working signal to the micro-control processing module group 5, so that the micro-control processing module group 5 remains in the standby state but in the non-working state;

after the signal average energy and time judgment is successfully executed, the wireless signal receiving module 3 performs modulation signal digital signal conversion operation on the first wireless signal to generate a first digital signal, and performs first digital signal output operation on the first digital signal to the digital signal muting module 4.

The digital signal muting module 4 is configured to perform digital signal muting on the first digital signal according to the current code system parameter, the total length parameter of the first code system signal, the length parameter of the first code system synchronization signal, the high-low level ratio parameter of the first code system bit 0 signal, the high-low level ratio parameter of the first code system bit 1 signal, and the digital signal multi-code system parameter record file to generate a second digital signal; the digital signal noise-suppressing module 4 is connected with the wireless signal receiving module 3, the micro-control main flow processing module 51 of the micro-control processing module group 5 and the storage module 1 through the first data bus 7, and the digital signal noise-suppressing module 4 outputs a second digital signal to the micro-control main flow processing module 51 of the micro-control processing module group 5; here, the digital signal muting module 4 is specifically a one-way signal output side of the micro control main process processing module 51 of the micro control processing module group 5.

In another specific implementation manner provided in this embodiment, the digital signal muting module 4 is specifically configured to, after the digital signal muting module 4 acquires the first digital signal from the wireless signal receiving module 3, the digital signal muting module 4 acquires the current code system parameter, the total length parameter of the first code system signal, the length parameter of the first code system synchronization signal, the high-low level ratio parameter of the first code system bit 0 signal, the high-low level ratio parameter of the first code system bit 1 signal, and the digital signal multi-code system parameter record file from the storage module 1;

the digital signal muting module 4 performs a digital signal total length verification operation on the first digital signal according to the current code system parameter, the first digital signal, the first code system signal total length parameter, and the digital signal multi-code system parameter recording file, and the specific operation steps include:

step C1, the digital signal muting module 4 obtains the code system parameter record corresponding to the current code system parameter in the digital signal multi-code system parameter record file to generate a first record according to the current code system parameter, and extracts the number of unit bit level signals of the first record to generate the total number of the first unit level;

step C2, the digital signal muting module 4 obtains the total number of level signals of the first digital signal according to the first digital signal to generate a first total number of level signals;

step C3, the digital signal muting module 4 generates a first signal bit length according to the quotient of the first total level number divided by the first unit total level number;

step C4, when the bit length of the first signal is equal to the total length parameter of the first code system signal, the total length verification of the digital signal is successfully executed;

here, the digital signal muting module 4 performs the first noise signal interception processing on the first digital signal: for the receiver, the message length of the valid signal that can be identified is known, and here, the bit length of the all-digital waveform signal is performed on the first digital signal using known parameters (in a common use state, the message transmission mostly uses the code message, and the common code message indicates the bit value 0 or the bit value 1 by using different high-low level relations in a unit time unit, so that it is very normal that one bit contains multiple level signals);

here, in another specific implementation manner provided in this embodiment, when the value of the bit length of the first signal is not equal to the value of the total length parameter of the first code signal, which indicates that the total length of the digital signal does not satisfy the non-noise determination requirement, the digital signal muting module 4 will exit the processing flow of the first digital signal, and then the micro-control processing module group 5 will not output a high-level working signal to the micro-control processing module group 5, so that the micro-control processing module group 5 still remains in the standby state rather than the non-working state;

after the total length check of the digital signal is successfully executed, the digital signal muting module 4 performs the check operation of the high-low level ratio of the synchronous signal to the first digital signal according to the current code system parameter, the first digital signal, the length parameter of the first code system synchronous signal, the high-low level ratio of the first code system synchronous signal, and the digital signal multi-code system parameter record file, and the specific operation steps include:

step D1, the digital signal muting module 4 obtains the code system parameter record corresponding to the current code system parameter in the digital signal multi-code system parameter recording file to generate a second record according to the current code system parameter, and extracts the number of unit bit level signals of the second record to generate the total number of the second unit level;

step D2, the digital signal muting module 4 extracts a section of continuous level signal from the first level signal to generate a first code system synchronization signal according to the first digital signal, wherein the total number of level signals included in the first code system synchronization signal is specifically the product of the total number of level signals of the second unit and the length parameter of the first code system synchronization signal;

step D3, the digital signal muting module 4 generates a first high level total by performing a statistical operation on the number of high level signals in the first code system synchronization signal according to the first code system synchronization signal, and generates a first low level total by performing a statistical operation on the number of low level signals in the first code system synchronization signal;

step D4, the digital signal noise-suppressing module 4 generates a first high-low level ratio according to the ratio of the first high level total to the first low level total;

step D5, when the first high-low level ratio is equal to the first code system synchronous signal high-low level ratio parameter, the synchronous signal high-low level ratio check is successfully executed;

here, the digital signal muting module 4 performs the second noise signal interception processing on the first digital signal: for the receiver, the high-low level ratio relation of the synchronous signal of the identified effective signal is fixed and known, and the high-low level ratio check of the synchronous signal is carried out on the first digital signal through the known high-low level ratio parameter of the synchronous signal;

here, in another specific implementation manner provided in this embodiment, when the first high-low level ratio is not equal to the first code system synchronization signal high-low level ratio parameter, it is described that the synchronization signal high-low level ratio does not satisfy the non-noise determination requirement, the digital signal muting module 4 will exit the processing flow of the first digital signal, and no high-level working signal will be output to the micro-control processing module group 5 subsequently, and the micro-control processing module group 5 still remains in the standby state rather than the working state;

after the synchronous signal high-low level ratio verification is successfully executed, the digital signal muting module 4 performs code signal high-low level ratio verification operation on the first digital signal according to the current code system parameter, the first digital signal, the first code system synchronous signal length parameter, the first code system bit 0 signal high-low level ratio parameter, the first code system bit 1 signal high-low level ratio parameter and the digital signal multi-code system parameter recording file, and the specific operation steps include:

step E1, the digital signal muting module 4 initializes the value of the second index to 1, initializes the value of the fifth state to 0, and obtains the value of the total number of level signals of the first digital signal to be the second total number;

step E2, the digital signal muting module 4 obtains the code system parameter record corresponding to the current code system parameter in the digital signal multi-code system parameter record file to generate a third record according to the current code system parameter, and extracts the number of unit bit level signals of the third record to generate a third unit level total number;

step E3, the digital signal squelch module 4 multiplies the total number of the third unit level by the length parameter of the first code system synchronous signal and then adds 1 to generate the first code order telecommunication signal start bit;

step E4, the digital signal muting module 4 extracts a section of continuous level signal from the level signal corresponding to the start bit of the first code signaling telecommunication signal to the last level signal of the first digital signal according to the first digital signal to generate a first code signaling signal;

step E5, the digital signal muting module 4 extracts a second index bit signal of the first code signaling signal according to the first code signaling signal, where the total number of level signals included in the second index bit signal is specifically the total number of the level signals of the third unit;

step E6, the digital signal muting module 4 performs a statistical operation on the number of high level signals in the second index bit signal to generate a second high level total number, and performs a statistical operation on the number of low level signals in the second index bit signal to generate a second low level total number according to the second index bit signal;

step E7, the digital signal muting module 4 generates a second high-low level ratio according to the ratio of the second high level total to the second low level total;

step E8, when the second high-low level ratio is not equal to the first code system bit 0 signal high-low level ratio parameter and the second high-low level ratio is not equal to the first code system bit 1 signal high-low level ratio parameter, the digital signal muting module 4 sets the value of the fifth state to 1 and goes to step E11;

step E9, the digital signal muting module 4 adds 1 to the value of the second index;

step E10, the digital signal muting module 4 determines whether the value of the second index is greater than the value of the second total number, if the value of the second index is greater than the value of the second total number, go to step E11, and if the value of the second index is less than or equal to the value of the second total number, go to step E5;

step E11, when the value of the fifth state is equal to 0, the code makes the high-low level of the signal to be compared with the verification;

here, the digital signal muting module 4 performs the third time noise signal interception processing on the first digital signal: for the receiver, the high-low level ratio check of the bit 0 value or the bit 1 value in the code signal of the valid signal (the valid signal is composed of two signals of a synchronization signal and the code signal, wherein the synchronization signal is in charge of signal synchronization at the front end, and the code signal is a signal loaded with a specific instruction at the back end) that can be identified is fixed and known, and the high-low level ratio check of the code signal is to check the high-low level ratio relation in each bit digital signal of the first digital signal through the known high-low level ratio parameter of the synchronization signal with the bit 0 value or the bit 1 value; because the receiver supports multiple code systems, and the ratio of high and low levels in the bit of 0 value or 1 value of each code system is different, the corresponding record needs to be inquired in the parameter record file of the multiple code systems of the digital signal by using the parameter of the current code system during each check, and the ratio parameter of high and low levels of the bit 0 or 1 signal in the record is extracted as a standard value, and the value of the code system identifier of the corresponding record is always consistent with the value of the current code system;

here, in another specific implementation manner provided in this embodiment, when the value of the fifth state is not equal to 0, the instruction code makes the high-low level ratio of the signal not meet the non-noise determination requirement, the digital signal muting module 4 will exit the processing flow of the first digital signal, and then the micro-control processing module group 5 will not output a high-level working signal to the micro-control processing module group 5, and the micro-control processing module group 5 still remains in the standby state but in the non-working state;

after the code command signal high-low level ratio verification is successfully executed, the digital signal muting module 4 extracts all waveform signals of the first digital signal to generate a second digital signal, and outputs the second digital signal to the main micro-control program processing module 51 of the micro-control processing module group 5, and the main micro-control program processing module 51 enters a working state from a standby state after receiving a working high level input by the digital signal muting module 4.

The micro-control processing module group 5 comprises a micro-control main process processing module 51, a micro-control multi-code decoding module 52 and a micro-control function execution module 53;

the micro-control main flow processing module 51 is used for calling the micro-control multi-code system decoding module 52 to perform digital signal decoding operation on a second digital signal according to a second digital signal, a current code system parameter and a digital signal multi-code system parameter recording file to generate a first instruction code text and calling the micro-control function execution module 53 to perform instruction function execution operation according to the first instruction code text to generate a first instruction execution result, the micro-control main flow processing module 51 is connected with the digital signal muting module 4, the micro-control multi-code system decoding module 52, the micro-control function execution module 53 and the storage module 1 through a first data bus 7, the micro-control main flow processing module 51 performs decoding data input operation on the second digital signal, the current code system parameter and the digital signal multi-code system parameter recording file to the micro-control multi-code system decoding module 52 and acquires the first instruction code text from the micro-control multi-code system decoding module 52, the micro-control main process processing module 51 performs instruction code message input operation on the first instruction code message to the micro-control function execution module 53 and acquires a first instruction execution result from the micro-control function execution module 53;

the micro-control multi-code system decoding module 52 is used for performing digital signal decoding operation on the second digital signal according to the current code system parameter and the digital signal multi-code system parameter recording file to generate a first instruction code text, the micro-control multi-code system decoding module 52 is connected with the micro-control main process processing module 51, and the micro-control multi-code system decoding module 52 performs first instruction code text output operation on the first instruction code text to the micro-control main process processing module 51;

the micro-control function execution module 53 is configured to call, according to the first instruction code text, a function execution unit corresponding to the first instruction code text inside the micro-control function execution module 53 to perform an instruction function execution operation, so as to generate a first instruction execution result, the micro-control function execution module 53 is connected to the micro-control main process processing module 51, and the micro-control function execution module 53 performs a first instruction execution result output operation on the first instruction execution result to the micro-control main process processing module 51.

Here, the micro control main flow processing module 51 enters the operating state from the standby state after receiving the operating high level input thereto by the digital signal muting module 4; after acquiring the first instruction execution result from the micro-control function execution module, if the first instruction execution result is successful, the micro-control main process processing module 51 exits the current processing flow, and switches the micro-control processing module group 5 from the working state to the standby state; if the first instruction execution result is failure, further error information feedback operation is performed according to the specific requirements of the upper computer application system on error execution, after the error information feedback operation is finished, the micro-control main process processing module 51 exits the current processing flow, and the micro-control processing module group 5 is switched from the working state to the standby state;

host computer communication module group 6, a data transmission task when being used for handling the data of outside host computer to the inside storage of storage module 1 and setting up the operation, host computer communication module group 6 specifically includes first host computer communication module 61, second host computer communication module 62, third host computer communication module 63 and fourth host computer communication module 64, the first host computer communication module 61 of host computer communication module group 6, second host computer communication module 62, third host computer communication module 63 and fourth host computer communication module 64 are connected with the host computer respectively, the first host computer communication module 61 of host computer communication module group 6, second host computer communication module 62, third host computer communication module 63 and fourth host computer communication module 64 are connected with storage module 1 through second data bus 8 respectively. The first upper computer communication module is a Universal Serial Bus (USB) communication module, the second upper computer communication module is a Wireless Bluetooth (WBT) communication module, the third upper computer communication module is a Wireless local area network (Wi-Fi) communication module, and the fourth upper computer communication module is an expanded Wireless communication module;

in another specific implementation manner provided in this embodiment, the upper computer transmits the first storage data to the first upper computer communication module 61, after the first upper computer communication module 61 acquires the first storage data sent from the upper computer, the first storage data is sent to the storage module 1 through the second data bus 8, and after the storage module 1 completes receiving the first storage data, the storage module further completes writing operation on the first storage data in the internal storage space;

in another specific implementation manner provided in this embodiment, the upper computer transmits second storage data to the second upper computer communication module 62, after the second upper computer communication module 62 acquires the second storage data sent from the upper computer, the second storage data is sent to the storage module 1 through the second data bus 8, and after the storage module 1 completes receiving the second storage data, the storage module further completes writing operation on the second storage data in the internal storage space;

in another specific implementation manner provided in this embodiment, the upper computer transmits third storage data to the third upper computer communication module 63, the third upper computer communication module 63 transmits the third storage data to the storage module 1 through the second data bus 8 after acquiring the third storage data transmitted from the upper computer, and the storage module 1 further completes write operation of the third storage data in the internal storage space after completing reception of the third storage data;

in another specific implementation manner provided in this embodiment, the upper computer transmits fourth storage data to the fourth upper computer communication module 64, the fourth upper computer communication module 64 sends the fourth storage data to the storage module 1 through the second data bus 8 after acquiring the fourth storage data sent from the upper computer, and the storage module 1 further completes the write operation of the fourth storage data in the internal storage space after completing the reception of the fourth storage data.

And the first data bus 7 is used for connecting the wireless signal receiving module 3, the digital signal muting module 4, the micro-control main process processing module 51 of the micro-control processing module group 5 and the storage module 1.

And the second data bus 8 is used for connecting the upper computer communication module group 6 and the storage module 1.

The invention provides a wireless signal receiver, which specifically comprises: the device comprises a storage module, an antenna, a wireless signal receiving module, a digital signal muting module, a micro-control processing module group, an upper computer communication module group, a first data bus and a second data bus. The wireless signal receiving module provides two times of noise signal identification operation, the digital signal muting module provides three times of noise signal identification operation, and only after the received signal is confirmed to be a non-noise signal, the working state of the micro-control processing module group is switched from the standby state to the working state to complete command identification and function execution of the signal. In addition, the receiver provides a multi-code system parameter file, the upper computer can configure the configuration parameters of the receiver through various communication modes, and the identification capability of the receiver for other code system signals is switched by switching the parameters such as the current code system. By using the wireless signal receiver provided by the invention, the purpose of multi-code system signal communication can be realized on one receiver, and compared with the original solutions of a plurality of sets of receiving equipment, the purchase, installation and maintenance costs of an application system on the wireless receiving equipment are reduced; the wireless signal receiver provided by the invention is additionally provided with the noise module which judges the signal by means of the code system signal logic besides the noise signal interception of the wireless signal, and the wireless signal receiver can more effectively avoid the error starting of the equipment working module caused by the noise signal and reduce the working power consumption of the equipment.

Those of skill would further appreciate that the various illustrative components and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, computer software, or combinations of both, and that the various illustrative components and steps have been described above generally in terms of their functionality in order to clearly illustrate this interchangeability of hardware and software. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the implementation. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present invention.

The steps of a method or algorithm described in connection with the embodiments disclosed herein may be embodied in hardware, a software module executed by a processor, or a combination of the two. A software module may reside in Random Access Memory (RAM), memory, Read Only Memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art.

The above-mentioned embodiments are intended to illustrate the objects, technical solutions and advantages of the present invention in further detail, and it should be understood that the above-mentioned embodiments are merely exemplary embodiments of the present invention, and are not intended to limit the scope of the present invention, and any modifications, equivalent substitutions, improvements and the like made within the spirit and principle of the present invention should be included in the scope of the present invention.

Claims

1. A wireless signal receiver, the receiver comprising: the system comprises a storage module, an antenna, a wireless signal receiving module, a digital signal muting module, a micro-control processing module group, an upper computer communication module group, a first data bus and a second data bus;

the second data bus is used for connecting the upper computer communication module group and the storage module;

the wireless signal receiving module is specifically configured to, after the wireless signal receiving module acquires the first wireless signal from the antenna, acquire, by the wireless signal receiving module, the first signal energy parameter, the first signal average energy parameter, the first signal time parameter, the first signal average time parameter, and the modulated signal parameter record file from the storage module; the wireless signal receiving module is used for carrying out unit signal energy and time judgment operation on the first wireless signal according to the first wireless signal, a first signal energy parameter, a first signal time parameter and a modulation signal parameter record file; after the unit signal energy and time judgment is successfully executed, the wireless signal receiving module carries out signal average energy and time judgment operation on the first wireless signal according to the first wireless signal, a first signal average energy parameter, a first signal average time parameter and a modulation signal parameter record file; after the signal average energy and time are judged to be successfully executed, the wireless signal receiving module carries out modulation signal digital signal conversion operation on the first wireless signal to generate a first digital signal, and carries out first digital signal output operation on the first digital signal to the digital signal muting module;

the digital signal muting module is specifically configured to, after the digital signal muting module acquires the first digital signal from the wireless signal receiving module, acquire, from the storage module, a current code system parameter, a total length parameter of the first code system signal, a length parameter of the first code system synchronization signal, a high-low level ratio parameter of the first code system bit 0 signal, a high-low level ratio parameter of the first code system bit 1 signal, and a digital signal multi-code system parameter record file; the digital signal muting module performs digital signal total length verification operation on the first digital signal according to the current code system parameter, the first digital signal, the first code system signal total length parameter and the digital signal multi-code system parameter recording file; after the total length check of the digital signal is successfully executed, the digital signal muting module performs synchronous signal high-low level ratio check operation on the first digital signal according to the current code system parameter, the first digital signal, the first code system synchronous signal length parameter, the first code system synchronous signal high-low level ratio parameter and the digital signal multi-code system parameter record file; after the synchronous signal high-low level ratio verification is successfully executed, the digital signal muting module performs code signal high-low level ratio verification operation on the first digital signal according to the current code system parameter, the first digital signal, the first code system synchronous signal length parameter, the first code system bit 0 signal high-low level ratio parameter, the first code system bit 1 signal high-low level ratio parameter and the digital signal multi-code system parameter recording file; after the code command signal high-low level ratio verification is successfully executed, the digital signal muting module extracts all waveform signals of the first digital signal to generate the second digital signal, and the second digital signal is output to the micro-control main flow processing module of the micro-control processing module group.

2. The receiver of claim 1,

3. The receiver according to claim 2, wherein the wireless signal receiving module performs unit signal energy and time determination operation on the first wireless signal according to the first wireless signal, a first signal energy parameter, a first signal time parameter, and a modulated signal parameter record file, specifically comprising:

4. The receiver according to claim 2, wherein the wireless signal receiving module performs a signal average energy and time determination operation on the first wireless signal according to the first wireless signal, a first signal average energy parameter, a first signal average time parameter, and a modulated signal parameter record file, specifically comprising:

5. The receiver according to claim 2, wherein the digital signal muting module performs a digital signal total length check operation on the first digital signal according to the current coding parameter, the first digital signal, a first total length parameter of the coding signal, and a digital signal multi-coding parameter record file, and specifically comprises:

6. The receiver according to claim 2, wherein the digital signal muting module performs a synchronization signal high/low level ratio check operation on the first digital signal according to the current coding system parameter, the first digital signal, the first coding system synchronization signal length parameter, the first coding system synchronization signal high/low level ratio parameter, and the digital signal multi-coding system parameter record file, and specifically comprises:

7. The receiver according to claim 2, wherein the digital signal muting module performs a code signal high-low level ratio checking operation on the first digital signal according to the current code system parameter, the first digital signal, the first code system synchronization signal length parameter, the first code system bit 0 signal high-low level ratio parameter, the first code system bit 1 signal high-low level ratio parameter, and the digital signal multi-code system parameter record file, and specifically comprises:

8. The receiver of claim 1,