CN110649091B

CN110649091B - Semiconductor device, manufacturing method thereof and electronic device

Info

Publication number: CN110649091B
Application number: CN201810681835.6A
Authority: CN
Inventors: 金吉松; 毛明军
Original assignee: Semiconductor Manufacturing International Shanghai Corp; Semiconductor Manufacturing International Beijing Corp
Current assignee: Semiconductor Manufacturing International Shanghai Corp; Semiconductor Manufacturing International Beijing Corp
Priority date: 2018-06-27
Filing date: 2018-06-27
Publication date: 2024-02-27
Anticipated expiration: 2038-06-27
Also published as: CN110649091A

Abstract

The invention provides a semiconductor device, a manufacturing method thereof and an electronic device, comprising: providing a semiconductor substrate, wherein a grid groove is formed on the semiconductor substrate; sequentially forming a high-k dielectric layer and a work function layer on the bottom and the side wall of the grid groove; forming an etching barrier layer to fill the gate groove, wherein the top surface of the etching barrier layer is lower than the top surfaces of the high-k dielectric layer and the work function layer; etching to remove part of the work function layer by taking the etching barrier layer as a barrier layer, so that the top surface of the work function layer is flush with the top surface of the etching barrier layer; removing a portion of the high-k dielectric layer to make the top surface of the high-k dielectric layer flush with the top surface of the work function layer; and removing the etching barrier layer. The method of the invention realizes the partial removal of the high-k dielectric layer, so that the high-k dielectric layer between the metal gate structure and the contact hole connecting the source electrode and the drain electrode is reduced, the capacitance is reduced, and the device performance is improved.

Description

Semiconductor device, manufacturing method thereof and electronic device

Technical Field

The present invention relates to the field of semiconductor technology, and in particular, to a semiconductor device, a method for manufacturing the same, and an electronic apparatus.

Background

In the field of integrated circuit fabrication, as the size of MOS transistors is continuously reduced, the physical limits of devices have increasingly greater impact on device fabrication, and scaling down the feature sizes of devices has become more difficult, wherein the problem of leakage from the gate to the substrate is likely to occur in the field of MOS transistor and its circuit fabrication.

The current approach to solving the above problems is to use high-K metal gates in the semiconductor devices instead of conventional polysilicon gate structures. However, the conventional metal gate structure includes a high-k dielectric layer formed on the bottom and the sidewall of the recess and a gate layer filled with the recess, and metal contact holes are typically formed on the source and the drain of the semiconductor device to lead the source and the drain out, so that a high-k dielectric layer is sandwiched between the gate layer and the metal contact holes to make the capacitance relatively high, so that the high-k dielectric layer is considered to be etched back when the metal gate is etched back in the current process, but the material properties of the high-k dielectric layer and the material properties of the work function layer of the metal gate are different, so that the etching challenge is great, and the common method is to bombard the high-k dielectric layer with Ar plasma, but so that the work function of the metal gate such as TiN is bombarded, so that the effective work function shifts, thereby affecting the performance of the device. Therefore, there is a need to propose a new method for manufacturing a semiconductor device to solve the above-mentioned technical problems.

Disclosure of Invention

In the summary, a series of concepts in a simplified form are introduced, which will be further described in detail in the detailed description. The summary of the invention is not intended to define the key features and essential features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter.

In view of the problems existing at present, an aspect of the present invention provides a method for manufacturing a semiconductor device, including:

providing a semiconductor substrate, wherein a grid groove is formed on the semiconductor substrate;

sequentially forming a high-k dielectric layer and a work function layer on the bottom and the side wall of the grid groove;

forming an etching barrier layer to fill the gate groove, wherein the top surface of the etching barrier layer is lower than the top surfaces of the high-k dielectric layer and the work function layer;

etching to remove part of the work function layer by taking the etching barrier layer as a barrier layer, so that the top surface of the work function layer is flush with the top surface of the etching barrier layer;

removing a portion of the high-k dielectric layer to make the top surface of the high-k dielectric layer flush with the top surface of the work function layer;

and removing the etching barrier layer.

Illustratively, the method further comprises the step of annealing prior to forming the etch stop layer or after forming the etch stop layer.

Illustratively, after forming the work function layer, before forming the etch stop layer, further comprising: and forming a protective layer on the surface of the work function layer.

Illustratively, after forming the protective layer before forming the etch stop layer, further comprising: and (3) performing annealing treatment.

Illustratively, when the material of the etch stop layer comprises an oxide, the method further comprises, prior to forming the etch stop layer, the steps of: and removing the protective layer.

Illustratively, prior to the step of removing a portion of the work function layer, further comprising the steps of: and etching back and removing part of the protective layer until the top surface of the protective layer is flush with the surface of the etching barrier layer.

Illustratively, where the material of the etch stop layer comprises an oxide, the etch stop layer is removed at the same time as the high-k dielectric layer is removed using a wet etch.

Illustratively, prior to forming the gate recess, further comprising the steps of:

forming a dummy gate structure in a region of the semiconductor substrate where a metal gate structure is predetermined to be formed;

Forming an interlayer dielectric layer to cover the semiconductor substrate and the dummy gate structure;

flattening the interlayer dielectric layer to stop on the surface of the pseudo gate structure;

and removing the pseudo gate structure to form the gate groove.

Illustratively, before planarizing the interlayer dielectric layer, the method further comprises the steps of: and nitriding the interlayer dielectric layer with partial thickness.

Illustratively, the nitridation process uses a decoupled plasma doping technique or a method using plasma implantation of N.

Illustratively, after the step of planarizing the interlayer dielectric layer, the method further comprises the steps of:

etching back the interlayer dielectric layer so that the top surface of the interlayer dielectric layer is lower than the top surface of the pseudo gate structure;

an etch stop layer is formed on a surface of the interlayer dielectric layer, wherein a top surface of the etch stop layer and a top surface of the dummy gate structure are flush.

Illustratively, the material of the etch stop layer comprises amorphous silicon or silicon oxide; the material of the protective layer comprises amorphous silicon.

The invention also provides a semiconductor device prepared by the manufacturing method.

In another aspect, the present invention also provides an electronic apparatus including the semiconductor device described above.

In summary, the method for manufacturing the high-k dielectric layer in the invention forms the etching barrier layer in the gate groove as the barrier layer in etching the work function layer, thereby realizing etching of the work function layer, and then removing part of the high-k dielectric layer to enable the top surfaces of the high-k dielectric layer and the work function layer to be flush, further realizing partial removal of the high-k dielectric layer, reducing the high-k dielectric layer between the metal gate structure and the contact hole connecting the source electrode and the drain electrode, reducing the capacitance and improving the device performance.

Drawings

The following drawings are included to provide an understanding of the invention and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and their description to explain the principles of the invention.

In the accompanying drawings:

FIG. 1A shows a schematic cross-sectional view of a conventional metal gate structure;

fig. 1B shows a scanning electron microscope image of a conventional semiconductor device having a metal gate structure;

Fig. 2A to 2F are schematic cross-sectional views showing a semiconductor device manufacturing method according to an embodiment of the present invention, which is sequentially performed to obtain the device;

fig. 3A to 3E are schematic cross-sectional views showing a semiconductor device manufacturing method according to another embodiment of the present invention, which is sequentially performed to obtain a device;

fig. 4 is a schematic perspective view showing a device obtained when a method of manufacturing a semiconductor device according to another embodiment of the present invention is performed;

fig. 5A to 5F are schematic cross-sectional views showing a semiconductor device manufacturing method according to still another embodiment of the present invention, which is sequentially performed to obtain the device;

fig. 6 is a flowchart showing a method of manufacturing a semiconductor device according to an embodiment of the present invention;

fig. 7 shows a schematic diagram of an electronic device according to an embodiment of the invention.

Detailed Description

In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present invention. It will be apparent, however, to one skilled in the art that the invention may be practiced without one or more of these details. In other instances, well-known features have not been described in detail in order to avoid obscuring the invention.

It should be understood that the present invention may be embodied in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the size of layers and regions, as well as the relative sizes, may be exaggerated for clarity. Like numbers refer to like elements throughout.

It will be understood that when an element or layer is referred to as being "on," "adjacent," "connected to," or "coupled to" another element or layer, it can be directly on, adjacent, connected, or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.

Spatially relative terms, such as "under," "below," "beneath," "under," "above," "over," and the like, may be used herein for ease of description to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements or features described as "under" or "beneath" other elements would then be oriented "on" the other elements or features. Thus, the exemplary terms "below" and "under" may include both an upper and a lower orientation. The device may be otherwise oriented (rotated 90 degrees or other orientations) and the spatially relative descriptors used herein interpreted accordingly.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.

Embodiments of the invention are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the invention. In this way, variations from the illustrated shape due to, for example, manufacturing techniques and/or tolerances, are to be expected. Thus, embodiments of the present invention should not be limited to the particular shapes of the regions illustrated herein, but rather include deviations in shapes that result, for example, from manufacturing. For example, an implanted region shown as a rectangle typically has rounded or curved features and/or implant concentration gradients at its edges rather than a binary change from implanted to non-implanted regions. Also, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface over which the implantation is performed. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the present invention.

In order to provide a thorough understanding of the present invention, detailed steps and structures will be presented in the following description in order to illustrate the technical solution presented by the present invention. Preferred embodiments of the present invention are described in detail below, however, the present invention may have other embodiments in addition to these detailed descriptions.

As shown in fig. 1A, the conventional metal gate structure includes a high-k dielectric layer 1021 and a metal gate work function layer 1022, which are sequentially formed on the bottom and the sidewall of the recess, and a gate layer 1023 filled with the recess, and for the FinFET device, a metal gate structure is formed on the fin 101, and as shown in fig. 1B, metal contact holes (CT) are typically formed on the source and the drain of the semiconductor device to lead the source and the drain out, so that a high-k dielectric layer (HK) is sandwiched between the gate layer and the metal contact holes to make the capacitance relatively high, so that the high-k dielectric layer 1021 is also considered to be etched back when the metal gate is etched back in the current process, but the material properties of the high-k dielectric layer 1021 and the material properties of the metal gate layer are different, so that the etching challenges are great, and the conventional method is to bombard the high-k dielectric layer with Ar plasma, but so that the work function of the metal gate such as TiN is bombarded to be effective, so that the work function of the metal gate is drifting, thereby affecting the performance of the device.

In view of the above technical problems, the present invention provides a method for manufacturing a semiconductor device, as shown in fig. 6, mainly comprising the following steps:

step S1, providing a semiconductor substrate, wherein a grid groove is formed on the semiconductor substrate;

Step S2, sequentially forming a high-k dielectric layer and a work function layer on the bottom and the side wall of the grid groove;

step S3, forming an etching barrier layer to fill the grid groove, wherein the top surface of the etching barrier layer is lower than the top surfaces of the high-k dielectric layer and the work function layer;

s4, taking the etching barrier layer as a barrier layer to etch and remove part of the work function layer, so that the top surface of the work function layer is flush with the top surface of the etching barrier layer;

s5, removing part of the high-k dielectric layer to enable the top surface of the high-k dielectric layer to be flush with the top surface of the work function layer;

and S6, removing the etching barrier layer.

Example 1

Next, a method of manufacturing the semiconductor device of the present invention will be described in detail with reference to fig. 2A to 2F.

First, as shown in fig. 2A, a semiconductor substrate (not shown) on which a gate groove 202A is formed is provided.

The semiconductor substrate in the present invention may be at least one of the following mentioned materials: silicon, silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-on-insulator (S-SiGeOI), silicon-on-insulator (SiGeOI), germanium-on-insulator (GeOI), and the like. Isolation structures, either Shallow Trench Isolation (STI) structures or local oxide silicon (LOCOS) isolation structures, are also formed in the semiconductor substrate. Various well (well) structures and channel layers on the substrate surface are also formed in the semiconductor substrate. Generally, the ion doped conductivity type of the well (well) structure is the same as that of the channel layer, but the concentration is lower than that of the gate channel layer, the ion implantation depth is wider, and the depth of the isolation structure is required to be larger than that of the isolation structure. For simplicity, the illustration is omitted.

For convenience of explanation and explanation of the technical solutions of the present application, finFET devices are mainly taken as examples in the embodiments herein, and for convenience of understanding of the positional relationship between the fin structure and the metal gate structure in the drawings referred to herein, the fin structure 201 is also shown in a schematic cross-sectional view, but the fin structure is not actually cut in the schematic cross-sectional view of the metal gate structure outside the sidewalls of the fin structure, as a schematic cross-sectional view taken along the section line AA' in fig. 4.

In one example, when the semiconductor device is a FinFET device, the fin structure 201 is formed on the semiconductor substrate, where the fin structure 201 is a pillar structure formed on the semiconductor substrate, and a plurality of fin structures may be formed on the semiconductor substrate, where the fin structures have the same width, or the fins are divided into a plurality of fin structure groups having different widths, and the lengths of the fin structures may also be different.

Specifically, the forming method of the fin structure is not limited to a certain method, and an exemplary forming method is given below: forming a hard mask layer (not shown) on the semiconductor substrate, wherein the hard mask layer may be formed by various suitable processes known to those skilled in the art, such as a chemical vapor deposition process, and the hard mask layer may be a bottom-up stacked oxide layer and a silicon nitride layer; patterning the hard mask layer to form a plurality of isolated masks for etching the semiconductor substrate to form fins thereon, the patterning being performed using a self-aligned double pattern (SADP) process in one embodiment; the semiconductor substrate is etched to form fin structures thereon.

In one example, after forming the fin structures, isolation structures (not shown) are formed on the semiconductor substrate outside of the fin structures 201, with the top surfaces of the isolation structures being lower than the top surfaces of the fin structures.

Specifically, a layer of isolation material is deposited to completely fill the gaps between the fin structures. In one embodiment, the deposition is performed using a flowable chemical vapor deposition process. The material of the isolation material layer may be selected from an oxide, such as a High Aspect Ratio Process (HARP) oxide, in particular silicon oxide. And etching back the isolation material layer to the target height of the fin structure to form an isolation structure. Specifically, the isolation material layer is etched back to expose a portion of the fins, thereby forming fins having a specific height.

In one example, after forming the isolation structure, further comprising forming a dummy gate structure on the isolation structure across the fin, wherein the dummy gate structure comprises a dummy gate dielectric layer and a dummy gate material layer. Wherein the dummy gate dielectric layer may be formed of a common oxide such as SiO ₂ The dummy gate material layer may be a semiconductor material commonly used in the art, for example, polysilicon, etc., and is not limited to a specific one, and is not listed here.

It is noted that the term "straddling", for example, a dummy gate structure straddling a fin structure, as used in the present invention means that the dummy gate structure is formed on both the upper surface and the side of a portion of the fin structure, and the dummy gate structure is also formed on a portion of the surface of the semiconductor substrate. The explanation of "straddling" herein applies equally to the metal gate structures and the like that are straddling fin structures, as referred to below.

The dummy gate structure may be formed using any suitable method known to those skilled in the art, and is not described in detail herein.

In one example, offset spacers may also be formed on the sidewalls of the dummy gate structure. Specifically, the offset sidewall may be one of silicon oxide, silicon nitride, silicon oxynitride or a combination thereof, and a Spacer (Spacer) is formed on the formed offset sidewall, where the Spacer may be one of silicon oxide, silicon nitride, silicon oxynitride or a combination thereof.

In one example, after the dummy gate structure is formed, source-drain ion implantation may be further performed to form a source and a drain in the fin on both sides of the dummy gate structure, and the specific type of implanted ions may be reasonably selected according to the type of the actual device.

An interlayer dielectric layer (not shown) may then be formed to cover the semiconductor substrate and the dummy gate structure, and planarized to stop on top of the dummy gate structure.

Wherein the interlayer dielectric layer can be made of dielectric materials commonly used in the art, such as various oxides, etc., and in this embodiment, siO ₂ The thickness thereof is not limited to a certain value.

Non-limiting examples of the planarization process include a mechanical planarization method and a chemical mechanical polishing planarization method.

In one example, before planarizing the interlayer dielectric layer, the method further comprises the steps of: and nitriding the interlayer dielectric layer with partial thickness to reduce the etching rate of the interlayer dielectric layer when the high-k dielectric layer is removed by wet etching, so as to avoid damage to the interlayer dielectric layer outside the grid groove.

Illustratively, the bottom of the nitrided portion of the interlayer dielectric layer is below the top surface of the dummy gate structure to ensure that the nitrided interlayer dielectric layer remains after planarization of the interlayer dielectric layer.

In one example, the nitridation process may be performed by any suitable method known to those skilled in the art, wherein preferably the nitridation process uses a decoupled plasma Doping (DPN) technique or a method using plasma implantation N.

In one example, the gate recess 202a is formed by removing the dummy gate structure.

Next, step two is performed, as shown in fig. 2A, a high-k dielectric layer 2021 and a work function layer 2022 are sequentially formed on the bottom and the sidewalls of the gate recess 202A.

Optionally, before forming the high-k dielectric layer 2021, a step of forming an interface layer (not shown) at the bottom of the gate recess 202a is further included.

The Interface (IL) layer is formed of a material including silicon oxide (SiOx) and functions to improve interface characteristics between the high-k dielectric layer and the semiconductor substrate. The IL layer may be a thermal oxide layer, a nitrogen oxide layer, a chemical oxide layer, or other suitable thin film layer. The interfacial layer may be formed using a suitable process such as thermal oxidation, chemical Vapor Deposition (CVD), atomic Layer Deposition (ALD), or Physical Vapor Deposition (PVD). The interfacial layer has a thickness in the range of 5 angstroms to 10 angstroms.

The high-k dielectric layer 2021 has a k value (dielectric constant) of usually 3.9 or more, and constituent materials thereof include hafnium oxide, hafnium silicon oxynitride, lanthanum oxide, zirconium silicon oxide, titanium oxide, tantalum oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, aluminum oxide, and the like, preferably hafnium oxide, zirconium oxide, or aluminum oxide. The high-k dielectric layer 2021 may be formed using a suitable process such as Chemical Vapor Deposition (CVD), atomic Layer Deposition (ALD), or Physical Vapor Deposition (PVD). The high-k dielectric layer 2021 has a thickness in a range of 10 angstroms to 30 angstroms.

Optionally, after forming the high-k dielectric layer 2021, the high-k dielectric layer 2021 may be further annealed. The annealing treatment may be any suitable annealing method known to those skilled in the art, such as rapid thermal annealing, furnace tube annealing, and the like. For example, using atomic layer deposition to deposit hafnium oxide as the high-k dielectric layer 2021, in order to obtain a pure crystalline structure of hafnium oxide, the high-k dielectric layer needs to be annealed, for example, at 400-600 ℃ for 30-600 s, which is called Post Deposition Anneal (PDA).

The material of the work function layer 2022 may be selected from, but is not limited to, tixN1-x, taC, moN, taN or combinations thereof or other suitable thin film layers. Wherein TiN may be used as the material of the work function layer 2022. The work function layer 2022 may be formed by a suitable process such as CVD, ALD, or PVD. The thickness of the work function layer 2022 ranges from 10 angstroms to 580 angstroms.

Next, step three is performed, as shown in fig. 2C, an etch stop layer 204 is formed to fill a portion of the gate recess, wherein the top surface of the etch stop layer 204 is lower than the top surfaces of the high-k dielectric layer 2021 and the work function layer 2022.

In one example, as shown in fig. 2A, after the work function layer 2022 is formed and before the etching stopper layer is formed, a step of forming a protective layer 203 on a surface of the work function layer 2022 may be further optionally performed, where the protective layer 203 is formed by conformal deposition, and the protective layer 203 is used to protect the work function layer during a subsequent annealing process.

The material of the protective layer 203 is an amorphous semiconductor material. The amorphous semiconductor material includes amorphous silicon (a-Si) or amorphous germanium (a-Ge), but may be any other suitable amorphous semiconductor material, and in this embodiment, the material of the protective layer preferably includes a-Si.

Methods of forming the protective layer include Chemical Vapor Deposition (CVD), such as Low Temperature Chemical Vapor Deposition (LTCVD), low Pressure Chemical Vapor Deposition (LPCVD), rapid thermal chemical vapor deposition (LTCVD), plasma chemical vapor deposition (PECVD), and generally similar methods such as sputtering and Physical Vapor Deposition (PVD) may also be used.

The thickness of the protective layer is in the range of 40 a to 120 a, and may be any other suitable thickness, and is not particularly limited herein.

The material of the etch stop layer 204 may be any suitable material, for example, the material of the etch stop layer 204 is an amorphous semiconductor material. The amorphous semiconductor material includes amorphous silicon (a-Si) or amorphous germanium (a-Ge), but may be any other suitable amorphous semiconductor material, and in this embodiment, the material of the etching stopper 204 preferably includes a-Si.

Alternatively, the etch stop layer 204 and the protective layer 203 may use the same material, e.g., each comprising a-Si.

In one example, a method of forming the etch stop layer 204 to fill a portion of the gate recess 202a includes the steps of: first, as shown in fig. 2B, an etch stop layer 204 is deposited to fill the gate recess 202a and overflow over the gate recess 202 a. The etch stop layer 204 may also be selectively planarized to stop on top of the gate recess. The planarization may be any suitable planarization method, such as chemical mechanical polishing, and the like. Next, as shown in fig. 2C, a portion of the etching stopper 204 is etched back to a target height, wherein when the protection layer and the etching stopper 204 are made of the same material, a step of simultaneously etching back the protection layer 203 is further included. Wherein the target height of the etch stop layer 204, i.e. the target height of the high-k dielectric layer and the work function layer. The etching back may use any suitable dry etching or wet etching method, and is not particularly limited herein.

In one example, the annealing treatment may also be performed after the formation of the protective layer 203, before the formation of the etch stop layer 204, or after the formation of the etch stop layer, for example, the annealing treatment may be a PCA annealing, wherein the purpose of the annealing treatment is to remove excess oxygen in the high-k dielectric layer.

Alternatively, the annealing process may be performed at a temperature ranging from 900 ℃ to 1100 ℃, as well as other suitable temperatures.

The annealing process may use any suitable annealing method, such as furnace annealing, spike annealing (spike annealing), laser annealing (laser annealing), pulsed electron beam rapid annealing, ion beam rapid annealing, continuous wave laser rapid annealing, and incoherent broadband light source (e.g., halogen lamp, arc lamp, graphite heating) rapid annealing. In this embodiment, the annealing treatment preferably uses peak annealing or laser annealing.

Subsequently, as shown in fig. 2D, a portion of the work function layer 2022 is etched away using the etching stopper 204 as a stopper, so that the top surface of the work function layer 2022 is flush with the top surface of the etching stopper 204.

Specifically, since a portion of the work function layer 2022 is exposed after etching back the etch stopper layer 204, the exposed portion of the work function layer 2022 can be removed by etching.

Portions of the work function layer 2022 may be removed using a suitable dry etching or wet etching method, wherein preferably, the exposed work function layer 2022 may be removed using a wet etching method.

Wherein the wet etching has a high etching selectivity of the work function layer relative to the high-k dielectric layer and the etching stopper layer, that is, when etching the work function layer, the high-k dielectric layer, the etching stopper layer, the interlayer dielectric layer, and the like are hardly corroded.

In one example, part of the work function layer 2022 may be removed using, for example, an SC1 solution (a mixed solution of an ammonia solution/a hydrogen peroxide solution) or hydrogen peroxide as an etchant.

Subsequently, step five is performed, as shown in fig. 2E, a portion of the high-k dielectric layer 2021 is removed, so that the top surface of the high-k dielectric layer 2021 is flush with the top surface of the work function layer 2022.

The work function layer 2022 and the etch stop layer 204 may serve as a stop layer when etching the high-k dielectric layer 2021, and any suitable etching method such as dry etching or wet etching may be used to remove the high-k dielectric layer 2021 exposed in the gate recess so that the top surface of the high-k dielectric layer 2021 is flush with the top surface of the work function layer 2022.

Among them, the high-k dielectric layer 2021 exposed in the gate recess 202a is preferably etched using a wet etching method, for example, the wet etching can employ a hydrofluoric acid solution such as a diluted hydrofluoric acid solution (DHF), a buffered oxide etchant (buffer oxide etchant (BOE)), or a hydrofluoric acid buffer solution (buffer solution of hydrofluoric acid (BHF)).

In addition, in this step, since the interlayer dielectric layer outside the gate recess is nitrided in the foregoing embodiment, the surface of the interlayer dielectric layer is rendered to be a nitrided surface, and the etching rate thereof in wet etching (for example, wet etching using a hydrofluoric acid solution) is reduced, and therefore, the etching in this step does not damage the interlayer dielectric layer.

Furthermore, due to the fact that the etching process of the high-k dielectric layer and the work function layer can be controlled more due to the fact that the etching barrier layer is introduced, even if the difference exists between materials, the high-k dielectric layer is not greatly affected, the Ar plasma is not required to be used for bombarding the high-k dielectric layer, the impact on the work function layer 2022 is not caused, the performance and the yield of the device are improved, and a process window is increased.

And then, executing a step six, and removing the etching barrier layer.

The etch stop layer may be removed using any suitable method known to those skilled in the art, including but not limited to dry etching or wet etching.

In one example, where the material of the etch stop layer comprises amorphous silicon, then the etch stop layer may be removed by wet etching using an etchant comprising tetramethylammonium hydroxide or ammonium hydroxide.

When a protective layer is formed, the protective layer is also removed in this step.

Finally, a conventional metal gate structure process is performed, in one example, process steps A1-A3:

first, in step A1, an N-type work function layer (not shown) is conformally deposited on the surface of the work function layer 2022.

The material of the N-type work function layer may be selected from, but is not limited to TaAlC, taC, ti, al, tixAl1-x or other suitable thin film layers. The material of the N-type work function layer is preferably TiAl. The N-type work function layer may be formed by a suitable process such as CVD, ALD, or PVD. The N-type work function layer may have a thickness in the range of 10 angstroms to 80 angstroms.

Next, in step A2, a diffusion barrier layer (not shown) is formed on the bottom and sidewalls of the gate recess, the diffusion barrier layer being located on the surface of the N-type work function layer.

A diffusion barrier layer may also be optionally provided, and the material of the diffusion barrier layer may be selected from, but not limited to TiN, taN, ta, taAl or other suitable thin film layers.

After the film layer is formed, a planarization process, such as chemical mechanical polishing, may be performed to stop on the surface of the interlayer dielectric layer, so as to remove the redundant film layer on the surface of the interlayer dielectric layer.

Next, in step A3, a gate layer (not shown) is filled in the gate groove to form a metal gate structure.

Illustratively, the gate layer fills the gate recess and covers the surface of the inter-layer dielectric layer, and the planarization step is stopped in the inter-layer dielectric layer, and further, when the gate layer is planarized (e.g., a chemical mechanical polishing process), the inter-layer dielectric layer (ILD) is polished, so that the ILD height is also reduced.

The material of the gate layer may be selected from, but is not limited to, al, W, or other suitable thin film layers. The gate layer may be formed using a suitable process such as CVD, ALD, or PVD.

Thus, the method for manufacturing a semiconductor device according to the present invention will be described in detail, and other process steps may be required for manufacturing a complete device, which will not be described in detail herein.

It should be noted that although the embodiment of the present invention is described with respect to FinFET devices, the method of the present invention is equally applicable to other non-FinFET devices.

Example two

Next, a method of manufacturing a semiconductor device according to another embodiment of the present invention is explained and described in detail with reference to fig. 3A to 3E and fig. 4. The method of this embodiment and the first embodiment have multiple steps that are the same, and in order to avoid repetition, a detailed description will be omitted herein, mainly describing differences between the two embodiments.

First, as shown in fig. 3A, a semiconductor substrate (not shown) on which a gate groove 302a is formed is provided. The description of this step refers to the content of the first embodiment described above, which differs only in the reference numerals. In this embodiment, a FinFET device is also taken as an example for illustration.

In one example, when the semiconductor device is a FinFET device, the fin structure 301 is formed on the semiconductor substrate, where the fin structure 301 is a pillar structure formed on the semiconductor substrate, and a plurality of fin structures may be formed on the semiconductor substrate, where the fin structures have the same width, or the fins are divided into a plurality of fin structure groups having different widths, and the lengths of the fin structures may also be different.

In one example, after forming the fin structures, isolation structures are formed on the semiconductor substrate outside of the fin structures 301, with the top surfaces of the isolation structures being lower than the top surfaces of the fin structures.

In one example, as shown in fig. 4, after forming the isolation structure, further comprising forming a dummy gate structure 30 over the isolation structure across the fin, wherein the dummy gate structure comprises a dummy gate dielectric layer and a dummy gate material layer.

Subsequently, as shown in fig. 4, an interlayer dielectric layer 31 may be further formed to cover the semiconductor substrate and the dummy gate structure 30, and planarized to stop on top of the dummy gate structure.

In one example, after the step of planarizing the interlayer dielectric layer, the method further comprises the steps of:

first, as shown in fig. 4, a part of the interlayer dielectric layer 31 is etched back so that the top surface of the interlayer dielectric layer 31 is lower than the top surface of the dummy gate structure 30.

The interlayer dielectric 31 may be etched back using any suitable dry or wet etching method, for example, a SICONI process is selected to etch the interlayer dielectric, which has a high selectivity to the interlayer dielectric.

An etch stop layer (not shown) is then formed on the surface of the interlayer dielectric layer, wherein a top surface of the etch stop layer is flush with a top surface of the dummy gate structure.

Specifically, an etch stop layer may be deposited to cover the interlayer dielectric layer 31 and the dummy gate structure 30, and then a planarization process (e.g., a chemical mechanical polishing process) may be performed to stop at the surface of the dummy gate structure 30. Since the interlayer dielectric is lower than the dummy gate structure, the etch stop layer on the planarized dummy gate structure is polished away and the etch stop layer remains on the ILD to act as a barrier when the high-k dielectric is later removed.

Illustratively, the etch stop layer may be a material having a low etch selectivity in a hydrofluoric acid solution relative to the high k dielectric layer, such as a nitride, which may be silicon nitride, silicon oxynitride, or other suitable insulating material.

The etch stop layer may be formed by deposition by a suitable deposition method, for example by atomic layer deposition.

In one example, the gate recess 302a is formed by removing the dummy gate structure.

Next, step two is performed, as shown in fig. 3A, a high-k dielectric layer 3021 and a work function layer 3022 are sequentially formed on the bottom and the side walls of the gate recess 302a.

Optionally, before forming the high-k dielectric layer 3021, a step of forming an interface layer (not shown) at the bottom of the gate recess 302a is further included.

Optionally, after forming the high-k dielectric layer 3021, the high-k dielectric layer 3021 may also be subjected to an annealing treatment called Post Deposition Annealing (PDA).

Next, as shown in fig. 3C, a third step is performed, where an etching stopper 304 is formed to fill a portion of the gate recess 302a, wherein the top surface of the etching stopper 304 is lower than the top surfaces of the high-k dielectric layer 3021 and the work function layer 3022.

In one example, as shown in fig. 3A, after forming the work function layer 3022 and before forming the etching stopper layer, the step of forming the protection layer 303 on the surface of the work function layer 3022 may be further performed, where the protection layer 303 is formed by conformal deposition, and the protection layer 303 is used to protect the work function layer during the subsequent annealing process.

The material of the protective layer 303 is an amorphous semiconductor material. The amorphous semiconductor material includes amorphous silicon (a-Si) or amorphous germanium (a-Ge), but may be any other suitable amorphous semiconductor material, and in this embodiment, the material of the protective layer preferably includes a-Si.

In one example, an anneal process, such as a PCA anneal, may also be performed after the formation of the protective layer 303 and prior to the formation of the etch stop layer 304, wherein the anneal process is to remove excess oxygen from the high k dielectric layer 3021.

Subsequently, as shown in fig. 3B, the protective layer may be removed, and the protective layer may be removed by dry etching or wet etching, preferably by wet etching, which has a high etching selectivity of the protective layer with respect to the work function layer, and when the material of the protective layer includes amorphous silicon, the protective layer may be removed by wet etching using an etchant including tetramethylammonium hydroxide or ammonium hydroxide.

In one example, after removing the protective layer, a method of forming an etch stop layer 304 filling a portion of the gate recess 302a includes: first, as shown in fig. 3B, an etch stop layer 304 is deposited to fill the gate recess 302a and overflow over the gate recess. The etch stop layer 304 may also be selectively planarized to stop on top of the gate recess. The planarization may be any suitable planarization method, such as chemical mechanical polishing, and the like. Next, as shown in fig. 3C, a portion of the etch stop layer 304 is etched back to a target height, wherein the target height of the etch stop layer 304, i.e., the target height of the high-k dielectric layer and the work function layer. The etching back may use any suitable dry etching or wet etching method, and is not particularly limited herein.

In this embodiment, the material of the etch stop layer 304 preferably comprises an oxide, particularly silicon oxide, which may be formed by, for example, chemical vapor deposition, physical vapor deposition, etc., such as by Flowable Chemical Vapor Deposition (FCVD).

Next, as shown in fig. 3D, a portion of the work function layer 3022 is etched away with the etching stopper 304 as a stopper, so that the top surface of the work function layer 3022 is level with the top surface of the etching stopper 304.

Specifically, since a portion of the work function layer 3022 is exposed after etching back the etch stopper layer 304, the exposed portion of the work function layer 3022 may be removed by etching.

A portion of the work function layer 3022 may be removed using a suitable dry etching or wet etching method, wherein the exposed work function layer 3022 may be removed preferably using a wet etching method.

In one example, a SC1 solution (a mixed solution of an ammonia solution/a hydrogen peroxide solution) or hydrogen peroxide may be used as an etchant to remove a part of the work function layer 3022.

Next, step five and step six are performed, as shown in fig. 3E, a portion of the high-k dielectric layer 3021 is removed, so that the top surface of the high-k dielectric layer 3021 is level with the top surface of the work function layer 3022; and removing the etching barrier layer.

Specifically, where the material of the etch stop layer includes an oxide, such as silicon oxide, and the material of the high-k dielectric layer 3021 also includes an oxide, the etch stop layer may be removed at the same time as the exposed high-k dielectric layer 3021 is removed using a wet etch.

The work function layer 3022 may serve as a barrier layer in etching the high-k dielectric layer 3021 and the etch stop layer 304, and the high-k dielectric layer 3021 exposed in the gate recess may be removed using any suitable etching method, such as dry etching or wet etching, so that a top surface of the high-k dielectric layer 3021 is level with a top surface of the work function layer 3022.

Among them, the high-k dielectric layer 3021 and the etch stopper layer exposed in the gate recess 302a are preferably etched by a wet etching method, for example, the wet etching can employ a hydrofluoric acid solution such as a diluted hydrofluoric acid solution (DHF), a buffered oxide etchant (buffer oxide etchant (BOE)), or a hydrofluoric acid buffer solution (buffer solution of hydrofluoric acid (BHF)).

Also, in this step, since an etch stop layer is formed on the interlayer dielectric layer outside the gate recess in the foregoing embodiment, the etch stop layer protects the interlayer dielectric layer thereunder from damage by, for example, wet etching with a hydrofluoric acid solution as an etchant.

Furthermore, due to the fact that the etching process of the high-k dielectric layer and the etching process of the work function layer can be more controllable through the introduction of the etching barrier layer, even if the difference exists between materials, the high-k dielectric layer is not greatly affected, and according to the scheme, ar plasma does not need to be used for bombarding the high-k dielectric layer, the impact on the bombardment of the work function layer 3022 is avoided, the performance and the yield of the device are improved, and the process window is increased.

Finally, a conventional metal gate structure process is performed, wherein the subsequent process of the metal gate structure can be referred to the description in the first embodiment, and the description is omitted herein.

Example III

In another embodiment of the present invention, a method for manufacturing a semiconductor device is provided, where the method in this embodiment and the first and second embodiments have the same steps, and in order to avoid repetition, a description is mainly given of a difference between the first embodiment and the second embodiment.

Next, a method of the present embodiment will be described with reference to fig. 5A to 5F. In this embodiment, the main difference between the method of the second embodiment and the method of the second embodiment is that the protective layer 303 is not removed before the etching stopper 304 is formed.

First, as shown in fig. 5A, a semiconductor substrate (not shown) on which a gate groove 302a is formed is provided.

Specific structures may refer to the foregoing first and second embodiments, and are not repeated here.

Illustratively, in this embodiment, an etching stop layer is also formed on the interlayer dielectric layer, and the forming method thereof may refer to the second embodiment.

Next, step two is performed, as shown in fig. 5A, a high-k dielectric layer 3021 and a work function layer 3022 are sequentially formed on the bottom and the side walls of the gate recess 302 a.

Next, as shown in fig. 5C, a third step is performed, where an etching stopper 304 is formed to fill a portion of the gate recess 302a, wherein the top surface of the etching stopper 304 is lower than the top surfaces of the high-k dielectric layer 3021 and the work function layer 3022.

In one example, as shown in fig. 5A, after forming the work function layer 3022 and before forming the etching stopper layer, the step of forming the protection layer 303 on the surface of the work function layer 3022 may further include forming the protection layer 303 by conformal deposition, where the protection layer 303 is used to protect the work function layer during the subsequent annealing process.

In one example, after the annealing process, a method of forming the etch stop layer 304 to fill a portion of the gate recess 302a includes: first, as shown in fig. 5B, an etch stop layer 304 is deposited to fill the gate recess 302a and overflow over the gate recess. The etch stop layer 304 may also be selectively planarized to stop on top of the gate recess. The planarization may be any suitable planarization method, such as chemical mechanical polishing, and the like. Next, as shown in fig. 5C, a portion of the etch stop layer 304 is etched back to a target height, wherein the target height of the etch stop layer 304, i.e., the target height of the high-k dielectric layer and the work function layer.

In one example, as shown in fig. 5D, after etching back the etching stopper 304, etching back to remove a portion of the protection layer 303 to be flush with the top surface of the etching stopper 304 is further included.

The exposed protective layer 303 may be removed using a dry etch or a wet etch, wherein preferably a wet etch is used, which has a high etch selectivity of the protective layer 303 with respect to the etch stop layer 304 and the work function layer 3022.

Where the material of the protective layer includes amorphous silicon, an etchant including tetramethylammonium hydroxide or ammonium hydroxide may be used to wet etch away the exposed protective layer 303.

Next, step four is performed, in which a portion of the work function layer 3022 is removed by etching using the etching stopper 304 as a stopper, so that the top surface of the work function layer 3022 is flush with the top surface of the etching stopper 304.

Specifically, since a part of the work function layer 3022 is exposed after etching back the etching stopper 304, the exposed part of the work function layer 3022 can be removed by etching, and the protective layer 303 can also function as a stopper.

Wherein the wet etching has a high etching selectivity of the work function layer relative to the high-k dielectric layer, the protective layer and the etching stopper layer, that is, when the work function layer is etched, the high-k dielectric layer, the etching stopper layer, the interlayer dielectric layer and the like are hardly corroded.

Next, performing the fifth and sixth steps, removing a portion of the high-k dielectric layer 3021 so that the top surface of the high-k dielectric layer 3021 is level with the top surface of the work function layer 3022; and removing the etching barrier layer.

The work function layer 3022 and the protective layer 303 may serve as a barrier layer for etching the high-k dielectric layer 3021 and the etch stop layer 304, and the high-k dielectric layer 3021 exposed in the gate recess may be removed using any suitable etching method, for example, dry etching or wet etching, so that a top surface of the high-k dielectric layer 3021 is flush with a top surface of the work function layer 3022.

Finally, as shown in fig. 5F, the remaining protective layer is removed. The protective layer may be removed using a dry etch or a wet etch, wherein preferably a wet etch is used, the wet etch having a high etch selectivity of the protective layer relative to the etch stop layer 304 and the work function layer 3022. When the material of the protective layer includes amorphous silicon, an etchant including tetramethylammonium hydroxide or ammonium hydroxide may be used to wet etch the exposed protective layer.

Finally, a conventional metal gate structure process is performed, wherein the subsequent process of the metal gate structure can be referred to the description in the first embodiment and the second embodiment, and the description is omitted herein.

Example IV

The invention also provides a semiconductor device prepared by adopting the method in the first embodiment, the second embodiment or the third embodiment.

Since the semiconductor device of the present invention is produced by the method in the foregoing embodiment one, embodiment two or embodiment three, it has the same advantages as the foregoing embodiment one.

Example five

In another embodiment of the present invention, an electronic apparatus is provided, including the semiconductor device, where the semiconductor device is prepared according to the foregoing method.

The electronic device of the embodiment may be any electronic product or apparatus such as a mobile phone, a tablet computer, a notebook computer, a netbook, a game console, a television, a VCD, a DVD, a navigator, a digital photo frame, a camera, a video camera, a recording pen, MP3, MP4, PSP, and the like, and may also be any intermediate product including a circuit. The electronic device provided by the embodiment of the invention has better performance due to the use of the semiconductor device.

Wherein fig. 7 shows an example of a mobile phone handset. The mobile phone handset 700 is provided with a display portion 702, an operation button 703, an external connection port 704, a speaker 705, a microphone 706, and the like, which are included in a housing 701.

The present invention has been illustrated by the above-described embodiments, but it should be understood that the above-described embodiments are for purposes of illustration and description only and are not intended to limit the invention to the embodiments described. In addition, it will be understood by those skilled in the art that the present invention is not limited to the embodiments described above, and that many variations and modifications are possible in light of the teachings of the invention, which variations and modifications are within the scope of the invention as claimed. The scope of the invention is defined by the appended claims and equivalents thereof.

Claims

1. A method of manufacturing a semiconductor device, comprising:

providing a semiconductor substrate, forming a gate groove on the semiconductor substrate, wherein before forming the gate groove, the method further comprises the following steps:

Nitriding the interlayer dielectric layer with partial thickness, wherein the bottom of the part of the interlayer dielectric layer subjected to nitriding is positioned below the top surface of the pseudo gate structure;

flattening the interlayer dielectric layer to stop on the surface of the pseudo gate structure, and reserving part of the interlayer dielectric layer after nitriding treatment;

removing the dummy gate structure to form the gate recess;

using the etching barrier layer as a barrier layer, and using a mixed solution of ammonia solution/hydrogen peroxide solution or hydrogen peroxide as an etchant to etch and remove part of the work function layer, so that the top surface of the work function layer is flush with the top surface of the etching barrier layer and lower than the top surface of the interlayer dielectric layer;

removing part of the high-k dielectric layer by using a hydrofluoric acid solution wet etching method, so that the top surface of the high-k dielectric layer is flush with the top surface of the work function layer, wherein the top surface of the interlayer dielectric layer is a surface after nitriding treatment, the etching rate of the interlayer dielectric layer in the wet etching is reduced, and damage to the interlayer dielectric layer is avoided;

Removing the etching barrier layer, wherein when the material of the etching barrier layer comprises amorphous silicon, the etching barrier layer is removed by wet etching by using an etchant comprising tetramethylammonium hydroxide or ammonium hydroxide;

wherein the method does not bombard the high-k dielectric layer with an Ar plasma.

2. The method of manufacturing of claim 1, further comprising the step of performing an annealing process before forming the etch stop layer or after forming the etch stop layer.

3. The method of manufacturing of claim 1, further comprising, after forming the work function layer, before forming the etch stop layer: and forming a protective layer on the surface of the work function layer.

4. The method of manufacturing of claim 3, further comprising, after forming the protective layer prior to forming the etch stop layer: and (3) performing annealing treatment.

5. The method of manufacturing of claim 3, further comprising, when the material of the etch stop layer comprises an oxide, the steps of, prior to forming the etch stop layer: and removing the protective layer.

6. The method of manufacturing of claim 3, further comprising, prior to the step of removing a portion of the work function layer, the steps of: and etching back and removing part of the protective layer until the top surface of the protective layer is flush with the surface of the etching barrier layer.

7. The method of manufacturing of claim 1, wherein the etch stop layer is removed at the same time that the high-k dielectric layer is removed using a wet etch when the material of the etch stop layer comprises an oxide.

8. The method of manufacturing according to claim 1, wherein the nitriding treatment uses a decoupled plasma doping technique or a method using plasma implantation of N.

9. The method of manufacturing of claim 3, wherein the material of the etch stop layer comprises amorphous silicon or silicon oxide; the material of the protective layer comprises amorphous silicon.

10. A method of manufacturing a semiconductor device, comprising:

forming an etch stop layer on a surface of the interlayer dielectric layer, wherein a top surface of the etch stop layer is flush with a top surface of the dummy gate structure;

removing the dummy gate structure to form the gate recess;

removing part of the high-k dielectric layer by using a hydrofluoric acid solution in a wet etching manner, so that the top surface of the high-k dielectric layer is flush with the top surface of the work function layer, wherein the etching stop layer is formed on the interlayer dielectric layer outside the grid groove and protects the interlayer dielectric layer below the etching stop layer from being damaged by the wet etching of the hydrofluoric acid solution as an etching agent;

11. A semiconductor device manufactured by the manufacturing method according to any one of claims 1 to 10.

12. An electronic device comprising the semiconductor device according to claim 11.