CN110648970B - Semiconductor device and method of forming the same - Google Patents

Semiconductor device and method of forming the same Download PDF

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Publication number
CN110648970B
CN110648970B CN201810681126.8A CN201810681126A CN110648970B CN 110648970 B CN110648970 B CN 110648970B CN 201810681126 A CN201810681126 A CN 201810681126A CN 110648970 B CN110648970 B CN 110648970B
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forming
layer
dummy gate
region
gate opening
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CN110648970A (en
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周飞
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823821—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

A semiconductor structure and a method of forming the same, wherein the method comprises: providing a substrate, wherein the substrate comprises a first area and a second area, and the first area and the second area are respectively provided with a pseudo gate structure and an interlayer dielectric layer which cover a part of the surface of the substrate; removing the dummy gate structure in the first interlayer dielectric layer to form a first dummy gate opening; removing the dummy gate structure in the second interlayer dielectric layer to form a second dummy gate opening; forming contact holes in the interlayer dielectric layers of the first region and the second region respectively, wherein the bottoms of the contact holes are exposed out of the source-drain doped regions of the first region and the second region respectively; forming a metal silicide layer on the bottom surface of the contact hole; forming a conductive plug filling the contact hole after forming the metal silicide layer; and after the conductive plug is formed, forming N-type work function material layers in the first dummy gate opening and the second dummy gate opening respectively. The semiconductor device formed by the method has better performance.

Description

Semiconductor device and method of forming the same
Technical Field
The invention relates to the field of semiconductor manufacturing, in particular to a method for forming a semiconductor device.
Background
With the development of semiconductor technology, the control capability of the conventional planar MOS transistor for the channel current becomes weaker, resulting in a serious leakage current. A Fin field effect transistor (Fin FET) is an emerging multi-gate device, which generally includes a Fin portion protruding from a surface of a semiconductor substrate, a gate structure covering a portion of a top surface and a sidewall of the Fin portion, and source-drain doped regions in the Fin portion located at both sides of the gate structure.
A post silicide process (silicide last) is usually used to form a metal silicide in the contact hole on the source/drain doped region to reduce the contact resistance between the source/drain doped region and the upper layer metal. However, the annealing process used to form the metal silicide exacerbates the diffusion of Al ions in the N-type work function material layer. The performance of semiconductor devices formed using the prior art techniques is desired to be improved.
Disclosure of Invention
The technical problem to be solved by the invention is to provide a method for forming a semiconductor device, which can reduce the diffusion of Al ions in an N-type work function material layer in an NMOS transistor to a gate dielectric layer.
To solve the above technical problem, an embodiment of the present invention provides a method for forming a semiconductor device, including: the method comprises the following steps: providing a substrate, wherein the substrate is provided with a pseudo gate structure and an interlayer dielectric layer, the pseudo gate structure and the interlayer dielectric layer cover part of the surface of the substrate, the interlayer dielectric layer covers the surface of the side wall of the pseudo gate structure, and source and drain doped regions are arranged in the substrate on two sides of the pseudo gate structure; removing the pseudo gate structure, and forming a pseudo gate opening in the interlayer dielectric layer; forming a contact hole in the interlayer dielectric layer, wherein the bottom of the contact hole is exposed out of the source drain doped region; forming a metal silicide layer on the bottom surface of the contact hole; forming a conductive plug filling the contact hole after forming the metal silicide layer; and forming an N-type work function material layer in the dummy gate opening after the conductive plug is formed.
Optionally, after the dummy gate opening is formed, the contact hole is formed.
Optionally, after forming the dummy gate opening and before forming the contact hole, the method further includes: forming interface layers on the side wall and the bottom surface of the pseudo gate opening; forming a gate dielectric layer on the surface of the interface layer; and forming a diffusion barrier layer on the surface of the gate dielectric layer.
Optionally, the substrate comprises a first region and a second region; the first region is used for forming an N-type field effect transistor, and the second region is used for forming a P-type field effect transistor.
Optionally, the dummy gate structures are respectively located on the substrate surface of the first region and the substrate surface of the second region; the source-drain doped region is respectively positioned in the substrate of the first region and the substrate of the second region; the contact holes are respectively positioned in the interlayer dielectric layer of the first area and the interlayer dielectric layer of the second area; the N-type work function material layer is respectively positioned in the dummy gate opening of the first area and the dummy gate opening of the second area.
Optionally, after forming the diffusion barrier layer and before forming the contact hole, the method further includes: and forming sacrificial structures in the dummy gate openings of the first area and the dummy gate openings of the second area, wherein the sacrificial structures fill the dummy gate openings of the first area and the dummy gate openings of the second area.
Optionally, the sacrificial structure includes a first sacrificial layer and a second sacrificial layer located on a surface of the first sacrificial layer.
Optionally, the step of forming the sacrificial structure includes: forming a first sacrificial layer on the side wall and the bottom surface of the dummy gate opening of the first region and the dummy gate opening of the second region; and forming a second sacrificial layer on the surface of the first sacrificial layer.
Optionally, the material of the first sacrificial layer includes amorphous silicon, polycrystalline silicon, or monocrystalline silicon; the material of the second sacrificial layer comprises silicon oxide.
Optionally, the method for forming the sacrificial structure further includes: performing a first annealing process after forming the first sacrificial layer; the annealing temperature of the first annealing process is 800-1000 ℃.
Optionally, the sacrificial structure is a single layer; the material of the sacrificial structure comprises amorphous silicon, polycrystalline silicon or monocrystalline silicon.
Optionally, a second annealing process is performed after the sacrificial structure is formed; the annealing temperature of the second annealing process is 800-1000 ℃.
Optionally, the forming method of the metal silicide layer includes: depositing a metal layer on the side wall and the bottom surface of the contact hole; carrying out a third annealing process to enable the metal layer to react with the surface of the source drain doped region to form a metal silicide layer; the third annealing process is a laser annealing process, and the annealing temperature is 750-900 ℃.
Optionally, the material of the metal silicide layer includes: a titanium silicon compound.
Optionally, after forming the conductive plug and before forming the N-type work function material layer, the method further includes: removing the sacrificial structures in the dummy gate opening of the first region and the dummy gate opening of the second region; and after removing the sacrificial structures in the dummy gate openings of the first region and the second region, removing the diffusion barrier layers in the dummy gate openings of the first region.
Optionally, after removing the diffusion barrier layer in the dummy gate opening of the first region and before forming the N-type work function material layer, the method further includes: and forming a P-type work function material layer in the dummy gate opening of the second region.
Optionally, the material of the P-type work function material layer includes titanium nitride or tantalum nitride.
Optionally, the material of the N-type work function material layer includes one or more of TiAl, TiAlC, TiAlN, and AlN.
Optionally, after forming the N-type work function material layer in the dummy gate opening, the method further includes: and filling a metal material in the dummy gate opening to form a metal gate.
Correspondingly, the invention also provides a semiconductor device formed by adopting any one of the methods.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following beneficial effects:
in the forming method of the semiconductor device provided by the technical scheme of the invention, after the metal silicide layer is formed in the contact hole, a conductive plug which is filled in the contact hole is formed; and after the conductive plug is formed, forming an N-type work function material layer in the dummy gate opening. After the metal silicide layer is formed in the contact hole, the N-type work function material layer is formed in the pseudo gate opening, the influence of a high-temperature process of an annealing process performed by forming the metal silicide layer on substances in the N-type work function material layer can be avoided, the diffusion of Al ions in the N-type work function material layer can be reduced, the diffusion of the Al ions in the N-type work function material layer in a transistor to a gate dielectric layer is reduced, the interface state of the gate dielectric layer can be improved, the reliability of the gate dielectric layer is improved, meanwhile, the change of the starting voltage of a device is avoided, and the performance of the obtained semiconductor device is improved.
Furthermore, a fourth annealing process carried out on the gate dielectric layer is formed, so that on one hand, the defects of the gate dielectric layer are repaired, and the interface state of the gate dielectric layer is improved, thereby being beneficial to improving the reliability and the starting voltage of the semiconductor device; on the other hand, the gate dielectric layer is formed before the metal silicide layer, so that the influence of the fourth annealing process on the metal silicide layer is avoided, the quality of the formed metal silicide layer is improved, the contact resistance of the source-drain doped region and the conductive plug is reduced, and the performance of the semiconductor device is improved.
Further, the forming method further includes: and forming an interface layer on the side wall and the bottom surface of the dummy gate opening before forming the contact hole. The interface layer can prevent the substrate from contacting a gate dielectric layer formed on the surface of the interface layer subsequently, so that the performance of the semiconductor device is improved.
Furthermore, the diffusion barrier layer can be used as a P-type work function material layer in the PMOS transistor on one hand, and can be used as a barrier layer to prevent an N-type work function material layer in the PMOS transistor from diffusing to the gate dielectric layer on the other hand, so that the reliability and the starting voltage of the semiconductor device are improved.
Drawings
Fig. 1 to 14 are schematic structural views of steps of a method for forming a semiconductor device according to an embodiment of the present invention.
Detailed Description
As described in the background, the performance of the semiconductor devices formed by the prior art needs to be improved.
A method of forming a semiconductor device, comprising: providing a semiconductor substrate, wherein the substrate comprises an NMOS transistor region and a PMOS transistor region, the semiconductor substrate of the NMOS transistor region and the PMOS transistor region is provided with a pseudo gate structure and an interlayer dielectric layer, the pseudo gate structure and the interlayer dielectric layer cover part of the surface of the substrate, the interlayer dielectric layer covers the side wall surface of the pseudo gate structure, and source-drain doped regions are arranged in the substrate at two sides of the pseudo gate structure; removing the pseudo gate structure of the NMOS transistor region, and forming a first pseudo gate opening in the interlayer dielectric layer of the NMOS transistor region; removing the pseudo gate structure of the PMOS transistor area, and forming a second pseudo gate opening in the interlayer dielectric layer of the PMOS transistor area; after a first dummy gate opening and a second dummy gate opening are formed, a high-k dielectric layer, an N-type work function material layer positioned on the high-k dielectric layer and a metal gate positioned on the N-type work function material layer are formed on the side wall and the bottom of the first dummy gate opening; forming a high-k dielectric layer, a P-type work function material layer positioned on the high-k dielectric layer and a metal gate positioned on the P-type work function material layer on the side wall and the bottom of the second dummy gate opening; after metal gates are formed in the first dummy gate opening and the second dummy gate opening, contact holes are formed above source-drain doped regions of the NMOS transistor region and the PMOS transistor region respectively, and metal silicide layers are formed on the side walls and the bottom surfaces of the contact holes; after the metal silicide layer is formed, filling metal materials in the contact hole to form a conductive plug.
By forming the metal silicide layer after the work function material layer is formed, the influence of the annealing process performed after the high-k dielectric layer is formed and the heat treatment performed in the process of forming the work function material layer on the formed metal silicide layer can be avoided, so that the quality of the metal silicide layer can be improved, the contact resistance of the source-drain doped region and the conductive plug can be reduced, and the formed semiconductor device has better performance.
By forming the metal silicide layer in the contact hole on the source drain doping region, the contact resistance between the source drain doping region and the metal layer filling the contact hole can be reduced. However, an annealing process is required to be performed to form the metal silicide layer, after the N-type work function metal material layer is formed on the side wall and the bottom of the first dummy gate opening, the metal silicide layer is formed in the contact hole on the source-drain doped region, and the high-temperature process of the annealing process can aggravate the diffusion of Al ions in the N-type work function material layer formed in the NMOS transistor to the lower gate dielectric layer, so that the interface state of the gate dielectric layer is influenced, the interface reliability of the gate dielectric layer and the starting voltage of the semiconductor device are further influenced, and the performance of the formed semiconductor device is poor.
In order to solve the technical problem, the invention provides a method for forming a semiconductor structure, which comprises the following steps: forming a contact hole in the interlayer dielectric layer, wherein the bottom of the contact hole is exposed out of the source drain doped region; forming a metal silicide layer on the bottom surface of the contact hole; and forming an N-type work function material layer in the dummy gate opening after the metal silicide layer is formed. The semiconductor device formed by the method has better performance.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
Referring to fig. 1, a substrate 100 is provided, the substrate includes a first region a and a second region B, the substrate 100 has a dummy gate structure 103 and an interlayer dielectric layer 107 covering a part of a surface of the substrate, the interlayer dielectric layer 107 covers a sidewall surface of the dummy gate structure 103, the substrate 100 on both sides of the dummy gate structure 103 has a source-drain doped region 106 therein, and a surface of the interlayer dielectric layer 107 has a protective layer 108 covering a part of a sidewall of the dummy gate structure 103.
In the present embodiment, the substrate 100 includes: a substrate 101 and a fin 102 on the substrate 101.
In other embodiments, when the semiconductor device is a planar MOS transistor, the substrate is a planar semiconductor substrate.
In this embodiment, the first region a is used to form NMOS transistors, and the second region B is used to form PMOS transistors.
In this embodiment, the method for forming the substrate 100 includes: providing an initial substrate, wherein the initial substrate is provided with a first mask layer, and the first mask layer exposes part of the top surface of the initial substrate; and etching the initial substrate by taking the first mask layer as a mask to form a substrate 101 and a fin part 102 positioned on the substrate 101.
In this embodiment, the material of the initial substrate is silicon. Correspondingly, the material of the substrate 101 and the fin portion 102 is silicon.
In this embodiment, the sidewall surface of the dummy gate structure 103 has an offset sidewall 104 and a main sidewall 105 located on the sidewall surface of the offset sidewall 104.
The offset spacers 104 are used to define the location of lightly doped regions (not shown). The main sidewall 105 is used to define the position of the source-drain doped region 106.
The substrate 100 also has an isolation structure (not shown) covering the fin 102, and a top surface of the isolation structure is lower than a top surface of the fin 102 and covers a portion of sidewalls of the fin 102.
Referring to fig. 2, the dummy gate structure 103 in the first region a interlayer dielectric layer 107 is removed to form a first dummy gate opening 109; and removing the dummy gate structure 103 in the second region B interlayer dielectric layer 107 to form a second dummy gate opening 110.
In this embodiment, the process of removing the dummy gate structure 103 is a dry etching process. The specific process parameters comprise: the adopted gas comprises HBr and He, wherein the HBr flow is 150-500 standard ml/min, the He flow is 100-400 standard ml/min, the pressure is 3-10 mTorr, the side wall radio frequency power is 200-500 watts, the bottom radio frequency power is 10-40 watts, and the temperature is 50-100 ℃.
The first dummy gate opening 109 and the second dummy gate opening 110 are used for forming a gate structure later.
Referring to fig. 3, an interface film 111, a gate dielectric film 112 on the surface of the interface film 111, and a diffusion barrier film 113 on the surface of the gate dielectric film 112 are formed on the sidewalls and bottom surfaces of the first and second dummy gate openings 109 and 110 and on the surface of the protection layer 108.
The process of forming the interface film 111 includes: a chemical vapor deposition process, a physical vapor deposition process, or an atomic layer deposition process.
The interface film 111 is used for forming an interface layer later. In this embodiment, the material of the interface film 111 includes: silicon oxide. Accordingly, the subsequently formed interfacial layer material includes: silicon oxide.
The gate dielectric layer film 112 is used for forming a gate dielectric layer subsequently. The gate dielectric film 112 is made of a high-K (K is greater than 3.9) dielectric material. In the present embodiment, the gate dielectric layer film 112The material is hafnium oxide. Correspondingly, the material of the gate dielectric layer formed subsequently is hafnium oxide. In other embodiments, the material of the gate dielectric layer film includes: la 2 O 3 、HfSiON、HfAlO 2 、ZrO 2 、Al 2 O 3 Or HfSiO 4 。
The forming process of the gate dielectric layer film 112 includes a chemical vapor deposition process or a physical vapor deposition process.
In this embodiment, a fourth annealing process is performed after the gate dielectric film 112 is formed; the annealing temperature of the fourth annealing process is 800-1000 ℃.
The fourth annealing process can repair the defects of the gate dielectric film 112, so that the defects of the subsequently formed gate dielectric layer can be repaired, the interface state of the gate dielectric layer is improved, and the reliability and the starting voltage of the semiconductor device are improved.
The diffusion barrier film 113 is used for the subsequent formation of a diffusion barrier layer. The material of the diffusion barrier film 113 includes tantalum nitride or titanium nitride. In this embodiment, the diffusion barrier film 113 is made of titanium nitride. Correspondingly, the material of the diffusion barrier layer formed subsequently is titanium nitride.
The diffusion barrier film 113 is formed by a chemical vapor deposition process, a physical vapor deposition process, or an atomic layer deposition process.
In the present embodiment, the process of forming the diffusion barrier film 113 is an atomic layer deposition process. The specific process parameters comprise: providing titanium-containing organic precursor substance, wherein the temperature is 80-300 ℃, the pressure is 5 mTorr-20 Torr, and the cycle time is 5-50 times.
In this embodiment, after the diffusion barrier film 113 is formed, a sacrificial structure is formed in the first dummy gate opening 109 and the second dummy gate opening 110, and the sacrificial structure fills the first dummy gate opening 109 and the second dummy gate opening 110. The sacrificial structure includes: a first sacrificial layer located at the bottom and sidewall surfaces of the first dummy gate opening 109 and the second dummy gate opening 110, and a second sacrificial layer located at the surface of the first sacrificial layer. The formation process of the first sacrificial layer and the second sacrificial layer will be described later with reference to fig. 4 to 5.
Referring to fig. 4, a first sacrificial film 114 and a second sacrificial film 115 are formed on the surfaces of the diffusion barrier film 113 in the first dummy gate opening 109 and the second dummy gate opening 110.
The forming steps of the first sacrificial film 114 and the second sacrificial film 115 include: forming a first sacrificial film 115 on the surfaces of the diffusion barrier film in the first dummy gate opening 109 and the second dummy gate opening 110; a second sacrificial film 115 is formed on the surface of the first sacrificial film 114, and the second sacrificial film 115 fills the first dummy gate opening 109 and the second dummy gate opening 110.
The material of the first sacrificial film 114 includes amorphous silicon, polycrystalline silicon, and single crystal silicon. In this embodiment, the material of the first sacrificial film 114 is amorphous silicon. The amorphous silicon material can balance the oxygen content in the high-k dielectric material, and the oxygen content in the high-k dielectric layer is too high or too low, so that the first sacrificial film 114 is formed, which is beneficial to improving the performance of the semiconductor device.
The process of forming the first sacrificial film 114 includes: a chemical vapor deposition process, a physical vapor deposition process, or an atomic layer deposition process. The first sacrificial film 115 is used for the subsequent formation of a first sacrificial layer.
In the present embodiment, the process of forming the first sacrificial film 114 is a chemical vapor deposition process. The specific process parameters comprise: the gas used comprises SiH 4 The SiH 4 The flow rate of the gas is 30-3000 standard ml/min, the temperature is 360-520 ℃, and the pressure is 0.03-10 torr.
The thickness of the first sacrificial film 114 is 35 to 110 angstroms.
The thickness of the first sacrificial film 114 is chosen in the sense that: if the thickness of the first sacrificial film is too thin, the protective effect of the first sacrificial film on the lower gate dielectric film and the interface film is insufficient, and the gate dielectric film and the interface film are easily affected by a first annealing process which is carried out subsequently, so that the performance of the formed semiconductor device is poor; if the thickness of the first sacrificial film is too thick, since the amorphous silicon material is easily affected by a first annealing process performed subsequently, atomic agglomeration occurs, which is not beneficial to removing the amorphous silicon material by a subsequent process, and thus the performance of the formed semiconductor device is poor.
In the present embodiment, after the first sacrificial film 114 is formed, a first annealing process is performed; the annealing temperature of the first annealing process is 800-1000 ℃.
The first annealing process can make the density of the lower interface film 111 higher, thereby improving the isolation effect of the subsequently formed interface layer on the substrate 100 and the subsequently formed gate dielectric layer, and further being beneficial to improving the performance of the semiconductor device.
The process of forming the second sacrificial film 115 includes: a chemical vapor deposition process, a physical vapor deposition process, or an atomic layer deposition process. The material of the second sacrificial layer 115 includes silicon oxide for subsequent formation of a second sacrificial layer.
Referring to fig. 5, the interface film 111, the gate dielectric film 112, the diffusion barrier film 113, the first sacrificial film 114, and the second sacrificial film 115 are planarized until the top surface of the protection layer 108 is exposed, and an interface layer 116, a gate dielectric layer 117 on the interface layer 116, a diffusion barrier layer 118 on the gate dielectric layer 117, a first sacrificial layer 119 on the diffusion barrier layer 118, and a second sacrificial layer 120 on the first sacrificial layer 119 are formed on the side surfaces and the bottom surfaces of the first dummy gate opening 109 and the second dummy gate opening.
The process of planarizing the interface film 111, the gate dielectric film 112, the diffusion barrier film 113, the first sacrificial film 114, and the second sacrificial film 115 until the top surface of the protection layer 108 is exposed includes: and (5) carrying out a chemical mechanical polishing process.
In other embodiments, the sacrificial structure is a single-layer sacrificial structure, the material of the single-layer sacrificial structure includes amorphous silicon, polycrystalline silicon, or monocrystalline silicon, and the first dummy gate opening and the second dummy gate opening are filled with the single-layer sacrificial structure. Performing a second annealing process after the sacrificial structure is formed; the annealing temperature of the second annealing process is 800-1000 ℃.
Referring to fig. 6, contact holes 121 are formed in the interlayer dielectric layers 107 of the first region a and the second region B, respectively, and the bottoms of the contact holes 121 expose the source-drain doped regions 106 of the first region a and the second region B, respectively.
The method for forming the contact hole 121 includes: forming a second mask layer (not shown in the figure) on the surface of the interlayer dielectric layer 107 in the first region a and the second region B, respectively, wherein the second mask layer exposes the top surface of a part of the interlayer dielectric layer 107; and etching the interlayer dielectric layer 107 by taking the second mask layer as a mask until the top surface of the source-drain doped region 106 is exposed, and forming a contact hole 121 in the interlayer dielectric layer 107.
The second mask layer is used to define the position and size of a contact hole at the top of the source/drain doped region 106.
The material of the second mask layer comprises silicon nitride or titanium nitride.
The process for etching the interlayer dielectric layer 107 comprises the following steps: one or two of the dry etching process and the wet etching process are combined.
In this embodiment, the process of etching the interlayer dielectric layer 107 is a dry etching process. The specific process parameters comprise: the gas used comprises CH 4 And CHF 3 ，CH 4 The flow rate of (1) is 8-500 standard ml/min, CHF 3 The flow rate is 30-200 standard ml/min, the pressure is 10-2000 mTorr, the radio frequency power is 100-1300 Watts, the bias voltage is 80-500 volts, and the time is 4-500 seconds.
The contact hole 121 is used for subsequently receiving a conductive plug.
Referring to fig. 7, a metal silicide layer 122 is formed on the bottom surface of the contact hole 121.
The method for forming the metal silicide layer 122 comprises the following steps: depositing a metal layer (not shown) on the sidewalls and bottom surface of the contact hole 121; performing a third annealing process to react the metal layer with the surface of the source-drain doped region 106 to form the metal silicide layer 122; after the annealing process, the remaining metal layer is removed.
The third annealing process adopts a laser annealing process, and the annealing temperature is 750-900 ℃.
The metal silicide layer 122 materials include: a titanium silicon compound. The metal silicide layer 122 may improve contact resistance between a subsequently formed conductive plug and the source/drain doped region 106.
Referring to fig. 8, after the metal silicide layer 122 is formed, a conductive plug 123 filling the contact hole 121 is formed.
The method for forming the conductive plug 123 includes: forming conductive plug films (not shown) in the first and second dummy gate openings 109 and 110 and on the surface of the protective layer 108; a portion of the conductive plug film is removed until the top surface of the protective layer 108 is exposed, and a conductive plug 123 is formed within the contact hole 121.
The conductive plug membrane is made of metal. Therefore, the material of the conductive plug 123 is metal. Tungsten metal has excellent step coverage and filling, and is a preferred material for electrical conduction. In this embodiment, the conductive plug film is made of tungsten, and correspondingly, the conductive plug 123 is made of tungsten. In other embodiments, the material of the conductive plug comprises aluminum or copper.
The forming process of the conductive plug film comprises the following steps: a chemical vapor deposition process or a physical vapor deposition process.
In this embodiment, the process of forming the conductive plug film is a chemical vapor deposition process. The specific process parameters comprise: the gas used comprises WF 6 ，WF 6 The flow rate of (a) is 100 to 600 standard ml/min.
The process of removing a portion of the conductive plug film includes a chemical mechanical polishing process.
Referring to fig. 9, after the conductive plug 123 is formed and before the N-type work function material layer is formed, the sacrificial structures (not shown) in the first dummy gate opening 109 and the second dummy gate opening 110 are removed.
The step of removing the sacrificial structures in the first dummy gate opening 109 and the second dummy gate opening 110 includes: removing the second sacrificial layer 120 in the first dummy gate opening 109 and the second dummy gate opening 110; after removing the second sacrificial layer 120, the first sacrificial layer 119 in the first and second dummy gate openings 110 is removed.
The process of removing the second sacrificial layer in the first dummy gate opening 109 and the second dummy gate opening 110 includes: one or two of the dry etching process and the wet etching process are combined.
In this embodiment, the process of removing the second sacrificial layer in the first dummy gate opening 109 and the second dummy gate opening 110 is a dry etching process. The specific process parameters comprise: the gas includes He and NH 3 、NF 3 Wherein the flow rate of He is 600-2000 standard ml/min, NH 3 The flow rate of (1) is 200 to 500 standard ml/min, NF 3 The flow rate of the pressure sensor is 20-200 standard ml/min, the pressure intensity is 2-10 torr, and the time is 20-100 seconds.
The process of removing the first sacrificial layer in the first dummy gate opening 109 and the second dummy gate opening 110 includes: one or two of the dry etching process and the wet etching process are combined.
In this embodiment, the process of removing the first sacrificial layer in the first dummy gate opening 109 and the second dummy gate opening 110 is a wet etching process. The specific process parameters comprise: the etching solution comprises NH 4 OH solution and H 2 O, said NH 4 OH solution and H 2 The volume relation of O is 1: 10-20: 1, the temperature is 25-80 ℃, and the time is 2-100 min.
Referring to fig. 10, after removing the sacrificial layer in the first dummy gate opening 109 and the second dummy gate opening 110, the diffusion barrier layer 118 in the first dummy gate opening 109 is removed.
The process of removing the diffusion barrier layer 118 in the first dummy gate opening 109 includes one or a combination of a dry etching process and a wet etching process.
In this embodiment, the process of removing the diffusion barrier layer 118 in the first dummy gate opening is a wet etching process. The specific process parameters comprise: etching solution 1 and etching solution 2, etching solution1 comprises NH 4 OH、H 2 O 2 And H 2 O，NH 4 OH、H 2 O 2 And H 2 The volume relation ratio of O is 5:200:1000, and the temperature is 40 ℃; the etching solution 2 comprises HCl and H 2 O 2 And H 2 O，HCl、H 2 O 2 And H 2 The volume relation of O is 1:1.5:100, and the temperature is 50 ℃.
Referring to fig. 11, after removing the diffusion barrier layer 118 in the first dummy gate opening 109, a P-type work function material film 124 is formed in the second dummy gate opening 110 before forming the N-type work function material layer.
The method of forming the P-type work function material film 124 in the second dummy gate opening 110 includes: forming a P-type work function material film 124 in the first dummy gate opening 109 and the second dummy gate opening 110; the P work function material film 124 within the first dummy gate opening is removed.
The P-type work function material film 124 is used for the subsequent formation of a P-type work function material layer. The material of the P-type work function material film 124 includes: thallium nitride or titanium nitride. In this embodiment, the P-type work function material film 124 is made of titanium nitride, and correspondingly, the subsequently formed P-type work function material layer is made of titanium nitride.
The forming process of the P work function material film 124 includes a chemical vapor deposition process, a physical vapor deposition process, or an atomic layer deposition process.
In the present embodiment, the process of forming the P work function material film 124 is an atomic layer deposition process. The specific process parameters are as follows: providing titanium-containing organic precursor substance, wherein the temperature is 80-300 ℃, the pressure is 5 mTorr-20 Torr, and the cycle time is 5-50 times.
The process for removing the P work function material film 124 in the first dummy gate opening includes one or two of a dry etching process and a wet etching process.
In this embodiment, the process of removing the P work function material film 124 in the first dummy gate opening is a wet etching process. The specific process parameters comprise: etching solution 1 and etching solution 2, etching solution 1 bagComprises NH 4 OH、H 2 O 2 And H 2 O，NH 4 OH、H 2 O 2 And H 2 The volume relation of O is 5:200:1000, and the temperature is 40 ℃; the etching solution 2 comprises HCl and H 2 O 2 And H 2 O，HCl、H 2 O 2 And H 2 The volume relation ratio of O is 1:1.5:100, and the temperature is 50 ℃.
Referring to fig. 12, after forming the P-type work function material film 124 in the second dummy gate opening, an N-type work function material film 125 is formed in the first dummy gate opening 109 and the second dummy gate opening 110, respectively.
The N-type work function material film 125 is used for the subsequent formation of an N-type work function material layer. The material of the N-type work function material film 125 includes Al ions. The material of the N-type work function material film 125 includes one or a combination of more of TiAl, TiAlC, TiAlN, and AlN. In this embodiment, the material of the N-type work function material film 125 is TiAl, and correspondingly, the material of the subsequently formed N-type work function material layer is TiAl.
The formation process of the N-type work function material film 125 includes a chemical vapor deposition process, a physical vapor deposition process, or an atomic layer deposition process.
In the present embodiment, the formation process of the N-type work function material film 126 is an atomic layer deposition process. The specific process parameters comprise: providing organic precursor containing titanium and organic precursor containing Al, wherein the temperature is 80-500 ℃, the pressure is 2 mTorr-200 Torr, and the cycle time is 5-100 times.
In this embodiment, after the metal silicide layer 122 is formed in the contact hole 123 of each of the first region a and the second region B, the N-type work function material film 125 is formed in the first dummy gate opening 109 and the second dummy gate opening 110, and the N-type work function material film 125 is used for forming an N-type work function material layer in the following step, so that the influence of a high-temperature process of a third annealing process performed to form the metal silicide layer 122 on a substance in the N-type work function material layer can be avoided, thereby reducing the diffusion of Al ions in the N-type work function material layer, reducing the diffusion of Al ions in the N-type work function material layer in the NMOS transistor to the gate dielectric layer 117 below, improving the interface reliability of the gate dielectric layer 117 and the turn-on voltage of the semiconductor device, and further improving the performance of the obtained semiconductor device.
Referring to fig. 13, after forming an N-type work function material film 125 in the first dummy gate opening 109 and the second dummy gate opening 110, a metal material is filled in the first dummy gate opening 109 and the second dummy gate opening 110 to form a metal gate film 126.
The metal gate film 126 is used for the subsequent formation of a metal gate. In this embodiment, the metal gate film is made of tungsten. Correspondingly, the material of the metal gate formed subsequently is tungsten. In other embodiments, the material of the metal gate film includes: al, Cu, Ag, Au, Ni, Ti, W, WN, or WSi.
The forming process of the metal gate film comprises a chemical vapor deposition process or a physical vapor deposition process.
Referring to fig. 14, the P-type work function material film 124, the N-type work function material film 125 and the metal gate film 126 are planarized until the top surface of the protection layer 108 is exposed, an N-type work function material layer 128 and a metal gate 129 on the surface of the N-type work function material layer 128 are formed in the first dummy gate opening 109 and the second dummy gate opening 110, respectively, and a P-type work function material layer 127 is further formed in the second dummy gate opening and between the diffusion barrier layer 118 and the N-type work function material layer 128.
The process of planarizing the P-type work function material film 124, the N-type work function material film 125, and the metal gate film 126 includes a chemical mechanical polishing process.
Correspondingly, the embodiment of the invention also provides a semiconductor device formed by adopting the method.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims (13)

1. A method of forming a semiconductor device, comprising:
providing a substrate, wherein the substrate is provided with a pseudo gate structure and an interlayer dielectric layer, the pseudo gate structure and the interlayer dielectric layer cover part of the surface of the substrate, the interlayer dielectric layer covers the surface of the side wall of the pseudo gate structure, and source and drain doped regions are arranged in the substrate on two sides of the pseudo gate structure; the substrate comprises a first region and a second region; the first region is used for forming an N-type field effect transistor, and the second region is used for forming a P-type field effect transistor;
removing the pseudo gate structure, and forming a pseudo gate opening in the interlayer dielectric layer;
forming a contact hole in the interlayer dielectric layer, wherein the bottom of the contact hole is exposed out of the source drain doped region;
forming a metal silicide layer on the bottom surface of the contact hole;
after the metal silicide layer is formed, forming a conductive plug which is filled in the contact hole;
forming an N-type work function material layer in the dummy gate opening after the conductive plug is formed;
after forming the dummy gate opening and before forming the contact hole, further comprising: forming interface layers on the side wall and the bottom surface of the pseudo gate opening; forming a gate dielectric layer on the surface of the interface layer;
forming a diffusion barrier layer on the surface of the gate dielectric layer; after forming the diffusion barrier layer and before forming the contact hole, the method further comprises: forming sacrificial structures in the dummy gate openings of the first region and the dummy gate openings of the second region, wherein the sacrificial structures fill the dummy gate openings of the first region and the dummy gate openings of the second region; the sacrificial structure comprises a first sacrificial layer and a second sacrificial layer positioned on the surface of the first sacrificial layer; the first sacrificial layer covers the side walls and the bottom surfaces of the dummy gate openings of the first region and the second region; the second sacrificial layer is positioned on the surface of the first sacrificial layer; performing a first annealing process after forming the first sacrificial layer;
after the forming of the conductive plug and before the forming of the N-type work function material layer, the method further includes: removing the second sacrificial layer in the dummy gate opening of the first region and the dummy gate opening of the second region; after removing the second sacrificial layer, removing the first sacrificial layer in the dummy gate opening of the first region and the dummy gate opening of the second region; removing the diffusion barrier layer in the dummy gate opening of the first region after removing the sacrificial structure in the dummy gate opening of the first region and the dummy gate opening of the second region; forming a P-type work function material layer in the dummy gate opening of the second region, and forming an N-type work function material layer after the P-type work function material layer is formed; the material of the second sacrificial layer comprises silicon oxide.
2. The method for forming a semiconductor device according to claim 1, wherein the contact hole is formed after the dummy gate opening is formed.
3. The method of forming a semiconductor device of claim 2, wherein forming the gate dielectric layer comprises performing a fourth annealing process.
4. The method for forming a semiconductor device according to claim 3, wherein the dummy gate structures are respectively located on a substrate surface of the first region and a substrate surface of the second region; the source-drain doped region is respectively positioned in the substrate of the first region and the substrate of the second region; the contact holes are respectively positioned in the interlayer dielectric layer of the first area and the interlayer dielectric layer of the second area; the N-type work function material layer is respectively positioned in the dummy gate opening of the first area and the dummy gate opening of the second area.
5. The method for forming a semiconductor device according to claim 4, wherein a material of the first sacrificial layer comprises amorphous silicon, polycrystalline silicon, or single crystal silicon.
6. The method for forming a semiconductor device according to claim 4, wherein an annealing temperature of the first annealing process is 800 degrees Celsius to 1000 degrees Celsius.
7. The method for forming a semiconductor device according to claim 4, wherein a second annealing process is performed after the sacrificial structure is formed; the annealing temperature of the second annealing process is 800-1000 ℃.
8. The method for forming a semiconductor device according to claim 1, wherein the method for forming the metal silicide layer comprises: depositing a metal layer on the side wall and the bottom surface of the contact hole; carrying out a third annealing process to enable the metal layer to react with the surface of the source drain doped region to form a metal silicide layer; the third annealing process is a laser annealing process, and the annealing temperature is 750-900 ℃.
9. The method for forming a semiconductor device according to claim 8, wherein a material of the metal silicide layer includes: a titanium silicon compound.
10. The method for forming a semiconductor device according to claim 4, wherein a material of the P-type work function material layer comprises titanium nitride or tantalum nitride.
11. The method of forming a semiconductor device according to claim 1, wherein a material of the N-type work function material layer includes one or a combination of TiAl, TiAlC, TiAlN, and AlN.
12. The method of forming a semiconductor device according to claim 1, further comprising, after forming an N-type work function material layer within the dummy gate opening: and filling metal materials in the dummy gate opening to form a metal gate.
13. A semiconductor device formed by a method using the semiconductor device according to any one of claims 1 to 12.
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