CN110648913A - Gallium arsenide-based diode device structure and manufacturing method - Google Patents
Gallium arsenide-based diode device structure and manufacturing method Download PDFInfo
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- CN110648913A CN110648913A CN201910962088.8A CN201910962088A CN110648913A CN 110648913 A CN110648913 A CN 110648913A CN 201910962088 A CN201910962088 A CN 201910962088A CN 110648913 A CN110648913 A CN 110648913A
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- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 title claims abstract description 61
- 229910001218 Gallium arsenide Inorganic materials 0.000 title claims abstract description 61
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 29
- 229910052751 metal Inorganic materials 0.000 claims abstract description 230
- 239000002184 metal Substances 0.000 claims abstract description 230
- 238000005530 etching Methods 0.000 claims abstract description 58
- 239000000758 substrate Substances 0.000 claims abstract description 54
- 238000000034 method Methods 0.000 claims abstract description 51
- 150000004767 nitrides Chemical class 0.000 claims abstract description 45
- 239000004642 Polyimide Substances 0.000 claims abstract description 40
- 229920001721 polyimide Polymers 0.000 claims abstract description 40
- 239000003990 capacitor Substances 0.000 claims abstract description 22
- 238000000151 deposition Methods 0.000 claims abstract description 10
- 229920002120 photoresistant polymer Polymers 0.000 claims description 36
- 239000010931 gold Substances 0.000 claims description 23
- 239000010936 titanium Substances 0.000 claims description 15
- 229910052737 gold Inorganic materials 0.000 claims description 11
- 150000002739 metals Chemical class 0.000 claims description 11
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 claims description 11
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 10
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 claims description 8
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical group OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 claims description 8
- 229910052719 titanium Inorganic materials 0.000 claims description 8
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 7
- 239000000523 sample Substances 0.000 claims description 7
- 229910000147 aluminium phosphate Inorganic materials 0.000 claims description 4
- 229910052697 platinum Inorganic materials 0.000 claims description 4
- 230000015556 catabolic process Effects 0.000 abstract description 5
- 238000002955 isolation Methods 0.000 abstract description 5
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 9
- 239000011248 coating agent Substances 0.000 description 9
- 238000000576 coating method Methods 0.000 description 9
- 238000000059 patterning Methods 0.000 description 6
- TXEYQDLBPFQVAA-UHFFFAOYSA-N tetrafluoromethane Chemical compound FC(F)(F)F TXEYQDLBPFQVAA-UHFFFAOYSA-N 0.000 description 6
- 238000009713 electroplating Methods 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 4
- BYDQGSVXQDOSJJ-UHFFFAOYSA-N [Ge].[Au] Chemical compound [Ge].[Au] BYDQGSVXQDOSJJ-UHFFFAOYSA-N 0.000 description 3
- 238000001514 detection method Methods 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 238000001704 evaporation Methods 0.000 description 3
- 229910052759 nickel Inorganic materials 0.000 description 3
- 230000003071 parasitic effect Effects 0.000 description 3
- 239000013618 particulate matter Substances 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 238000004140 cleaning Methods 0.000 description 2
- 239000002131 composite material Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000008020 evaporation Effects 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000007747 plating Methods 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 2
- 230000037303 wrinkles Effects 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 230000002708 enhancing effect Effects 0.000 description 1
- FFUAGWLWBBFQJT-UHFFFAOYSA-N hexamethyldisilazane Chemical compound C[Si](C)(C)N[Si](C)(C)C FFUAGWLWBBFQJT-UHFFFAOYSA-N 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 238000005496 tempering Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
- H01L29/66196—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices with an active layer made of a group 13/15 material
- H01L29/66204—Diodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/868—PIN diodes
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The invention discloses a gallium arsenide-based diode device structure and a manufacturing method thereof, wherein the method comprises the following steps: manufacturing P-type ohmic contact metal, a P-type table top, N-type ohmic contact metal and an N-type table top on a substrate of N + type gallium arsenide, I-type gallium arsenide and P + type gallium arsenide which are epitaxially grown layer by layer; depositing a first nitride layer and etching a through hole; manufacturing a P-type connecting metal, an N-type connecting metal and a lower polar plate; depositing a second nitride layer and etching a through hole, wherein the second nitride layer covering the lower polar plate is used as a dielectric layer; manufacturing a polyimide layer and etching a through hole to be used as a pier of the air bridge structure; and manufacturing an air bridge structure at the positions of the dielectric layer and the P-type connecting metal. The polyimide layer is adopted to protect the diode device, the isolation degree between the devices is increased due to the polyimide layer, the breakdown voltage of the capacitor structure is increased, the height difference of the device is reduced, and the subsequent air bridge process becomes stable.
Description
Technical Field
The invention relates to the field of manufacturing of diode devices on semiconductor devices, in particular to a gallium arsenide-based diode device structure and a manufacturing method thereof.
Background
Such a PIN structure is also called a diode if a layer of Intrinsic (Intrinsic) semiconductor is added between the P-type semiconductor and the N-type semiconductor. The traditional diode has larger height difference, which can reduce the reliability of metal interconnection in the air bridge.
Disclosure of Invention
Therefore, a gallium arsenide-based diode device structure and a manufacturing method thereof are needed to be provided, so that the problems of large height difference of a diode and low metal interconnection reliability in an air bridge are solved.
In order to achieve the above object, the inventor provides a method for manufacturing a gallium arsenide-based diode device structure, comprising the following steps:
manufacturing P-type ohmic contact metal on a substrate of N + type gallium arsenide, I-type gallium arsenide and P + type gallium arsenide which are epitaxially grown layer by layer, wherein the P-type ohmic contact metal is connected with the P + type gallium arsenide;
etching the I-type gallium arsenide and the P + type gallium arsenide to a preset depth and width by using an etching solution to form a P-type table top;
manufacturing N-type ohmic contact metal on the N + type gallium arsenide outside the P-type mesa, wherein the N-type ohmic contact metal is connected with the N + type gallium arsenide;
etching N + type gallium arsenide to a preset depth and width in the region outside the P-type mesa and the N-type ohmic contact metal to form an N-type mesa;
depositing a first nitride layer, and etching through holes on the P-type ohmic contact metal and the N-type ohmic contact metal;
manufacturing a P-type connecting metal, an N-type connecting metal and a lower polar plate, wherein the P-type connecting metal is connected with the P-type ohmic contact metal through a through hole of a first nitride layer on the P-type ohmic contact metal, the N-type connecting metal is connected with the N-type ohmic contact metal through a through hole of the first nitride layer on the N-type ohmic contact metal, and the lower polar plate is arranged on the region outside the N-type table top and serves as a lower polar plate of a capacitor;
depositing a second nitride layer, etching through holes on the P-type connecting metal and the N-type connecting metal, and using the second nitride layer covered on the lower polar plate as a dielectric layer of the capacitor;
covering the polyimide layer, and etching through holes on the P-type ohmic contact metal and the lower polar plate;
covering the pier photoresistors, developing the P-type connecting metal and the areas on the lower polar plate, using the areas as the bottoms of piers on two sides, reserving the pier photoresistors after the development, and depositing seed layer metal on the pier photoresistors;
covering the bridge surface photoresistor, developing the bridge surface areas between the two side piers, depositing air bridge metal to the piers and the bridge surface, and removing the bridge surface photoresistor and the pier photoresistor to obtain the air bridge, wherein the air bridge metal is also used as an upper polar plate of the capacitor.
Further, the P-type mesa or the N-type mesa is etched twice.
Further, the depth and width of the etching are monitored by a current method, and the current method comprises the following steps:
adding voltage on the two ohmic contact metals to form a closed circuit, and detecting the test current of the circuit by using a probe;
the test current reaches the target current, which indicates that the depth and width of the etching meet the requirements;
the test current is lower than the target current, indicating that the depth and width of the etch are not satisfactory.
Further, the etching solution is a phosphoric acid/hydrogen peroxide etching solution.
Further, the P-type ohmic contact metal has a structure of titanium, gold, and platinum.
Further, the structure of the N-type ohmic contact metal is germanium gold, gold and nickel.
Further, when covering the polyimide, the method also comprises the following steps:
and baking the polyimide layer at a high temperature.
Further, when removing the bridge deck photoresist, the method also comprises the following steps:
and carrying out full exposure on the bridge surface light resistance, and removing the bridge surface light resistance after developing.
The invention provides a gallium arsenide-based diode device structure, which is prepared by any one of the methods for manufacturing the gallium arsenide-based diode device structure.
The invention provides a gallium arsenide-based diode device structure, which comprises: n + type gallium arsenide, I type gallium arsenide and P + type gallium arsenide which are epitaxially grown layer by layer are arranged on the substrate; an N-type table top is arranged on the substrate, the N-type table top is N + type gallium arsenide, a P-type table top and N-type ohmic contact metal are arranged on the N-type table top, the N-type ohmic contact metal is arranged on the outer side of the P-type table top, the P-type table top is I-type gallium arsenide and P + type gallium arsenide, and the P-type table top is provided with the P-type ohmic contact metal; a lower polar plate is arranged on the surface of the substrate outside the N-type mesa;
the P-type ohmic contact metal is provided with P-type connecting metal, the N-type ohmic contact metal is provided with N-type connecting metal, seed layer metal is arranged at the position of a pier taking the P-type ohmic contact metal and the lower polar plate as an air bridge, the seed layer metal is connected with the P-type connecting metal and the dielectric layer, the air bridge metal covers the seed layer metal and serves as the main body part of the air bridge, meanwhile, the air bridge metal also serves as the upper polar plate of the capacitor, and the seed layer metal and the air bridge metal form the air bridge;
nitride layers are arranged between the P-type table board and the N-type ohmic contact metal and between the N-type ohmic contact metal and the lower polar plate, and the nitride layer covered on the lower polar plate is used as a dielectric layer of the capacitor; a polyimide layer is also disposed between the piers of the air bridge, the polyimide layer being on the nitride layer.
Different from the prior art, the technical scheme adopts the polyimide layer to protect the diode device. Due to the polyimide layer, the isolation between devices is increased, the breakdown voltage of a capacitor structure is increased, the height difference of the devices is reduced, and the subsequent air bridge process becomes stable.
Drawings
FIG. 1 is a schematic cross-sectional view of a P-type ohmic contact metal formed on a substrate according to the present invention;
FIG. 2 is a schematic cross-sectional view of a current-based test structure according to the present invention;
FIG. 3 is a schematic cross-sectional view of a P-type mesa fabricated on a substrate according to the present invention;
FIG. 4 is a schematic cross-sectional view of an N-type ohmic contact metal formed on a substrate according to the present invention;
FIG. 5 is a schematic cross-sectional view of an N-type mesa fabricated on a substrate according to the present invention;
FIG. 6 is a cross-sectional view of a first nitride layer formed on a substrate according to the present invention;
FIG. 7 is a schematic cross-sectional view of the present invention showing the formation of a bottom plate, a P-type interconnect metal and an N-type interconnect metal on a substrate;
FIG. 8 is a schematic cross-sectional view illustrating a second nitride layer formed on a substrate according to the present invention;
FIG. 9 is a cross-sectional view of a polyimide layer formed on a substrate according to the present invention;
FIG. 10 is a schematic cross-sectional view illustrating the fabrication of a bridge pier photoresist on a substrate according to the present invention;
FIG. 11 is a cross-sectional view of an air bridge structure formed on a substrate according to the present invention.
Description of reference numerals:
1. p + type gallium arsenide;
2. type I gallium arsenide;
3. n + type gallium arsenide;
4. a P-type ohmic contact metal;
5. a P-type mesa;
6. an N-type ohmic contact metal;
7. an N-type table top;
8. a first nitride layer;
91. a P-type connection metal;
92. an N-type connecting metal;
93. a lower polar plate;
10. a second nitride layer;
11. a polyimide layer;
12. bridge pier photoresistance;
13. seed layer metal;
14. an air bridge metal.
Detailed Description
To explain technical contents, structural features, and objects and effects of the technical solutions in detail, the following detailed description is given with reference to the accompanying drawings in conjunction with the embodiments.
Referring to fig. 1 to 11, the present embodiment provides a method for fabricating a gaas-based diode device structure, which is fabricated on a substrate on which N + gaas 1, I-gaas 2, and P + gaas 3 are epitaxially grown layer by layer, where the substrate is a gaas substrate. The manufacturing method comprises the following steps: manufacturing a P-type ohmic contact metal 4 on the substrate; the specific implementation mode is that a photoresist is coated on P + type gallium arsenide 1, the photoresist is patterned, namely, the position of metal to be deposited is opened by exposure and development, then three metals of titanium (Ti), platinum (Pt) and gold (Au) are plated by adopting the modes of electroplating, evaporation or sputtering, finally, the metal is lifted off and cleaned by removing photoresist, and P type ohmic contact metal 4 is formed on P + type gallium arsenide 3, and the structure is shown in figure 1. The P-type ohmic contact metal of the Ti/Pt/Au metal structure has lower contact resistivity than the traditional ohmic contact.
Then, a P-type table-board 5 is manufactured on the substrate; the specific steps are coating photoresist on the substrate, patterning the photoresist, namely opening the area outside the P-type table-board 5, and then putting the substrate into phosphoric acid (H)3PO4) Hydrogen peroxide (H)2O2) In the etching solution, the photoresist is used as the maskThe P + GaAs 1 to N + GaAs 3 are mold etched, and after each etching but before the photoresist is removed, the depth and width of the etching are monitored by current method to form P-type mesa, the structure is shown in FIG. 3. The test structure of the current method is shown in fig. 2, voltage is connected to two adjacent P-type ohmic contact metals 4 as a power supply, a closed circuit is formed among the substrate, the P-type ohmic contact metals 4 and the power supply, a probe is used for detecting the test current of the circuit, and if the test current reaches the target current, the depth and the width of etching meet the requirements; if the test current does not reach the target current, the depth and width of the etch are not satisfactory. And after the test current is detected by the current method, removing the photoresist. The traditional manufacturing method is used for etching the table top in a single etching mode, and the etching depth of the device is not accurate enough. The invention adopts a secondary etching mode for etching the P-type mesa, monitors the depth and the width of etching by adopting a current method in each etching process (after etching but before removing the photoresistance), and judges whether the etching meets the requirement or not by using a mode that the test current in the probe detection circuit reaches the target current. The shape control of the etching in the whole operation process is more accurate than the traditional measuring mode by using a thickness measuring instrument and does not generate particle pollution.
Then, manufacturing an N-type ohmic contact metal 6; coating photoresist, patterning the photoresist, namely exposing and developing to open a part for manufacturing the N-type ohmic contact metal 6, plating three metals of germanium gold (AuGe), nickel (Ni) and gold (Au) in an evaporation mode, performing tempering treatment at 400 ℃ to reduce the N-type ohmic contact resistance 6, finally performing metal lift-off and photoresist removal cleaning to form the N-type ohmic contact metal 6 outside the P-type table-board 5, and connecting the N-type ohmic contact metal 6 with N + type gallium arsenide 3, wherein the structure is shown in figure 4. The N-type ohmic contact metal 6 of AuGe/Ni/Au structure has lower contact resistivity than the conventional ohmic contact.
After the N-type ohmic contact metal 6 is manufactured, an N-type table-board 7 is manufactured on the substrate; the specific process steps are the same as those for making the P-type mesa 5, coating a photoresist on the substrate, patterning the photoresist, i.e. opening the outer region of the N-type mesa 7 to be made, and then lining the substrateBottom by phosphoric acid (H)3PO4) Hydrogen peroxide (H)2O2) The etching solution etches the N + GaAs 3 to the substrate, and the current method is also used to monitor the etching depth and width after each etching before removing the photoresist, so as to remove the photoresist after forming the N-type mesa, and the structure is shown in FIG. 5. In the current method, voltage is not connected to two adjacent N-type ohmic contact metals 6 to be used as a power supply, a closed circuit is formed among the substrate, the N-type ohmic contact metals 6 and the power supply, and a probe is used for detecting the test current of the circuit. The P-type mesa 5 and the N-type ohmic contact metal 6 are on the obtained N-type mesa 7. The invention adopts a secondary etching mode for etching the N-type table-board 7, adopts a current method to monitor the depth and the width of etching in each etching process (after etching but before removing the photoresistance), and judges whether the etching meets the requirements or not by using a mode that the test current in the probe detection circuit reaches the target current. The shape control of the etching in the whole operation process is more accurate than the traditional measuring mode by using a thickness measuring instrument and does not generate particle pollution.
In order to protect the diode device, a first nitride layer 8 is deposited on the substrate; a first nitride layer 8 is coated on the substrate by chemical vapor deposition, the first nitride layer 8 can be silicon nitride or other nitride materials, then the first nitride layer 8 is exposed and developed, so that the area on the P-type ohmic contact metal 4 and the N-type ohmic contact metal 6 and the surface of the substrate outside the N-type mesa 7 are opened, and carbon tetrafluoride (CF) is used4) Etching the first nitride layer 8 to the P-type ohmic contact metal 4 with carbon tetrafluoride (CF)4) Etching the first nitride layer 8 to the N-type ohmic contact metal 6 with carbon tetrafluoride (CF)4) Etching the first nitride layer 8 of the region on one side outside the N-type mesa 7 to the substrate to form through holes respectively, and leaving the first nitride layer 8 outside the through holes, wherein the structure is as shown in fig. 6, the through holes are communicated with the substrate, or the through holes are communicated with the P-type ohmic contact metal 4, or the through holes are communicated with the N-type ohmic contact metal 6, so as to facilitate subsequent manufacture of the connection metal. The first nitride layer 8 is also on the N-type mesa 7 and on the face of the substrate outside the N-type mesa 7.
Then, a lower plate 93, a P-type connecting metal 91 and an N-type connecting metal 92 are manufactured on the substrate; coating a photoresist on the substrate, patterning the photoresist, namely exposing and developing to open the regions on the P-type ohmic contact metal 4 and the N-type ohmic contact metal 6, exposing and developing to open the region outside the N-type mesa 7, then evaporating the upper metal, lifting the metal, removing the photoresist and cleaning, forming a P-type connecting metal 91 on the P-type ohmic contact metal 4, forming an N-type connecting metal 92 on the N-type ohmic contact metal 6, and forming a lower plate 93 on one side outside the N-type mesa 7, wherein the structure is shown in FIG. 7. The P-type connecting metal 91 is connected with the P-type ohmic contact metal 4 through a through hole of the first nitride layer 8 on the P-type ohmic contact metal 4; the N-type connecting metal 92 is connected with the N-type ohmic contact metal 6 through a through hole of the first nitride layer 8 on the N-type ohmic contact metal 6; the lower plate 93 is connected to the substrate through a through hole of the first nitride layer 8 on the side outside the N-type mesa 7, and also serves as a first plate of the MIM capacitor.
In order to prevent short circuits between the connecting metals, a second nitride layer 10 is then deposited on the substrate; the specific process is to deposit the second nitride layer 10 on the substrate, the material of the second nitride layer 10 may be silicon nitride or other nitrides, then perform photolithography patterning, perform etching with the photoresist as a mask, and etch through holes on the P-type connection metal 91 and the N-type connection metal 92 for the subsequent fabrication of an air bridge structure, which is shown in fig. 8. In general, the second nitride layer 10 covers both side regions of the P-type connection metal 91 and the N-type connection metal 92. In order to avoid the electrical connection between the lower plate 93 and the air bridge metal 14, the second nitride layer 10 covering the lower plate 93 also serves as a dielectric layer of the MIM capacitor, and the dielectric layer completely covers the lower plate 93, thereby isolating the air bridge metal 14 from the lower plate 93.
The traditional diode device is not protected by the polyimide layer 11, the height difference is large, and the reliability of metal interconnection can be reduced, so the polyimide layer 11 is manufactured in the invention; the specific process is to cover a polyimide layer 11, and after the polyimide layer 11 is covered, the polyimide layer 11 is immediately baked at a high temperature, and the water vapor of the polyimide layer 11 is baked. After high temperature baking, through holes are etched on the P-type ohmic contact metal 4 and the lower electrode plate 93. The process of etching the through hole includes coating a photoresist on the polyimide layer 11, patterning the photoresist, exposing and developing the regions on the P-type connection metal 91 and the lower plate 93, etching the polyimide layer 11 to the P-type connection metal 91 by using the photoresist as a mask, etching the polyimide layer 11 to the lower plate 93 to obtain a through hole, and communicating the through hole with the P-type connection metal 91 or the through hole with the lower plate 93, wherein the structure is as shown in fig. 9. On one hand, a plurality of metal and nitride layers are manufactured on the substrate, the polyimide layer 11 can reduce the height difference of the substrate, fill the groove of the substrate, reduce the possibility of metal fracture and protect the diode device; on the other hand, the polyimide layer 11 increases the isolation between diode devices, increases the breakdown voltage of the MIM capacitor, and improves the reliability of metal interconnection in the air bridge, so that the subsequent air bridge process becomes stable.
After the polyimide layer 11 is manufactured, manufacturing an air bridge, wherein the air bridge is connected with the MIM capacitor and the P-type ohmic contact metal 4; the polyimide layer 11 is also baked before the air bridge is manufactured, and the polyimide layer 11 generates water vapor in the baking process. A pier photoresist 12 is coated on the polyimide layer 11, the regions on the P-type connection metal 91 and the lower plate 93 are exposed and developed to obtain openings, and the pier photoresist 12 outside the openings is left as a shape defining an air bridge pier. The structure is shown in fig. 10, in which the opening communicates with the P-type connection metal 91 or the opening communicates with the lower plate 93, and the P-type connection metal 91 and the lower plate 93 are used as bottoms of both side piers. Then, two metals of titanium (Ti) and gold (Au) are sputtered to form a seed layer metal 13, and the seed layer metal 13 with the Ti and Au structures is beneficial to enhancing the metal adhesion. Coating bridge deck light resistances on the pier light resistances 12 and the seed layer metal 13, exposing and developing bridge deck areas between the two side piers to obtain openings of areas to be electroplated with metal, then plating air bridge metal 14 in an electroplating mode, forming the air bridge metal 14 covering the seed layer metal 13 in the pier and bridge deck areas on the two sides, and finally removing the light resistances in a metal lifting and bridge deck light resistance full exposure and developing mode, wherein the structure is shown in fig. 11.
The seed layer metal 13 and the air bridge metal 14 form an air bridge, the seed layer metal 13 is connected with the P-type connecting metal 91 through a through hole of the polyimide layer 11 on the P-type connecting metal 91, the seed layer metal 13 is connected with the dielectric layer through a through hole of the polyimide layer 11 on the dielectric layer, the air bridge metal 14 serves as a main body part of the air bridge and covers the seed layer metal 13, and the air bridge metal 14 serves as an upper polar plate, namely a polar plate two of the MIM capacitor. The air bridge metal 14, the dielectric layer and the lower plate 93 form a MIM capacitor, and the air bridge connects the P-type connection metal 91 with the lower plate 93, thereby connecting the MIM capacitor with the P-type ohmic contact metal 4. The air bridge has two layers of metal interconnection technologies (seed layer metal 13 and air bridge metal 14), wherein the seed layer metal 13 adopts a novel air bridge technology, the traditional TiW/Au electroplating mode is changed into a Ti/Au electroplating mode, the adhesion of metal is improved, the resistance of metal is reduced, the working frequency of a device is improved, the loss is reduced, and the parasitic capacitance of a diode device is reduced due to the existence of the air bridge.
During the process of coating the bridge surface photoresist, the wafer is scrapped due to the wrinkle generated by the over-high temperature, and the process is failed due to the metal rupture caused by the over-high pressure during the lift-off process of the photoresist during the process of removing the bridge surface photoresist. Therefore, when the bridge deck photoresist is removed, the invention adopts the method of removing the tackifier (HMDS) required in the process of coating the bridge deck photoresist, then adjusting the coating mode, and then using the photomask to carry out full exposure and development on the bridge deck photoresist to remove the bridge deck photoresist, and at the moment, the bridge pier photoresist is also developed and removed, thereby effectively solving the problem of surface wrinkle caused in the process of removing the air bridge photoresist. The bridge surface light resistor and the pier light resistor use the same-layer light shield, so that the manufacturing cost is saved.
The invention adopts a secondary etching mode for etching the table-board, monitors the depth and the width of etching by adopting a current method in the etching process, and judges whether the etching meets the requirement or not by using a mode that the test current in the probe detection circuit reaches the target current. The shape control of the etching in the whole operation process is more accurate than the traditional measuring mode by using a thickness measuring instrument and does not generate particle pollution.
The polyimide layer can reduce the height difference of the substrate, fill and level the groove of the substrate, reduce the possibility of metal fracture and protect the device; on the other hand, the polyimide layer increases the isolation between devices, increases the capacitor breakdown voltage of the MIM and enables the subsequent air bridge process to be stable. The air bridge has a metal interconnection technology (seed layer metal and air bridge metal) of two layers of metal, wherein the seed layer metal is in a structure of Ti (titanium)/Au (gold), so that the adhesion of the metal is improved, the resistance of the metal is reduced, the working frequency of the device is improved, the loss is reduced, and the parasitic capacitance of the diode device is reduced due to the existence of the air bridge.
The invention provides a gallium arsenide-based diode device structure, comprising: n + type gallium arsenide 3, I type gallium arsenide 2 and P + type gallium arsenide 1 which are epitaxially grown layer by layer on the substrate, wherein the substrate is a gallium arsenide substrate; an N-type table-board 7 is arranged on the substrate, and the N-type table-board 7 is N + type gallium arsenide 3; the N-type table top 7 is provided with a P-type table top 5 and N-type ohmic contact metal 6, the N-type ohmic contact metal 6 is arranged on the outer side of the P-type table top 5, the N-type ohmic contact metal 6 is a composite metal structure of germanium gold (AuGe), nickel (Ni) and gold (Au), and the N-type ohmic contact metal 6 has lower contact resistivity than the traditional ohmic contact; the P-type table top 5 is I-type gallium arsenide 2 and P + type gallium arsenide 1, a P-type ohmic contact metal 4 is arranged on the P-type table top 5, the P-type ohmic contact metal 4 is a composite metal structure of titanium (Ti), platinum (Pt) and gold (Au), and the P-type ohmic contact metal 4 has lower contact resistivity than the traditional ohmic contact; a lower polar plate 93 is arranged on the surface of the substrate outside the N-type table surface 7;
the P-type ohmic contact metal 4 is provided with a P-type connection metal 91, the N-type ohmic contact metal 6 is provided with an N-type connection metal 92, the P-type ohmic contact metal 4 and the lower polar plate 93 are used as bridge piers of the air bridge, the seed layer metal 13 is connected with the P-type connection metal 92 and the dielectric layer, the air bridge metal 14 covers the seed layer metal 13 to be used as a main body part of the air bridge and also be used as an upper polar plate of the capacitor, and the seed layer metal 13 and the air bridge metal 14 form the air bridge. The seed layer metal 13 is titanium (Ti) and gold (Au), and replaces the traditional TiW and Au structures, so that the adhesiveness of the metal is improved, the resistance value of the metal is reduced, the working frequency of the device is improved, and the loss is reduced. The presence of the air bridge also reduces the parasitic capacitance of the diode device.
And nitride layers are arranged between the P-type mesa 5 and the N-type ohmic contact metal 6 and between the N-type ohmic contact metal 6 and the lower polar plate 93, and have a protection effect on a diode device, namely, the short circuit between the metals is prevented. A polyimide layer 11 is also provided between the piers of the air bridge, the polyimide layer 11 being on the nitride layer. On one hand, the polyimide layer 11 can reduce the height difference of the substrate, fill the groove of the substrate, reduce the possibility of metal fracture and protect the diode device; on the other hand, the polyimide layer 11 increases the isolation between diode devices, increases the breakdown voltage of a capacitor, and improves the reliability of metal interconnection in the air bridge, so that the subsequent air bridge process becomes stable.
It should be noted that, although the above embodiments have been described herein, the invention is not limited thereto. Therefore, based on the innovative concepts of the present invention, the technical solutions of the present invention can be directly or indirectly applied to other related technical fields by making changes and modifications to the embodiments described herein, or by using equivalent structures or equivalent processes performed in the content of the present specification and the attached drawings, which are included in the scope of the present invention.
Claims (10)
1. A method for manufacturing a gallium arsenide-based diode device structure is characterized by comprising the following steps:
manufacturing P-type ohmic contact metal on a substrate of N + type gallium arsenide, I-type gallium arsenide and P + type gallium arsenide which are epitaxially grown layer by layer, wherein the P-type ohmic contact metal is connected with the P + type gallium arsenide;
etching the I-type gallium arsenide and the P + type gallium arsenide to a preset depth and width by using an etching solution to form a P-type table top;
manufacturing N-type ohmic contact metal on the N + type gallium arsenide outside the P-type mesa, wherein the N-type ohmic contact metal is connected with the N + type gallium arsenide;
etching N + type gallium arsenide to a preset depth and width in the region outside the P-type mesa and the N-type ohmic contact metal to form an N-type mesa;
depositing a first nitride layer, and etching through holes on the P-type ohmic contact metal and the N-type ohmic contact metal;
manufacturing a P-type connecting metal, an N-type connecting metal and a lower polar plate, wherein the P-type connecting metal is connected with the P-type ohmic contact metal through a through hole of a first nitride layer on the P-type ohmic contact metal, the N-type connecting metal is connected with the N-type ohmic contact metal through a through hole of the first nitride layer on the N-type ohmic contact metal, and the lower polar plate is arranged on the region outside the N-type table top and serves as a lower polar plate of a capacitor;
depositing a second nitride layer, etching through holes on the P-type connecting metal and the N-type connecting metal, and using the second nitride layer covered on the lower polar plate as a dielectric layer of the capacitor;
covering the polyimide layer, and etching through holes on the P-type ohmic contact metal and the lower polar plate;
covering the pier photoresistors, developing the P-type connecting metal and the areas on the lower polar plate, using the areas as the bottoms of piers on two sides, reserving the pier photoresistors after the development, and depositing seed layer metal on the pier photoresistors;
covering the bridge surface photoresistor, developing the bridge surface areas between the two side piers, depositing air bridge metal to the piers and the bridge surface, and removing the bridge surface photoresistor and the pier photoresistor to obtain the air bridge, wherein the air bridge metal is also used as an upper polar plate of the capacitor.
2. The method of claim 1, wherein the P-type mesa or the N-type mesa is etched twice.
3. The method of claim 1 or 2, wherein the etching depth and width are monitored by a galvanic method, the galvanic method comprising the steps of:
adding voltage on the two ohmic contact metals to form a closed circuit, and detecting the test current of the circuit by using a probe;
the test current reaches the target current, which indicates that the depth and width of the etching meet the requirements;
the test current is lower than the target current, indicating that the depth and width of the etch are not satisfactory.
4. The method of claim 1, wherein the etchant is a phosphoric acid/hydrogen peroxide etchant.
5. The method of claim 1, wherein the P-type ohmic contact metal is selected from the group consisting of titanium, gold, and platinum.
6. The method of claim 1, wherein the N-type ohmic contact metal is selected from the group consisting of ge, au, and ni.
7. The method of claim 1, further comprising the steps of, when covering the polyimide:
and baking the polyimide layer at a high temperature.
8. The method of claim 1, further comprising the steps of removing the bridge photoresist:
and carrying out full exposure on the bridge surface light resistance, and removing the bridge surface light resistance after developing.
9. A gaas-based diode device structure, wherein the gaas-based diode device structure is fabricated by the method of any one of claims 1 through 8.
10. A gallium arsenide based diode device structure, comprising: n + type gallium arsenide, I type gallium arsenide and P + type gallium arsenide which are epitaxially grown layer by layer are arranged on the substrate; an N-type table top is arranged on the substrate, the N-type table top is N + type gallium arsenide, a P-type table top and N-type ohmic contact metal are arranged on the N-type table top, the N-type ohmic contact metal is arranged on the outer side of the P-type table top, the P-type table top is I-type gallium arsenide and P + type gallium arsenide, and the P-type table top is provided with the P-type ohmic contact metal; a lower polar plate is arranged on the surface of the substrate outside the N-type mesa;
the P-type ohmic contact metal is provided with P-type connecting metal, the N-type ohmic contact metal is provided with N-type connecting metal, seed layer metal is arranged at the position of a pier taking the P-type ohmic contact metal and the lower polar plate as an air bridge, the seed layer metal is connected with the P-type connecting metal and the dielectric layer, the air bridge metal covers the seed layer metal and serves as the main body part of the air bridge, meanwhile, the air bridge metal also serves as the upper polar plate of the capacitor, and the seed layer metal and the air bridge metal form the air bridge;
nitride layers are arranged between the P-type table board and the N-type ohmic contact metal and between the N-type ohmic contact metal and the lower polar plate, and the nitride layer covered on the lower polar plate is used as a dielectric layer of the capacitor; a polyimide layer is also disposed between the piers of the air bridge, the polyimide layer being on the nitride layer.
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