CN110647355A - Data processor and data processing method - Google Patents
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- CN110647355A CN110647355A CN201810680472.4A CN201810680472A CN110647355A CN 110647355 A CN110647355 A CN 110647355A CN 201810680472 A CN201810680472 A CN 201810680472A CN 110647355 A CN110647355 A CN 110647355A
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Abstract
The present disclosure provides a data processor and a data processing method, wherein the data processor includes: the data conversion module is configured to convert the first data into the second data according to a preset data format, wherein the preset data format comprises a preset granularity and a preset byte order; the control module is configured to control the data conversion module to convert the first data into second data according to the preset data format when determining that the byte order of the first data is different from a preset byte order according to the received control signal. The embodiment of the disclosure has the characteristics of good applicability and capability of reducing cost.
Description
Technical Field
The present disclosure relates to the field of data processing, and in particular, to a data processor, a chip, an electronic device, and a data processing method.
Background
In a bus-structured processor, data is operated in a fixed format within the processor, and when data needs to be written from the processor to the memory, there are two types of data formats for writing to the memory. The first format is called big endian (big endian), i.e. the logical high byte of the internal data of the processor is written into the low address in the memory, and the logical low byte of the internal data of the processor is written into the high address in the memory. The second format is called the little-end format, and the storage order of data in the memory is opposite to that of the big-end format.
The existing processor only supports the operation of data in a big-end format or only supports the operation of data in a small-end format, and cannot be simultaneously suitable for the data processing of the two formats, so the existing technology has the defect of poor applicability.
Disclosure of Invention
In view of this, the embodiments of the present disclosure provide a data processor, a chip, an electronic device, and a data processing method, which have good applicability and can reduce cost.
According to a first aspect of the present disclosure, there is provided a data processor comprising:
the data conversion module is configured to convert the first data into the second data according to a preset data format, wherein the preset data format comprises a preset granularity and a preset byte order;
the control module is configured to control the data conversion module to convert the first data into the second data according to the received control signal when the data format of the first data is determined to be different from a preset data format.
In some embodiments, the data conversion module comprises:
a grouping unit configured to convert data into data corresponding to a preset granularity;
a endian conversion unit configured to convert the data into data corresponding to a preset endian;
the control module is further configured to convert, by a grouping unit, the first data into third data based on the preset granularity and convert, by the endian conversion unit, the third data into second data based on the preset endian when the data granularity of the first data is different from the preset granularity and the endian of the first data is different from the preset endian; or
Converting, by the endian conversion unit, the first data into second data based on the preset endian when the data granularity of the first data is the same as the preset granularity and the endian of the first data is different from the preset endian; or
And when the data granularity of the first data is different from the preset granularity and the byte order of the first data is the same as the preset byte order, converting the first data into second data through a grouping unit based on the preset granularity.
In some embodiments, the control module comprises:
a endian control unit configured to determine an endianness of the first data according to the received control signal, and control a data conversion module to perform data conversion of the first data based on a preset endian when the endian of the first data is different from the preset endian.
In some embodiments, the grouping unit is further configured to divide the first data into a plurality of tuples based on a ratio between a data granularity of the first data and a preset granularity, the plurality of tuples being the third data or the second data, wherein the data granularity of each tuple is the same as the preset granularity.
In some embodiments, the grouping unit is further configured to divide the first data into a plurality of tuples according to an order of an address space of the first data from a lower address to a higher address, and a number of the plurality of tuples is a ratio between a data granularity of the first data and a preset granularity.
In some embodiments, the endian conversion unit is further configured to reverse the endianness of the bytes in each tuple of the first data or the third data, and obtain the second data according to the order of each tuple, wherein the granularity of the data in each tuple is the same as the preset granularity.
In some embodiments, the control module obtains a first address space for storing first data and a second address space for storing second data based on the control signal;
the data conversion module acquires first data based on the first address space, converts the first data into second data, and stores the second data into a second address space.
In some embodiments, the data processing device further comprises an arithmetic module configured to perform arithmetic processing on the second data according to a preset arithmetic instruction;
the control module is further configured to determine the preset operation instruction based on the control signal, and control the operation module to perform operation processing on the second data based on the preset operation instruction.
In some embodiments, the control module further comprises:
the detection unit is configured to detect whether the operation module meets a preset condition, and if so, the operation module is controlled to perform operation processing on the second data.
In some embodiments, the operation module includes a plurality of operation units, and the detection unit is further configured to determine that the operation module satisfies a preset condition when there is an idle operation unit.
In some embodiments, the detection unit is further configured to detect whether an address space applied to the operation processing currently executed by the operation module conflicts with an address space of the second data and an address space of a preset operation instruction, and if not, determine that the operation module satisfies a preset condition.
In some embodiments, further comprising:
a storage module;
the control module is further configured to store the control signal, and the first address space of the first data, the granularity information of the first data, and the preset granularity information determined based on the control signal to the storage module.
According to a second aspect of embodiments of the present disclosure, there is provided a data processing chip comprising a data processor as described in any one of the above embodiments.
According to a third aspect of the embodiments of the present disclosure, there is provided an electronic device including the data processing chip of the above embodiments.
According to a fourth aspect of the embodiments of the present disclosure, there is provided a data processing method applied in a data processor and including:
receiving a control signal;
according to the received control signal, when the data format of first data is determined to be different from a preset data format, a data conversion module is controlled to convert the first data into second data;
the data conversion module is configured to convert the first data into the second data according to a preset data format, where the preset data format includes a preset granularity and a preset byte order.
In the embodiment of the disclosure, the data conversion module comprises a grouping unit and a byte order conversion unit,
and the control data conversion module converting the first data into second data includes:
converting, by a grouping unit, the first data into third data based on the preset granularity when the data granularity of the first data is different from the preset granularity, and converting, by the byte order conversion unit, the third data into second data based on the preset byte order when the byte order of the first data is different from the preset byte order; or
Converting, by the endian conversion unit, the first data into second data based on the preset endian when the data granularity of the first data is the same as the preset granularity and the endian of the first data is different from the preset endian; or
And when the data granularity of the first data is different from the preset granularity and the byte order of the first data is the same as the preset byte order, converting the first data into second data through a grouping unit based on the preset granularity.
In the embodiment of the present disclosure, the method further includes:
determining the byte order of the first data according to the received control signal, and controlling a data conversion module to perform data conversion of the first data based on a preset byte order when the byte order of the first data is different from the preset byte order.
In an embodiment of the present disclosure, converting, by a grouping unit, the first data into third data or second data based on the preset granularity includes:
dividing, by a grouping unit, the first data into a plurality of tuples based on a ratio between a data granularity of the first data and a preset granularity, the plurality of tuples being the third data or the second data, wherein the data granularity of each tuple is the same as the preset granularity.
In an embodiment of the present disclosure, dividing the first data into a plurality of tuples based on a ratio between a data granularity of the first data and a preset granularity includes:
the first data is divided into a plurality of byte groups according to the sequence of the address space of the first data from a low address to a high address, and the number of the group of the plurality of byte groups is the same as the ratio between the data granularity of the first data and the preset granularity.
In an embodiment of the present disclosure, converting, by the endian conversion unit, the third data or the first data into the second data based on the preset endian includes:
and transferring the byte sequence in each byte group of the first data or the third data through the byte sequence conversion unit, and obtaining the second data according to the sequence of each byte group, wherein the data granularity of each byte group is the same as the preset granularity.
In the embodiment of the present disclosure, the method further includes:
acquiring a first address space for storing first data and a second address space for storing second data based on the control signal;
the data conversion module acquires first data based on the first address space, converts the first data into second data, and stores the second data into a second address space.
In the embodiment of the present disclosure, the method further includes:
determining the preset operation instruction based on the control signal;
and the control operation module performs operation processing on the second data based on the preset operation instruction.
In the embodiment of the present disclosure, the method further includes:
detecting whether the operation module meets a preset condition or not;
if yes, the operation module is controlled to carry out operation processing on the second data based on the preset operation instruction.
In an embodiment of the present disclosure, the detecting whether the operation module satisfies a preset condition includes:
and when an idle operation unit exists in the operation module, judging that the operation module meets a preset condition.
In an embodiment of the present disclosure, the detecting whether the operation module satisfies a preset condition includes:
detecting whether the address space applied by the currently executed operation processing of the operation module conflicts with the address space of the second data and the address space of a preset operation instruction, and if not, judging that the operation module meets a preset condition.
According to the data conversion module, the data conversion module can be arranged in the data processor, data can be conveniently converted into a required format through the data conversion module, data conversion is not required to be performed through other conversion devices, the use cost of other conversion devices is reduced, meanwhile, the data processor can be suitable for multiple data formats through the arrangement of the data conversion module, and the data processor has good applicability.
Other features and aspects of the present disclosure will become apparent from the following detailed description of exemplary embodiments, which proceeds with reference to the accompanying drawings.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate exemplary embodiments, features, and aspects of the disclosure and, together with the description, serve to explain the principles of the disclosure.
FIG. 1 shows a block diagram of a data processor according to an embodiment of the present disclosure;
FIG. 2 shows a block diagram of a data conversion module in a data processor according to an embodiment of the present disclosure;
FIG. 3 shows a block diagram of a control module in a data processor according to an embodiment of the present disclosure;
FIG. 4 shows a block diagram of a data processor in accordance with an embodiment of the present disclosure;
FIG. 5 shows a flow diagram of a data processing method according to an embodiment of the present disclosure;
fig. 6 shows a block diagram of a grouping unit according to an embodiment of the present disclosure.
Detailed Description
Various exemplary embodiments, features and aspects of the present disclosure will be described in detail below with reference to the accompanying drawings. In the drawings, like reference numbers can indicate functionally identical or similar elements. While the various aspects of the embodiments are presented in drawings, the drawings are not necessarily drawn to scale unless specifically indicated.
The word "exemplary" is used exclusively herein to mean "serving as an example, embodiment, or illustration. Any embodiment described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments.
Furthermore, in the following detailed description, numerous specific details are set forth in order to provide a better understanding of the present disclosure. It will be understood by those skilled in the art that the present disclosure may be practiced without some of these specific details. In some instances, methods, means, elements and circuits that are well known to those skilled in the art have not been described in detail so as not to obscure the present disclosure.
Fig. 1 is a block diagram of a data processor according to an embodiment of the present disclosure, where the data processor of the embodiment of the present disclosure may be configured as a chip for data processing, or may also be disposed in an electronic device to perform corresponding data processing operations, and the data processor may implement simultaneous adaptation to a big-end format and a small-end format, thereby improving applicability, and reducing cost.
As shown in fig. 1, a data processor of an embodiment of the present disclosure may include: a data conversion module 100 and a control module 200 connected to the data conversion module 100.
The data conversion module 100 may convert the first data into the second data according to a preset data format, where the preset data format includes a preset granularity and a preset byte order. The control module 200 may control the data conversion module 100 to convert the first data into the second data according to a preset data format when determining that the byte order of the first data is different from a preset byte order according to the received control signal.
In the embodiment of the present disclosure, the data conversion module 100 may convert the first data into the second data according to the data conversion instruction transmitted by the control module 200, where the conversion may include converting the first data into the second data having the predetermined endian format according to the predetermined granularity. Where data granularity refers to the number of byte bits of data, such as 8 bits, 16 bits, 32 bits, 64 bits, etc., the disclosure is not limited thereto. The endianness refers to whether the sequence of bytes during storage and the sequence during input (output) are first-come, first-come or last-come, that is, the endianness can include endian in big-end format and endian in little-end format. Endian in big-end format refers to a logical high order byte of data being written to a low address in the address space and a logical low order byte of data being written to a high address in the address space. Endian in little-endian format refers to a logical high-order byte of data being written to a high address of the address space and a logical low-order byte of data being written to a low address of the address space.
The control module 200 in the embodiment of the disclosure may receive the control signal, and may obtain, according to the received control signal, a first address space of first data that needs to be executed with a data processing operation, a data format of the first data, a preset data format of second data that needs to be output to execute the data processing operation, a preset operation instruction for executing the data processing operation, and a second address space of the second data that is output after executing the data processing operation. The first address space may include a start address and an end address for storing the first data, and correspondingly, the second address space may also include a start address and an end address for storing the second data, and the data format of the first data may include the data granularity and the byte order of the first data, and the preset data format may include the data format of the second data, such as the preset granularity and/or the preset byte order.
The control module 200 of the embodiment of the present disclosure may store the control signal or each information obtained based on the control signal into a storage module, which may be a separate storage device within the data processor from the control module 200 and the data conversion module 100, or a buffer or a memory provided within the control module 200. The disclosed embodiments are not so limited. The modules or devices in the data processor may be facilitated to retrieve corresponding data or instructions therefrom by storing the control signals or various information obtained based on the control signals to the memory module. Wherein, the storage module can include: one or any combination of a register and a cache, specifically, the cache may be used to store the computation instruction; the registers may be used to store the machine learning model, the data, and a scalar; the cache is a scratch pad cache.
The control module 200 may obtain the above-mentioned information about the data conversion operation according to the received control signal, and may correspondingly control the data conversion module 100 to perform the related data conversion operation. The control module 200 may determine whether the endian of the first data is the same as the preset endian based on the control signal, if so, the data conversion module 100 is not required to perform the endian conversion operation of the data, and if not, a data conversion instruction may be sent to the data conversion module 100 to control the data conversion module 100 to convert the first data into the second data corresponding to the preset data format.
Fig. 2 shows a block diagram of a data conversion module in a data processor according to an embodiment of the present disclosure, wherein the data conversion module 100 may include a grouping unit 101 and an endian conversion unit 102, wherein the grouping unit 101 may be configured to divide first data into a plurality of tuples according to a preset granularity to obtain third data, and the endian conversion unit 102 may be configured to convert an endian of the data into a preset endian. The data conversion module 100 may obtain a first address space of the first data based on the data conversion instruction transmitted from the control module 200, so as to read the corresponding first data according to the first address space, may also obtain a second address space for storing the second data, may store the converted second data in the second address space, and may also obtain a data format of the first data and a preset data format of the second data.
The control module 200 may control the grouping unit 101 to group the first data based on the preset granularity by sending a corresponding data conversion instruction to the data conversion module 100 to obtain third data when the data granularity of the first data is different from the preset granularity and the byte order of the first data is different from the preset byte order, where the granularity of each byte group of the third data is the same as the preset granularity; and the third data may be converted into the second data based on a preset endian by the endian conversion unit 102.
Based on the above configuration, that is, when the endianness of the first data is different from the preset endianness, the grouping unit 101 may group the first data so that the data granularity of each group is the preset granularity, and then the endianness of the first data may be converted into the preset endianness by the endianness conversion unit 102, so as to obtain the second data meeting the preset data format.
Correspondingly, fig. 3 shows a block diagram of a control module in a data processor according to an embodiment of the present disclosure, where the control module 200 in the embodiment of the present disclosure may include a byte-order control unit 201 and a packet control unit 202, where the byte-order control unit 101 may determine a byte order of first data according to a received control signal, and control the data conversion module 100 to perform a data conversion operation based on a preset byte order when the byte order of the first data is different from the preset byte order. And the packet control unit 202 may determine the granularity of the first data according to the received control signal, and determine the number of packet groups for controlling the data conversion module 100 to perform the packet operation when the granularity of the first data is different from a preset granularity order, where the number of packet groups is a ratio between the number of bits of the first data and the preset granularity.
Correspondingly, the grouping control unit 202 may be configured to control the grouping unit 101 to group the first data according to the determined grouping number to obtain third data, and the endian control unit 201 may be configured to control the endian conversion unit 102 to convert the endian of the third data into the preset endian. The packet control unit 202 may obtain the granularity of the first data and the preset granularity of the second data based on the control signal, and further determine the number of packet groups. The endian-ness control unit 201 may control the endian-ness conversion unit 102 to perform data conversion, that is, to convert the third data into the second data, based on a preset endian-ness.
The above is only an embodiment of the control module and the data conversion module in the embodiment of the present disclosure, and in other embodiments, the control module and the data conversion module may have different structures, so long as the control module can control the data conversion module to perform a data conversion operation, which may be regarded as an embodiment of the present disclosure.
The following illustrates a specific process of the data conversion module executing the data conversion operation according to the embodiment of the present disclosure. The grouping unit 101 of the embodiment of the present disclosure may divide the first data into a plurality of tuples based on a ratio between a data granularity of the first data and a preset granularity, and the plurality of tuples are combined to form the third data, wherein the data granularity of each tuple is the same as the preset granularity. Wherein, each byte group at least comprises data of one byte, and each byte is 8-bit data. That is, in the embodiment of the present disclosure, when the grouping operation is performed by the grouping unit 101, the first data may be divided into a plurality of tuples according to the above ratio, and the data within each tuple may be combined, and the third data may be formed from the combined data of each tuple.
In addition, the embodiment of the present disclosure may read the first data according to an address order of a first address space of the first data, and perform data grouping, where the grouping unit 101 may divide the first data into a plurality of tuples according to an order of the address space of the first data from a lower address to a higher address, and a number of the plurality of tuples is a ratio between a data granularity of the first data and a preset granularity. That is, in the embodiment of the present disclosure, when the first data is stored in the corresponding address space, the first data may be stored in an order from a low address to a high address, and therefore, the grouping unit 101 may read the first data according to the order from the low address to the high address, and regroup the first data to obtain a plurality of tuples, where the number of the tuples may be determined according to a ratio between a granularity of the first data and a preset granularity, and each tuple includes data of the preset granularity.
Since the number of bits of data transmitted by the data bus is all multiple of 64 (64 × n), the following illustrates an embodiment in which the data granularity of the first data is converted into 8 bits, 16 bits, 32 bits, or 64 bits by the data conversion module 100.
The preset granularity may be 8 bits, and the first data does not need to be subjected to packet conversion and endian conversion.
Or, when the preset granularity is 16 bits of data, grouping every 2 bytes as a byte group according to the sequence from the low address to the high address of the first address space, at this time, obtaining a plurality of byte groups, where the group number is the ratio between the granularity of the first data and 16, and the granularity of the data in the byte group is 16 bits.
When the preset granularity is 32-bit data, grouping every 4 bytes as a byte group according to the sequence of the first address space from a low address to a high address, wherein the group number is the ratio of the granularity of the first data to 32, and the data granularity in the byte group is 32 bits.
When the preset granularity is 64-bit data, 8 bytes are grouped into a byte group according to the sequence of the first address space from a low address to a high address, the group number is the ratio of the granularity of the first data to 64, and the data granularity in the byte group is 64 bits.
Based on the above configuration, the grouping operation of the first data can be completed. By the method, the group number of the byte groups can be conveniently determined according to the ratio of the data granularity of the first data to the preset granularity, so that third data corresponding to the preset data granularity is obtained.
In the embodiment of the present disclosure, the grouping unit 101 may include a conversion subunit corresponding to a preset granularity, such as at least one of an 8-bit conversion subunit, a 16-bit conversion subunit, a 32-bit conversion subunit, or a 64-bit conversion subunit, or in other embodiments, may also have a conversion subunit of another granularity, and when performing data conversion of the corresponding preset granularity, the corresponding conversion subunit may be controlled to perform data granularity conversion.
Alternatively, in other embodiments of the present disclosure, the grouping unit 101 may include multiple conversion subunits, and fig. 6 shows a block diagram of a grouping unit according to an embodiment of the present disclosure, where the grouping unit may include an 8-bit conversion subunit 1011, a 16-bit conversion subunit 1012, a 32-bit conversion subunit 1013, and a 64-bit conversion subunit 1014, and a selector 1015 connected to each conversion subunit. In other embodiments of the present disclosure, the conversion sub-unit with other granularities may further execute grouping corresponding to the preset granularity, which is not limited in the embodiments of the present disclosure.
The selector 1015 is configured to perform a selection operation of the third data, that is, each of the conversion subunits 1011, 1012, 1013, and 1014 may perform a grouping operation of the first data to obtain the corresponding third data, and the selector 1015 may select a group of the third data corresponding to the preset granularity from the outputs of each of the conversion subunits. When the preset granularity is changed, the third data corresponding to the preset granularity can be conveniently acquired.
In addition, the endian conversion unit 102 in the embodiment of the disclosure is configured to invert the endian of the data, so that the subsequent operation processing can process the data of different endian. The third data converted by the grouping unit 102 may be subjected to byte order conversion, and may be obtained by turning the byte order in each byte group of the third data and obtaining the second data according to the order of each byte group, where the data granularity of each byte group is the same as the preset granularity.
Wherein, when the data granularity of the first data is the same as the preset granularity, the endian conversion unit 102 divides the first data into a plurality of tuples in an order from a low address to a high address for storing the first data, wherein one tuple is taken in a unit of one data granularity. The endianness of the bytes within each tuple is reversed when the endian conversion is performed. For example, for a 16-bit data granularity, 2 bytes may be included within each tuple, where the order of the first byte and the second byte may be reversed. For another example, for a 32-bit data granularity, 4 bytes may be included in each tuple, wherein the order of the first to fourth bytes may be reversed, or for a 64-bit data granularity, 8 bytes may be included in each tuple, wherein the order of the first to eighth bytes may be reversed, and so on, such that endian conversion of data in each tuple may be achieved. After completing the turning of the byte order in the byte group, the second data may be composed according to the order of the byte group, that is, when completing the conversion process of the data byte order, the byte order in the byte group is converted, but the order of the byte group is not changed.
In addition, when the data granularity of the first data is different from the preset granularity, the first data is firstly divided into a plurality of byte groups corresponding to the preset granularity by the grouping unit 101 to form third data, and the byte order of the third data is converted into the preset byte order by the byte order conversion unit 102 to obtain second data. For example, when the data granularity of 16 bits is converted by the grouping unit 101, the first data may be divided into a plurality of tuples in the order of addresses from low to high, each tuple has 2 bytes, and the two bytes in each tuple may be swapped by the endian conversion unit 102, and the order between the tuples is not changed, so as to obtain the second data. Alternatively, when the 32-bit data granularity is converted by the grouping unit 101, the first data may be divided into a plurality of tuples in the order of addresses from low to high, each tuple has 4 bytes, the order of the four bytes in each tuple may be reversed by the endian conversion unit 102, and the order between the tuples is not changed, so that the second data is obtained. Alternatively, when the 64-bit data granularity is converted by the grouping unit 101, the first data may be divided into a plurality of tuples in the order of addresses from low to high, each tuple has 8 bytes, the order of the 8 bytes in each tuple may be reversed by the endian conversion unit 102, and the order between the tuples is not changed, so as to obtain the second data. By analogy, the above embodiments are only for illustrating the endian conversion performed by the endian conversion unit, and in other embodiments, the endian conversion process of data with other granularities may also be performed, which is not illustrated herein.
Further, as shown in fig. 3, in the embodiment of the present disclosure, the control module 200 may further include a detection unit 203, where the detection unit 203 may determine whether a second address space for storing second data in the control signal is in an idle state before the control module 200 controls the data conversion module 100 to perform data conversion, if so, control the data conversion module 100 to perform data conversion, otherwise, control the data conversion module to perform corresponding data conversion operation until the second address space is in the idle state, so as to avoid address collision and data error.
In order to more clearly embody the data conversion process of the embodiment of the present disclosure, the following is exemplified.
When a system to which the data processor of the embodiment of the present disclosure is applied needs to perform data processing, a control signal may be sent to the control module 200 through the control bus, where the control signal may include information such as a first address space of first data that needs to be performed with data processing, a data granularity (e.g., 64 bits) of the first data, a byte order (big-endian format) of the first data, and a second address null of second data to be obtained, a preset data granularity (32 bits) of the second data, and a preset byte order (little-endian format) of the second data. After receiving the control signal, the control module 200 may send a data conversion instruction to the data conversion module 100, so that the grouping unit groups the first data according to a preset data granularity (32 bits) to obtain third data, and adjusts the byte order of each byte group of the third data into a preset byte order (small-end format) through the byte order conversion unit, so as to obtain second data meeting the preset data format, and then the second data may be output to a corresponding second storage space through a data bus, or used for other operation processing.
With the above-described embodiments, the conversion of the data granularity and/or the endian format of the first data can be completed, so that the data processor can be adapted to various first data without performing the data conversion by other devices.
In addition, fig. 4 shows a block diagram of a data processor according to an embodiment of the present disclosure, wherein the data processor may further include an operation module 300 in addition to the data conversion module 100 and the control module 200 described in the above embodiment. The operation module 300 can perform operation processing on the second data according to a preset operation instruction.
As described in the above embodiment, the control module 200 obtains the control signal from the address bus to correspondingly obtain the preset operation instruction for performing the data operation, based on which, the control module 200 may determine the preset operation instruction based on the control signal and control the operation module 300 to perform the operation processing on the second data based on the preset operation instruction.
In the embodiment of the disclosure, when the control module 200 determines that the first data does not need to be converted by the data conversion module 100 based on the control signal, that is, when the byte order of the first data is the same as the preset byte order, the operation module is directly controlled to perform the operation of the data based on the preset operation instruction.
In addition, when the control module 200 determines that the first data needs to be converted by the data conversion module 100 based on the control signal, that is, the byte order of the first data is different from the preset byte order, the control module 200 first converts the first data into the second data by the data conversion module 100, and then the control operation module 300 operates the second data based on the preset operation instruction, so as to obtain the data required by the system. It should be noted that the preset operation instruction in the embodiment of the present disclosure may be set based on different operation requirements, and the system may determine the operation instruction applied to the operation processing of the data according to the requirement, where the operation instruction includes information such as a formula and a rule applied to the operation processing, and the data required by the system may be obtained through the operation processing.
Further, in the embodiment of the present disclosure, before the operation module 300 executes the operation, the control module 200 needs to determine whether the operation module satisfies a preset condition, and only when the preset condition is satisfied, the control module controls the operation module to execute the operation processing operation. The detecting unit 203 in the control module 200 may detect whether the operation module 300 meets a preset condition, and if so, control the operation module to perform operation processing on the second data.
In the embodiment of the present disclosure, the detecting unit 203 may determine whether the operation module 300 has a capability of performing the above operation, if so, the operation module may be controlled to perform the operation on the second data, and if not, the operation module may be controlled to perform the operation on the second data until the operation module can perform the above operation. The operation module 300 may be an electronic device with data operation processing capability, which can process a plurality of operation instructions in parallel, and when there are a plurality of operation operations, the operation module 300 may not be able to smoothly execute more operation operations due to the limitation of the memory or the data processing speed. Therefore, the embodiment of the disclosure may determine that the operation module 300 has the capability of performing the operation when the detection unit 203 determines that the data processing speed of the operation module 300 is higher than the preset speed or the memory space is higher than the preset memory space.
In addition, the operation module 300 in the embodiment of the present disclosure may include a plurality of operation units, and the plurality of operation units may respectively perform different operation operations, and therefore, the detection unit 203 may determine that the operation module satisfies the preset condition when there is an idle operation unit. That is, when there is an operation unit capable of performing the operation, the operation module is controlled to perform the corresponding operation through the idle operation unit.
In the embodiment of the present disclosure, the detecting unit 203 may further detect whether an address space applied by the operation processing currently executed by the operation module 300 conflicts with a second address space of the second data and an address space of the preset budget instruction, and if not, determine that the operation module satisfies the preset condition. The conflict here means that an address space for storing data generated by the operation currently executed by the operation module overlaps with an address space of the second data, or the address space for storing data generated by the operation currently executed by the operation module overlaps with an address space of a preset operation instruction, or the address space for storing data after the second data operation is executed overlaps with an address space used by the operation currently executed by the operation module. And controlling the operation module to execute the operation only when the address has no conflict.
Based on the configuration, the corresponding operation can be executed through the operation module only when the operation module meets the preset condition, so that the data safety is ensured, and meanwhile, the operation efficiency can be improved.
To sum up, the data processor of the embodiment of the present disclosure may be provided with a data conversion module, and the data conversion module may conveniently convert data into a desired format without using other conversion devices to perform data conversion, thereby reducing the use cost of other conversion devices, and meanwhile, the data processor may be adapted to a plurality of data formats by the arrangement of the data conversion module, and has better applicability.
It is understood that the above-mentioned method embodiments of the present disclosure can be combined with each other to form a combined embodiment without departing from the logic of the principle, which is limited by the space, and the detailed description of the present disclosure is omitted.
In addition, the present disclosure also provides a data processing chip including the data processor in the above embodiments, an electronic device, and a data processing method applied in the data processor, and the corresponding technical solutions and descriptions and corresponding descriptions in the method portions are referred to, and are not described again.
An embodiment of the present disclosure further provides a data processing chip, which includes the data processor as described in any one of the above embodiments.
In some embodiments, a chip package structure is provided, which includes the above chip.
In some embodiments, a board card is provided, which includes the above chip package structure.
An embodiment of the present disclosure further provides an electronic device, which includes the data processor or the data processing chip described in any of the above embodiments, or the above board card.
The electronic device comprises a data processing device, a robot, a computer, a printer, a scanner, a tablet computer, an intelligent terminal, a mobile phone, a vehicle data recorder, a navigator, a sensor, a camera, a server, a cloud server, a camera, a video camera, a projector, a watch, an earphone, a mobile storage, a wearable device, a vehicle, a household appliance, and/or a medical device.
The vehicle comprises an airplane, a ship and/or a vehicle; the household appliances comprise a television, an air conditioner, a microwave oven, a refrigerator, an electric cooker, a humidifier, a washing machine, an electric lamp, a gas stove and a range hood; the medical equipment comprises a nuclear magnetic resonance apparatus, a B-ultrasonic apparatus and/or an electrocardiograph.
In addition, an embodiment of the present disclosure further provides a data processing method, which is applied to the data processor in the foregoing embodiment, and fig. 5 shows a flowchart of the data processing method according to the embodiment of the present disclosure, where the method may include:
s100: receiving a control signal;
s200: according to the received control signal, when the byte order of the first data is determined to be different from the preset byte order, controlling a data conversion module to convert the first data into second data according to a preset data format;
the data conversion module is configured to convert the first data into the second data according to a preset data format, where the preset data format includes a preset granularity and a preset byte order.
In an embodiment of the present disclosure, the data conversion module includes a grouping unit and a endian conversion unit,
and, the converting the first data into the second data according to a preset data format by the control data converting module includes:
dividing the first data into a plurality of byte groups based on the preset granularity through a grouping unit to obtain third data;
converting, by the endian conversion unit, the third data into second data based on the preset endian;
wherein the granularity of each tuple of the third data is the same as the preset granularity.
In an embodiment of the present disclosure, dividing, by a grouping unit, the first data into a plurality of tuples based on the preset granularity to obtain third data includes:
dividing the first data into a plurality of byte groups according to the sequence of the address space of the first data from a low address to a high address, wherein the group number of the plurality of byte groups is the same as the ratio of the data granularity of the first data to a preset granularity;
obtaining the third data based on the plurality of tuples.
In an embodiment of the present disclosure, converting, by the endian conversion unit, the third data into second data based on the preset endian includes:
and transferring the byte sequence in each byte group of the third data through the byte sequence conversion unit, and obtaining the second data according to the sequence of each byte group.
In an embodiment of the present disclosure, the method further comprises:
acquiring a first address space for storing first data and a second address space for storing second data based on the control signal;
the data conversion module acquires first data based on the first address space, converts the first data into second data, and stores the second data into a second address space.
In an embodiment of the present disclosure, the method further comprises:
determining the preset operation instruction based on the control signal;
and the control operation module performs operation processing on the second data based on the preset operation instruction.
In an embodiment of the present disclosure, the method further comprises:
detecting whether the operation module meets a preset condition or not;
if yes, the operation module is controlled to carry out operation processing on the second data based on the preset operation instruction.
In an embodiment of the present disclosure, the detecting whether the operation module satisfies a preset condition includes:
when an idle operation unit exists in the operation module, judging that the operation module meets a preset condition; and/or
Detecting whether the address space applied by the currently executed operation processing of the operation module conflicts with the address space of the second data and the address space of a preset operation instruction, and if not, judging that the operation module meets a preset condition.
It should be noted that, for simplicity of description, the above-mentioned method embodiments are described as a series of acts or combination of acts, but those skilled in the art will recognize that the present application is not limited by the order of acts described, as some steps may occur in other orders or concurrently depending on the application. Further, those skilled in the art should also appreciate that the embodiments described in the specification are exemplary embodiments and that the acts and modules referred to are not necessarily required in this application.
In the foregoing embodiments, the descriptions of the respective embodiments have respective emphasis, and for parts that are not described in detail in a certain embodiment, reference may be made to related descriptions of other embodiments.
In the embodiments provided in the present application, it should be understood that the disclosed apparatus may be implemented in other manners. For example, the above-described embodiments of the apparatus are merely illustrative, and for example, the division of the units is only one type of division of logical functions, and there may be other divisions when actually implementing, for example, a plurality of units or components may be combined or may be integrated into another system, or some features may be omitted, or not implemented. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection of some interfaces, devices or units, and may be an electric or other form.
The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
In addition, functional units in the embodiments of the present application may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit. The integrated unit may be implemented in the form of hardware, or may be implemented in the form of a software program module.
The integrated units, if implemented in the form of software program modules and sold or used as stand-alone products, may be stored in a computer readable memory. Based on such understanding, the technical solution of the present application may be substantially implemented or a part of or all or part of the technical solution contributing to the prior art may be embodied in the form of a software product stored in a memory, and including several instructions for causing a computer device (which may be a personal computer, a server, or a network device) to execute all or part of the steps of the method described in the embodiments of the present application. And the aforementioned memory comprises: a U-disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a removable hard disk, a magnetic or optical disk, and other various media capable of storing program codes.
Those skilled in the art will appreciate that all or part of the steps in the methods of the above embodiments may be implemented by associated hardware instructed by a program, which may be stored in a computer-readable memory, which may include: flash Memory disks, Read-Only memories (ROMs), Random Access Memories (RAMs), magnetic or optical disks, and the like.
The foregoing detailed description of the embodiments of the present application has been presented to illustrate the principles and implementations of the present application, and the above description of the embodiments is only provided to help understand the method and the core concept of the present application; meanwhile, for a person skilled in the art, according to the idea of the present application, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present application.
Claims (19)
1. A data processor, comprising:
the data conversion module is configured to convert the first data into the second data according to a preset data format, wherein the preset data format comprises a preset granularity and a preset byte order;
the control module is configured to control the data conversion module to convert the first data into second data according to the preset data format when determining that the byte order of the first data is different from a preset byte order according to the received control signal.
2. The data processor of claim 1, wherein the data conversion module comprises:
a grouping unit configured to group data by a preset granularity to obtain a plurality of tuples;
a endian conversion unit configured to convert the data into data corresponding to a preset endian;
the control module is further configured to, when the endianness of the first data is different from the preset endianness, divide the first data into a plurality of tuples by a grouping unit based on the preset granularity to obtain third data, and convert the third data into second data by the endian conversion unit based on the preset endian, wherein the granularity of each tuple of the third data is the same as the preset granularity.
3. The data processor of claim 2, wherein the grouping unit is further configured to divide the first data into a plurality of tuples according to an order of an address space of the first data from a lower address to a higher address, and a number of the plurality of tuples is a ratio between a data granularity of the first data and a preset granularity.
4. The data processor of claim 2, wherein the endian conversion unit is further configured to reverse the endianness of the bytes in the respective tuples of the third data and obtain the second data in the order of the respective tuples.
5. The data processor of claim 1, wherein the control module obtains a first address space for storing first data and a second address space for storing second data based on the control signal;
the data conversion module acquires first data based on the first address space, converts the first data into second data, and stores the second data into a second address space.
6. The data processor according to claim 1, further comprising an arithmetic module configured to perform arithmetic processing on the second data according to a preset arithmetic instruction;
the control module is further configured to determine the preset operation instruction based on the control signal, and control the operation module to perform operation processing on the second data based on the preset operation instruction.
7. The data processor of claim 6, wherein the control module further comprises:
the detection unit is configured to detect whether the operation module meets a preset condition, and if so, the operation module is controlled to perform operation processing on the second data.
8. The data processor of claim 7, wherein the operation module comprises a plurality of operation units, and the detection unit is further configured to determine that the operation module satisfies a preset condition when there is an idle operation unit; and/or
The detection unit is further configured to detect whether an address space applied to the operation processing currently executed by the operation module conflicts with an address space of the second data and an address space of a preset operation instruction, and if not, the operation module is judged to meet a preset condition.
9. The data processor of claim 1, further comprising:
a storage module;
the control module is further configured to store the control signal, and a first address space of the first data, a data format of the first data, a preset data format of second data, and a second storage space of the second data, which are determined based on the control signal, to the storage module.
10. A data processing chip comprising a data processor as claimed in any one of claims 1 to 9.
11. An electronic device comprising a data processing chip as claimed in claim 10.
12. A data processing method for use in a data processor, comprising:
receiving a control signal;
according to the received control signal, when the byte order of the first data is determined to be different from the preset byte order, controlling a data conversion module to convert the first data into second data according to a preset data format;
the data conversion module is configured to convert the first data into the second data according to a preset data format, where the preset data format includes a preset granularity and a preset byte order.
13. The method of claim 12, wherein the data conversion module comprises a packet unit and a endian conversion unit,
and, the converting the first data into the second data according to a preset data format by the control data converting module includes:
dividing the first data into a plurality of byte groups based on the preset granularity through a grouping unit to obtain third data;
converting, by the endian conversion unit, the third data into second data based on the preset endian;
wherein the granularity of each tuple of the third data is the same as the preset granularity.
14. The method of claim 13, wherein the dividing the first data into a plurality of tuples by a grouping unit based on the preset granularity to obtain third data comprises:
dividing the first data into a plurality of byte groups according to the sequence of the address space of the first data from a low address to a high address, wherein the group number of the plurality of byte groups is the same as the ratio of the data granularity of the first data to a preset granularity;
obtaining the third data based on the plurality of tuples.
15. The method of claim 13, wherein converting, by the endian conversion unit, the third data into second data based on the preset endian includes:
and transferring the byte sequence in each byte group of the third data through the byte sequence conversion unit, and obtaining the second data according to the sequence of each byte group.
16. The method of claim 12, further comprising:
acquiring a first address space for storing first data and a second address space for storing second data based on the control signal;
the data conversion module acquires first data based on the first address space, converts the first data into second data, and stores the second data into a second address space.
17. The method of claim 12, further comprising:
determining the preset operation instruction based on the control signal;
and the control operation module performs operation processing on the second data based on the preset operation instruction.
18. The method of claim 17, further comprising:
detecting whether the operation module meets a preset condition or not;
if yes, the operation module is controlled to carry out operation processing on the second data based on the preset operation instruction.
19. The method of claim 18, wherein the detecting whether the operation module satisfies a preset condition comprises:
when an idle operation unit exists in the operation module, judging that the operation module meets a preset condition; and/or
Detecting whether the address space applied by the currently executed operation processing of the operation module conflicts with the address space of the second data and the address space of a preset operation instruction, and if not, judging that the operation module meets a preset condition.
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| CN201810680472.4A CN110647355B (en) | 2018-06-27 | 2018-06-27 | Data processor and data processing method |
| KR1020207036740A KR102470893B1 (en) | 2018-06-27 | 2019-06-25 | Debug method by breakpoint of on-chip code, chip debug system by on-chip processor and breakpoint |
| EP20217296.1A EP3825841A1 (en) | 2018-06-27 | 2019-06-25 | Method and device for parallel computation of a network model |
| JP2020560786A JP7053891B2 (en) | 2018-06-27 | 2019-06-25 | On-chip code breakpoint debugging method, on-chip processor and breakpoint-based chip debugging system |
| EP19824842.9A EP3798850A4 (en) | 2018-06-27 | 2019-06-25 | On-chip code breakpoint debugging method, on-chip processor, and chip breakpoint debugging system |
| PCT/CN2019/092805 WO2020001438A1 (en) | 2018-06-27 | 2019-06-25 | On-chip code breakpoint debugging method, on-chip processor, and chip breakpoint debugging system |
| US17/138,161 US11789847B2 (en) | 2018-06-27 | 2020-12-30 | On-chip code breakpoint debugging method, on-chip processor, and chip breakpoint debugging system |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112151069A (en) * | 2020-08-20 | 2020-12-29 | 深圳市捷视飞通科技股份有限公司 | Voice data processing method and device, computer equipment and storage medium |
Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7181562B1 (en) * | 2004-03-31 | 2007-02-20 | Adaptec, Inc. | Wired endian method and apparatus for performing the same |
| CN101373461A (en) * | 2003-03-19 | 2009-02-25 | 松下电器产业株式会社 | Data sharing device for shared data between different byte sequence processors and processor |
| CN101645017A (en) * | 2009-09-07 | 2010-02-10 | 深圳市茁壮网络股份有限公司 | Cross-platform byte order processing method, device and byte code running platform |
| CN102150139A (en) * | 2008-09-12 | 2011-08-10 | 瑞萨电子株式会社 | Data processing device and semiconductor integrated circuit device |
| CN102314406A (en) * | 2010-06-30 | 2012-01-11 | 国际商业机器公司 | The method and system that is used for the lazy data sequenceization of compunication |
| CN102789413A (en) * | 2011-05-23 | 2012-11-21 | 同济大学 | System and method for debugging parallel program |
| CN105320513A (en) * | 2014-07-31 | 2016-02-10 | 中国石油化工股份有限公司 | I/O (input/output) method suitable for any SEG-Y seismic data |
| CN106354568A (en) * | 2016-08-23 | 2017-01-25 | 京信通信技术(广州)有限公司 | Method and device for communication between different processes |
| CN106951587A (en) * | 2017-02-15 | 2017-07-14 | 芯启源（南京）半导体科技有限公司 | FPGA debugging systems and method |
-
2018
- 2018-06-27 CN CN201810680472.4A patent/CN110647355B/en active Active
Patent Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101373461A (en) * | 2003-03-19 | 2009-02-25 | 松下电器产业株式会社 | Data sharing device for shared data between different byte sequence processors and processor |
| US7181562B1 (en) * | 2004-03-31 | 2007-02-20 | Adaptec, Inc. | Wired endian method and apparatus for performing the same |
| CN102150139A (en) * | 2008-09-12 | 2011-08-10 | 瑞萨电子株式会社 | Data processing device and semiconductor integrated circuit device |
| CN101645017A (en) * | 2009-09-07 | 2010-02-10 | 深圳市茁壮网络股份有限公司 | Cross-platform byte order processing method, device and byte code running platform |
| CN102314406A (en) * | 2010-06-30 | 2012-01-11 | 国际商业机器公司 | The method and system that is used for the lazy data sequenceization of compunication |
| CN102789413A (en) * | 2011-05-23 | 2012-11-21 | 同济大学 | System and method for debugging parallel program |
| CN105320513A (en) * | 2014-07-31 | 2016-02-10 | 中国石油化工股份有限公司 | I/O (input/output) method suitable for any SEG-Y seismic data |
| CN106354568A (en) * | 2016-08-23 | 2017-01-25 | 京信通信技术(广州)有限公司 | Method and device for communication between different processes |
| CN106951587A (en) * | 2017-02-15 | 2017-07-14 | 芯启源（南京）半导体科技有限公司 | FPGA debugging systems and method |
Non-Patent Citations (1)
| Title |
|---|
| 陈辉; 周自立: "嵌入式系统实验关于大小端转换方法的探讨", 《实验室研究与探索》 * |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112151069A (en) * | 2020-08-20 | 2020-12-29 | 深圳市捷视飞通科技股份有限公司 | Voice data processing method and device, computer equipment and storage medium |
| CN112151069B (en) * | 2020-08-20 | 2024-03-15 | 深圳市捷视飞通科技股份有限公司 | Voice data processing method, device, computer equipment and storage medium |
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|---|---|
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