CN110646898A

CN110646898A - Method of forming a photonic semiconductor device and photonic system

Info

Publication number: CN110646898A
Application number: CN201910558565.4A
Authority: CN
Inventors: 张智杰; 蔡仲豪; 王垂堂; 夏兴国; 余振华
Original assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Current assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority date: 2018-06-27
Filing date: 2019-06-26
Publication date: 2020-01-03
Anticipated expiration: 2039-06-26
Also published as: TW202014746A; US10930628B2; KR20200001536A; DE102019116579A1; US20200006304A1; CN110646898B; US11362077B2; US11605622B2; US20230215853A1; KR102256263B1; US11830864B2; US20210202453A1; TWI743499B; DE102019116579B4; US20220328466A1

Abstract

The method includes forming a plurality of photonic devices in a semiconductor wafer, forming V-grooves in a first side of the semiconductor wafer, forming openings extending through the semiconductor wafer, forming a plurality of conductive features within the openings, wherein the conductive features extend from the first side of the semiconductor wafer to a second side of the semiconductor wafer, forming a polymer material over the V-grooves, depositing a molding material within the openings, wherein the conductive features of the plurality of conductive features are separated by the molding material, removing the polymer material to expose the V-grooves after depositing the molding material, and placing optical fibers within the V-grooves. Embodiments of the invention also relate to methods of forming photonic semiconductor devices and photonic systems.

Description

Method of forming a photonic semiconductor device and photonic system

Technical Field

Embodiments of the invention relate to methods of forming photonic semiconductor devices and photonic systems.

Background

Electrical signals and processing are one technique used for signal transmission and processing. In recent years, optical signals and processing have been used in an increasing number of applications, particularly due to the use of optical fiber related applications for signal transmission.

Optical signals and processing are often combined with electrical signals and processing to provide fully developed applications. For example, optical fibers may be used for long-range signal transmission, and electrical signals may be used for short-range signal transmission as well as processing and control. Thus, a device integrating an optical component and an electronic component is formed for conversion between optical signals and electrical signals, and processing of optical signals and electrical signals. Thus, a package may include an optical (photonic) die containing an optical device and an electronic die containing an electronic device.

Disclosure of Invention

Embodiments of the present invention provide a method of forming a photonic semiconductor device, comprising: forming a plurality of openings through a photonic substrate, wherein the photonic substrate comprises a slot configured to receive an optical fiber, wherein the slot is formed in a top surface of the photonic substrate; forming a plurality of vias over the first redistribution structure electrically connected to the first redistribution structure; placing the photonic substrate over the first redistribution structure, wherein the plurality of vias extend through the plurality of openings in the photonic substrate; forming a sacrificial material in the trench; forming a molding compound within the plurality of openings in the photonic substrate, wherein the molding compound surrounds the plurality of vias; forming a second redistribution structure over the top surface of the photonic substrate, wherein the second redistribution structure is electrically connected to the plurality of vias and the photonic substrate; removing the second redistributed portion to expose the sacrificial material; removing the sacrificial material to expose the trench; and installing an optical fiber in the groove.

Another embodiment of the present invention provides a method of forming a photonic semiconductor device, comprising: forming a plurality of photonic devices in a semiconductor wafer; forming a v-shaped groove in a first side of the semiconductor wafer; forming an opening extending through the semiconductor wafer; forming a plurality of conductive features within the openings, wherein the conductive features extend from a first side of the semiconductor wafer to a second side of the semiconductor wafer; forming a polymer material over the v-shaped groove; depositing a molding material within the opening, wherein the conductive components of the plurality of conductive components are separated by the molding material; after depositing the molding material, removing the polymer material to expose the V-shaped grooves; and placing an optical fiber within the V-groove.

Yet another embodiment of the present invention provides a photonic system including: a photonic substrate comprising a set of waveguides formed in the photonic substrate, the set of waveguides optically coupled to at least one photonic device formed in the photonic substrate; a molding compound in a first region of the photonic substrate, the molding compound extending from a first side of the photonic substrate to a second side of the photonic substrate; at least one via extending through the molding compound from a first side of the molding compound to a second side of the molding compound; a redistribution structure disposed over the at least one via and the photonic substrate, the redistribution structure electrically coupled to the at least one via and the at least one photonic device; and at least one semiconductor device electrically coupled to the at least one photonic device through the redistribution structure.

Drawings

Various aspects of the invention are best understood from the following detailed description when read with the accompanying drawing figures. It should be noted that, in accordance with standard practice in the industry, various components are not drawn to scale. In fact, the dimensions of the various elements may be arbitrarily increased or decreased for clarity of discussion.

Fig. 1 illustrates a plan view of a photonic system according to some embodiments.

Fig. 2A-2B illustrate cross-sectional views of a photonic system according to some embodiments.

Fig. 3A-3M are cross-sectional views of intermediate steps during a process for forming a photonic system according to some embodiments.

FIG. 4 illustrates a schematic diagram of a photonic system according to some embodiments.

Fig. 5A-5C are various views of a photonic system according to some embodiments.

Fig. 6A-6C are various views of a photonic system according to some embodiments.

Fig. 7A-7I are cross-sectional views of intermediate steps during a process for forming a photonic system according to some embodiments.

Fig. 8A-8C are various views of a photonic system according to some embodiments.

Detailed Description

The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to limit the invention. For example, in the following description, forming a first feature over or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. Further, the present invention may repeat reference numerals and/or characters in the various embodiments. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Also, spatially relative terms, such as "below …," "below …," "lower," "above …," "upper," and the like, may be used herein for ease of description to describe one element or component's relationship to another element (or other) component as illustrated. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

According to some embodiments, a three-dimensional (3D) package including an optical device and an electronic device, and a method of forming the same, are provided. Specifically, a photonic system is formed having a conductive member for transmitting an electrical signal and a waveguide for transmitting an optical signal. The die is coupled to a system over an integrated photonic substrate (e.g., a wafer or other substrate having photonic devices) or within an opening in the integrated photonic substrate. Vias may also be formed within openings in the integrated photonic substrate. The sacrificial material may be used to protect components of the integrated photonic substrate (e.g., slots for fiber mounting) during processing. According to some embodiments, an intermediate stage of forming a package is shown. Some variations of some embodiments are discussed. Like reference numerals are used to refer to like elements throughout the various views and exemplary embodiments.

Embodiments described herein may allow for improved performance and more efficient fabrication of photonic systems. For example, larger vias may be formed to electrically connect the photonic system to another substrate or component. Larger vias may be more conductive, which may improve power efficiency, and may have less loss or distortion at higher frequencies, which may improve the signal-to-noise ratio of the electrical signal and improve the performance of the system at higher frequency operation. In addition, the process flows described herein are less prone to process damage when forming components such as grooves for optical fibers. Some embodiments may also provide additional advantages, such as less metal wiring required within the photonic system or a reduction in the overall thickness of the photonic system.

Fig. 1 illustrates a photonic system 100 according to some embodiments. Photonic system 100 is, for example, a High Performance Computing (HPC) system and includes a plurality of sites 110, each site 110 being a separate computing system (exemplary site 110 labeled in fig. 1, and exemplary sites labeled in fig. 2A-2B). Each site 110 includes one or more dies (e.g., dies 112 or 114, described in more detail below) coupled to an Integrated Photonic Structure (IPS)102, and each site 110 communicates with other sites 110 using an optical network (e.g.,

waveguides

120 or 122, described in more detail below) formed in the IPS 102. Fig. 1 is a diagram of a photonic system 100 with multiple sites 110. Fig. 2A is a diagrammatic representation of photonic system 100 along section a-a ', and fig. 2B is a diagrammatic representation of photonic system 100 along section B-B'. It should be noted that the sections a-a 'and B-B' labeled in fig. 1 for photonic system 100 are for illustration purposes and that the structure of photonic system 100 shown in fig. 2A through 2B or other photonic systems described herein may be different. Some components are not labeled in fig. 1 or fig. 2A-2B, and are discussed in more detail in fig. 3A-3M below.

IPS102 may include a substrate 103, and substrate 103 may be a material such as a glass, ceramic, dielectric, or semiconductor substrate. For example, the substrate 103 may comprise a bulk semiconductor or the like, which may be doped (e.g., with p-type or n-type dopants) or undoped. In some embodiments, the substrate 103 is a wafer, such as a silicon wafer or other type of semiconductor wafer. Other substrate materials such as multilayer or gradient substrates may also be used. In some embodiments, the material of the substrate 103 may include silicon; germanium; a compound semiconductor including silicon carbide, gallium arsenide, gallium phosphide, indium arsenide, and/or indium antimonide; including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and/or GaInAsP, or combinations thereof. In the embodiment shown in fig. 1 and 2A-2B, the substrate 103 is formed from a silicon wafer, such as a 12 inch silicon wafer. In this manner, the photonic system 100 may be a system on a wafer (SoW). In some embodiments, IPS102 can have a thickness between about 100 μm and about 800 μm.

IPS102 may include one or more optical networks, which may be, for example, sets of waveguides formed within IPS 102. In some embodiments, multiple sets of waveguides formed within IPS102 convey optical signals and/or optical power between sites 110. The IPS102 shown in fig. 1 includes a set of power waveguides (power WG)120 and a set of data waveguides (data WG) 122. In other embodiments, only one set of waveguides or more than two sets of waveguides may be used. In some embodiments, the power WG120 delivers optical power to the site 110, and the site 110 may be in the form of Continuous Wave (CW) light. In some embodiments, data WG122 transmits optical signals, which may be in the form of modulated or pulsed light, between bit points 110. In some cases, a waveguide or a group of waveguides may carry optical power and optical signals. In some embodiments, a waveguide set (e.g., power WG120 or data WG122) may also convey optical signals and/or optical power between IPS102 and external components. For example, the waveguide set may be coupled to an external component by one or more optical fibers. As shown in fig. 1, power WG120 is coupled to an optical power source (e.g., LED, laser, etc.) via optical fiber 124. Optical fiber 124 can be mounted to IPS102 through v-groove 126 (see, e.g., fig. 2A-2B). In some embodiments, the optical fiber 124 and the power WG120 are coupled by a mode converter 121, and the mode converter 121 may form part of the power WG 120. The waveguides described herein are examples, and other embodiments may have different waveguides or have different waveguides than the configuration shown.

In some embodiments, the waveguide (e.g., 120 or 122) of the IPS102 is a waveguide, such as a slab waveguide, formed in the substrate 103. For example, the waveguide may be made of silicon surrounded by silicon oxide. In some embodiments, the waveguides may be formed by patterning the silicon substrate 103 such that the waveguides protrude from the top surface of the substrate 103. Silicon oxide may then be formed on the protruding silicon waveguide. Patterning of the substrate 103 may be accomplished with acceptable photolithography and etching techniques. For example, a photoresist may be formed and developed on the front side of the substrate 103. The photoresist may be patterned and then more etching processes may be performed using the patterned photoresist as an etching mask. Specifically, the front surface of the substrate 103 may be etched to form a recess, wherein the remaining, unrecessed portion of the substrate 103 forms a silicon waveguide. Waveguide components such as mode couplers (e.g., mode coupler 121), grating couplers, or other components may be formed in the same step or using separate lithography or etching steps. The etching process may include one or more anisotropic wet or dry etching processes. The silicon waveguide may then be covered with silicon oxide, which may be a thermal oxide or oxide formed by a process such as PVD, CVD, flowable CVD, or the like, or combinations thereof. Other techniques for forming waveguides may also be used. It should be understood that the dimensions of the waveguide depend on the application. In some embodiments, the silicon waveguide has a width between about 300nm and about 700nm, such as about 500nm, and a height between about 100nm and about 500nm, such as about 200 nm.

IPS102 also includes an integrated photonic device (not separately shown in fig. 1 or fig. 2A-2B) that interacts with, controls, or senses optical signals transmitted through the waveguide. These integrated photonic devices may include devices such as optical modulators (e.g., modulators 210A-210B shown in fig. 4), photodetectors (e.g., photodetectors 212A-212B shown in fig. 4), and the like. For example, an optical modulator may be formed and used to modulate continuous light from the power WG120 into modulated light transmitted by the data WG 122. As another example, a photodetector may be formed and used to sense the modulated light from the data WG 122. Additionally, integrated electronic devices such as transistors, diodes, capacitors, resistors, metal wiring, and the like may also be formed within the IPS102 and may be coupled to integrated photonic devices within the IPS 102. In this manner, IPS102 may include one or more photonic integrated circuits. In some embodiments, each site 110 may include an integrated photonic device or an integrated electronic device. An integrated photonic device or an integrated electronic device may be formed in the IPS102 (e.g., in the substrate 103) using suitable techniques known in the art.

In some embodiments, photonic system 100 further includes a via (TV)108 extending through IPS102, connecting an electronic component from one side of IPS102 to another side of IPS 102. The formation of the TV108 is described in more detail in fig. 3A-3C. In some embodiments, one or more openings (e.g., openings 104 shown in fig. 3B-3C) are formed in IPS102 such that one or more TVs 108 extend through each opening. In some embodiments, an opening is formed in IPS102 using suitable photolithography and etching techniques. In some embodiments, the openings may have a lateral dimension of between about 100 μm and about 500 μm. The TV108 may also be surrounded by the molding compound 106. In some embodiments, the molding compound 106 may be a material such as an encapsulant, a resin, a polymer, an oxide, a nitride, another dielectric material, and the like. In some embodiments, the material of the molding compound 106 is selected such that the Coefficient of Thermal Expansion (CTE) of the molding compound 106 is approximately equal to the CTE of the material of the substrate 103 or the package substrate 350 (see fig. 3M). In some embodiments, the CTE of the molding compound 106 is between about 5 ppm/deg.C and about 30 ppm/deg.C, such as about 15 ppm/deg.C. In some cases, by forming openings for multiple TVs 108 in IPS102, TVs 108 may be formed to have larger dimensions than individual openings through IPS102, such as forming vias for individual ones. The use of a larger TV108 may allow for improved electrical performance (e.g., conduction, current loading, high frequency performance, etc.) of the photonic system 100.

Each site 110 of photonic system 100 may include one or more dies, which may include a processor die, a memory die, an Electronic Integrated Circuit (EIC), the like, or combinations thereof. For example, as shown in fig. 1 and 2A-2B, site 110 includes processor die 112 and EIC114, but in other embodiments, a site may include more than one processor die 112 or EIC 114. The processor die 112 may be a Central Processing Unit (CPU), a Graphics Processing Unit (GPU), an Application Specific Integrated Circuit (ASIC), or the like. The processor die 112 may also include memory, such as volatile memory, such as Dynamic Random Access Memory (DRAM), Static Random Access Memory (SRAM), and the like. In some cases, site 110 may include separate dies for processing and for storage. For clarity, the die used for processing, the die used for storage, the die with processing and storage, and combinations of these dies are referred to herein as "processor die 112".

In some embodiments, EIC die 114 may comprise a CPU and may include control circuitry for controlling the operation of the photonic devices associated with sites 110. The EIC die 114 can communicate with the photonic device of the IPS102 using electrical signals. In some embodiments, EIC114 comprises circuitry for processing electrical signals received from photonic devices, such as electrical signals received from photodetectors (e.g., photodetectors 212A-212B in fig. 4). For example, EIC114 may include a controller, transimpedance amplifier, and the like. EICs 114 may be communicatively coupled to one or more processor dies 112. In some cases, EIC114 controls the high frequency signal of the photonic device according to an electrical signal (digital or analog) received from processor die 112. In some embodiments. The functionality of EIC114 may be part of processor die 112, or the functionality of processor die 112 may be part of EIC114, or processor die 112 and EIC114 may be combined together into a single die.

Turning to fig. 3A-3M, cross-sectional views of intermediate steps in the formation of photonic system 300 (see fig. 3M) are shown in accordance with some embodiments. The photonic system 300 may be similar to the photonic system 100 shown in fig. 1 or fig. 2A-2B. In fig. 3A, a redistribution layer (RDL)305 is formed over a carrier substrate 302, and then a via TV108 is formed over the RDL 305. The carrier substrate 302 may comprise, for example, a silicon-based material such as a glass material or silicon oxide, or other materials such as alumina, metals, ceramics, combinations of these, and the like. In some embodiments, a release layer (not shown) may be formed over the carrier substrate 302.

Referring to fig. 3A, a dielectric layer 304 is formed over a carrier substrate 302. The dielectric layer 304 may be formed of one or more suitable dielectric materials such as silicon oxide, silicon nitride, low-k dielectrics such as carbon-doped oxides, very low-k dielectrics such as porous carbon-doped silicon dioxide, polymers, combinations of these, and the like. In some embodiments, the dielectric layer 304 may be Polybenzoxazole (PBO), but any suitable material may be used, such as polyimide or a polyimide derivative. The dielectric layer 304 may be formed by a process such as spin coating, lamination, CVD, etc., or a combination thereof. The dielectric layer 304 may have a thickness between about 5 μm and about 25 μm, such as about 7 μm, although any suitable thickness may be used.

In an embodiment, RDL305 may be formed by initially forming one or more seed layers (not shown) of titanium, copper, or a titanium-copper alloy by a suitable formation process, such as PVD, CVD, sputtering, or the like. A seed layer is formed over the dielectric layer 304. A photoresist (also not shown) may then be formed to cover the seed layer, and then patterned to expose those portions of the seed layer at locations where RDLs 305 will be subsequently formed. Once the photoresist is formed and patterned, a conductive material may be formed on the seed layer. The conductive material may be a material such as copper, titanium, tungsten, aluminum, other metals, combinations thereof, and the like. The conductive material may be formed by a deposition process such as electroplating or electroless plating. However, while the materials and methods discussed are suitable for forming conductive materials, these materials are merely exemplary. RDL305 may alternatively be formed using any other suitable material or any other suitable formation process, such as CVD or PVD. Once the conductive material is formed, the photoresist may be removed by a suitable removal process such as ashing or chemical stripping. In addition, after removing the photoresist, those portions of the seed layer covered by the photoresist may be removed by, for example, a suitable wet or dry etching process, which may use the conductive material as an etch mask. The remaining portions of the seed layer and the conductive material form RDL 305.

A dielectric layer 306 is then formed over dielectric layer 304 and RDL 305. Dielectric layer 306 may be a similar material as dielectric layer 304 and may be formed in a similar manner. Dielectric layer 306 may have a thickness between about 5 μm and about 25 μm (such as about 7 μm), although any suitable thickness may be used. The dielectric layer 306 may then be patterned to expose the portion of the RDL305 above it that forms the TV 108. The dielectric layer 306 may be patterned using suitable photolithography and etching techniques, such as forming a photoresist over the dielectric layer 306, patterning the photoresist, and then etching the dielectric layer 306 using the patterned photoresist as an etch mask. Suitable wet or dry etching may be used.

In an embodiment, the TV108 may be formed by initially forming one or more seed layers 307 of titanium, copper, or a titanium-copper alloy by a suitable formation process (such as PVD, CVD, sputtering, etc.). A seed layer 307 is formed over the dielectric layer 306 and exposed portions of the RDL 305. A photoresist (also not shown) may then be formed to cover the seed layer 307, and then patterned to expose those portions of the seed layer 307 where the TV108 will subsequently be formed. Once the photoresist is formed and patterned, a conductive material may be formed on the seed layer. The conductive material may be, for example, copper, titanium, tungsten, aluminum, other metals, combinations thereof, and the like. The conductive material may be formed by a deposition process such as electroplating or electroless plating. However, while the materials and methods discussed are suitable for forming conductive materials, these materials are merely exemplary. The TV108 may alternatively be formed using any other suitable material or any other suitable formation process, such as CVD or PVD. Once the conductive material is formed, the photoresist may be removed by a suitable removal process such as ashing or chemical stripping. In addition, after removing the photoresist, those portions of the seed layer 307 that are covered by the photoresist may be removed by, for example, a suitable wet or dry etching process, which may use the conductive material as an etch mask. The remaining portion of the seed layer 307 and the conductive material form the TV 108. The TV108 may have a width of between about 100 μm and about 500 μm (such as about 250 μm), or may have a height of between about 100 μm and about 500 (such as about 250 μm), although any suitable dimensions may be used.

Turning to fig. 3B, IPS102 is placed on dielectric layer 306. In some embodiments, IPS102 is mounted to dielectric layer 306 using an adhesive layer (not shown) disposed between IPS102 and dielectric layer 306. As shown in FIG. 3B, each opening 104 in IPS102 is aligned with one or more TVs 108. The IPS102 may include previously described components, such as a power WG120, a data WG122, and a mode converter 121. The IPS102 shown in fig. 3B also includes contact pads 123 that can provide electrical connections to components (e.g., photonic devices) formed in the IPS 102. In some cases, there may be vias making electrical connection between the contact pads 123 of the IPS102 and overlying conductive features or wires (e.g., RDL323 shown in fig. 3G). For the sake of clarity, all suitable combinations of contact pads, vias or similar components are referred to as contact pads 123. IPS102 may also include other components not shown, such as photonic devices, metal wiring, and the like.

In some embodiments, a protective layer 318 is formed over IPS 102. The protective layer 318 may be formed over the IPS102 before placement on the dielectric layer 306 or after the IPS102 is placed on the dielectric layer 306. The protective layer 318 may be formed of one or more suitable dielectric materials, such as silicon oxide, silicon nitride, polymers, combinations of these, and the like. The protective layer 318 may be formed by a process such as spin coating, lamination, CVD, etc., or a combination thereof. The protective layer 318 may have a thickness between about 5 μm and about 25 μm (such as about 7 μm), but any suitable thickness may be used.

IPS102 also includes one or more v-grooves 126, v-grooves 126 being grooves shaped to receive optical fibers (e.g., optical fibers 124 of fig. 1 or 2A). A v-groove 126 may be adjacent to a component, such as a power WG120, a data WG122, or a mode coupler 121, to allow optical coupling between the fiber 124 and the component. In some embodiments, v-groove 126 is formed in IPS102 prior to placement on dielectric layer 306. In some embodiments, the v-groove 126 is formed to have a length (e.g., distance in a direction along the cross-section shown in fig. 3B) of between about 1mm and about 10 mm. In some embodiments, the depth of the v-groove 126 is between about 70 μm and about 110 μm. The v-groove 126 may be formed before the protective layer 318 is formed or after the protective layer 318 is formed. For example, in some embodiments, the protective layer 318 is formed first, and then a region of the protective layer 318 is removed to expose a surface of the IPS 102. Regions of the protective layer 318 may be removed using, for example, a photolithographic patterning process, laser drilling, or other suitable techniques. The v-grooves 126 may then be etched into the exposed surface of the IPS102 using, for example, a dry etch process, a wet etch process, or a combination thereof.

Fig. 3C shows the formation of sacrificial material 320 over v-grooves 126. Sacrificial material 320 is deposited within v-grooves 126 to protect v-grooves 126 during subsequent process steps. In some embodiments, the sacrificial material 320 is formed over the v-grooves 126 by forming a photoresist over the structure, patterning an opening in the photoresist over the v-grooves 126, depositing the sacrificial material 320 within the opening and then removing the photoresist. The sacrificial material 320 may be a dielectric material, for example, a polymer material such as DAF (die attach film), a removable glue, an epoxy, etc., other types of materials, or combinations thereof. In some embodiments, sacrificial material 320 may be formed by a suitable technique, such as CVD, PVD, spin coating, nano-inkjet, and the like. In some embodiments, sacrificial material 320 is formed protruding from v-groove 126 or formed protruding above protective layer 318.

Referring to fig. 3D, a molding compound 106 is formed around the TV 108. A molding compound 106 is deposited within the opening 104 of the IPS102 and may be deposited over the TV108 or over the IPS 102. In this case, the molding compound 106 is formed over the sacrificial material 320, and the sacrificial material 320 prevents the molding compound 106 from forming within the v-groove 126. The molding compound 106 may be formed using CVD, spin-on techniques, and the like.

Turning to fig. 3E, after the molding compound 106 is deposited, a planarization process (e.g., a Chemical Mechanical Polishing (CMP) process) may be performed to remove excess portions of the molding compound 106. The planarization process may also remove excess portions of the TV108, the protective layer 318, or the sacrificial material 320 and may expose the top surface of the TV108, the protective layer 318, the sacrificial material 320, or the contact pad 123. In some embodiments, a separate planarization process is used to remove excess portions of the TV108, the protective layer 318, or the sacrificial material 320 prior to planarization of the molding compound 106.

Turning to FIG. 3F, sacrificial material 320 is removed, and then dielectric layer 322 is formed over IPS102, TV108, and molding compound 106. In some cases, if a molding compound is formed in the v-groove 126, the material of the sacrificial material 320 can be removed using a technique that is less likely to damage or etch the v-groove 126 than the technique of removing the molding compound 106. For example, in embodiments where the sacrificial material 320 is a polymer material, laser drilling may be used to remove the polymer material rather than using an additional lithography or etching step. In this manner, fewer process steps may be required than if the v-grooves 126 were not protected by the sacrificial layer 320. In some embodiments, sacrificial material 320 is not removed prior to forming dielectric layer 322. An exemplary process flow in which the sacrificial material 320 is not removed is described below for the embodiment shown in fig. 7A-7I.

Still referring to FIG. 3F, a dielectric layer 322 is formed over IPS102, TV108 and molding compound 106. A dielectric layer 322 may also be formed on the surface of v-groove 126 as shown in fig. 3F. Dielectric layer 322 may be a similar material as dielectric layer 304 and may be formed in a similar manner. Dielectric layer 322 may have a thickness of between about 4 μm and about 10 μm (such as about 7 μm), although any suitable thickness may be used.

In fig. 3G, RDL323 and contact pad 325 are formed. Prior to forming the RDL323, the dielectric layer 322 is patterned to expose the TV108 and the contact pad 123. The dielectric layer 322 may be patterned using suitable photolithography and etching techniques, such as forming a photoresist over the dielectric layer 322, patterning the photoresist, and then etching the dielectric layer 322 using the patterned photoresist as an etch mask. Suitable wet or dry etches may be used. In an embodiment, RDL323 may be formed similarly to RDL305 previously described. For example, a seed layer may be formed over the dielectric layer 322, a patterned photoresist may be formed over the seed layer, a conductive material may be formed over the seed layer, and then the photoresist may be removed, with the remaining portion of the conductive material forming the RDL 323. A dielectric layer 324 may then be formed over the RDL 323. Dielectric layer 324 may be a similar material as dielectric layer 304 or dielectric layer 322 and may be formed in a similar manner. Dielectric layer 324 may have a thickness between about 4 μm and about 10 μm (such as about 7 μm), but any suitable thickness may be used. In some embodiments, additional RDLs and dielectric layers may be formed over the RDL 323. Additional RDLs and/or dielectric layers may be formed in a similar manner as dielectric layer 322 and RDL 323.

Still referring to fig. 3G, dielectric layer 324 is patterned to expose portions of RDL 323. The dielectric layer 324 may be patterned using suitable photolithography and etching techniques, such as forming a photoresist over the dielectric layer 324, patterning the photoresist, and then etching the dielectric layer 324 using the patterned photoresist as an etch mask. Suitable wet or dry etches may be used. In an embodiment, contact pad 325 may be formed similarly to RDL305 or RDL323 previously described. For example, a seed layer may be formed over the dielectric layer 324, a patterned photoresist may be formed over the seed layer, a conductive material may be formed over the seed layer, and then the photoresist may be removed, with the conductive remaining portion of the material forming the contact pad 325.

Still referring to fig. 3G, an opening 326 is formed that extends through the

dielectric layers

322 and 324 and removes material of the

dielectric layers

322 and 324 within the v-groove 126. In some embodiments, the opening 326 is formed by forming a photoresist over the dielectric layer 324, and then patterning the opening in the photoresist at a location corresponding to the opening 326.

Dielectric layers

322 and 324 may be etched using a suitable etching process, such as a wet etch process or a dry etch process, to form opening 326. For example, an anisotropic dry etch process may be used. In some embodiments, the opening 326 has sloped sidewalls as shown in fig. 3G, but in other embodiments, the opening 326 may have vertical sidewalls. In some embodiments, the width of the opening 326 may be greater than the width of the v-groove 126, such that the opening 326 exposes a portion of the IPS102 surrounding some or all of the v-groove 126. In some embodiments, opening 326 may have a bottom width (e.g., at the bottom surface of dielectric layer 322) of between about 90 μm and about 150 μm or a top width (e.g., at the top surface of dielectric layer 324) of between about 90 μm and about 150 μm.

Turning to fig. 3H, the structure is mounted to a tape 330, which tape 330 may be an adhesive tape, a die attach film, a carrier, or the like. In some embodiments, the material of the band 330 may at least partially fill the opening 326 or the v-groove 126, as shown in fig. 3H. The carrier substrate 302 is then peeled from the dielectric layer 304. For example, in embodiments where the carrier substrate 302 is attached to the dielectric layer 304 using a release layer, the release layer may be decomposed by exposure to light (e.g., UV light) or heat, and then the carrier substrate 302 is separated from the dielectric layer 304.

In fig. 3I, after the carrier substrate 302 is removed, external connections 332 may be formed. An opening is formed in dielectric layer 304 to expose RDL305, and then an external connection 332 is formed that extends through the opening and electrically connects RDL 305. In an embodiment, the openings in the dielectric layer 304 may be patterned using, for example, a laser drilling process. In some embodiments using a laser drilling method, an optional protective layer, such as a light-to-heat conversion (LTHC) layer or a water-soluble protective film (hogomax) layer (not separately shown in fig. 3G), is first deposited over the dielectric layer 304. Once protected, the laser is directed to those portions of the dielectric layer 304 that are desired to be removed to form openings that expose the RDL 305. During the laser drilling process, the drilling energy may be in the range of 0.1mJ to about 30mJ, and the drilling angle is about 0 degrees (perpendicular to the dielectric layer 304) to about 85 degrees relative to the normal to the dielectric layer 304. In other embodiments, the dielectric layer 304 may be patterned using photolithography and etching techniques.

In some embodiments, external connections 332 may be formed over openings in the dielectric layer 304 to provide external connections to the RDL305 and the TV 108. The external connections 332 may be contact bumps such as micro-bumps, solder bumps, or controlled collapse chip connection (C4) bumps, and may comprise a material such as solder, tin, lead-free tin, copper, silver, or the like, or a combination thereof. In embodiments where the external connections 332 are solder bumps, the external connections 332 may be formed by initially forming a solder layer having a thickness of, for example, about 170 μm by any suitable method, such as evaporation, plating, printing, solder transfer, ball placement, and the like. Once the solder layer is formed on the structure, reflow may be performed to shape the solder material into the desired bump shape.

In fig. 3J, the structure is attached to a carrier structure 340. The carrier structure 340 may be, for example, a frame, a metal ring, etc., which is intended to provide support and stability to the structure during and after the lift-off process. In an embodiment, the structure is attached to the carrier structure 340 using an adhesive 342. The adhesive 342 may be a tape, a die attach film, an ultraviolet release tape, or the like, but any other suitable adhesive or attachment may alternatively be used. Once the structure is attached to the carrier structure 340, the tape 330 may be peeled off the structure.

Turning to fig. 3K, processor die 112 and EIC114 are mounted to contact pads 325. As shown in fig. 3K, each site 110 may include one or more processor dies 112 and one or more EICs 114. In some embodiments, processor die 112 or EIC114 is placed using, for example, a pick and place process. Processor die 112 or EIC114 can be connected to contact pads 325, for example, by optionally dipping connectors 334 (e.g., conductive bumps, contact pads, solder balls, etc.) of processor die 112 or EIC114 into the flux, and then physically aligning connectors 334 of processor die 112 or EIC114 with respective contact pads 325 using a pick and place tool. In some cases, reflow may be implemented to bond connections of processor die 112 or EIC114 to contact pads 325. Underfill 336 may be formed between processor die 112 or EIC114 and dielectric layer 324 at site 110. In some cases, underfill 336 may surround connector 334. In an embodiment, the underfill 336 may be a material such as a molding compound, an epoxy, an underfill, a Molded Underfill (MUF), a resin, or the like. In some embodiments, underfill 336 may be a material that is optically transparent (or relatively transparent) to the wavelengths of light used for optical communication within IPS 102.

In fig. 3L-3M, a segmentation process is performed on the structure, forming a photonic system 300. The singulation process may be, for example, a sawing process. In some embodiments, the opening 326 or v-groove 126 extends into the scribe line region, and the singulation process cuts through the portion of the opening 326 or v-groove 126 within the scribe line region. In some embodiments, the singulation process cuts through the v-groove 126 such that one end of the v-groove 126 is open. In some embodiments, after singulation, the v-groove 126 has a length of between about 500 μm and about 2 mm. In some embodiments, photonic system 300 may have a thickness H3 of between about 1mm and about 3 mm.

FIG. 3M shows a cross-sectional view of photonic structure 300 aligned with optical fiber 124, similar to section A-A' labeled above in FIG. 1. As shown in fig. 3M, one or more optical fibers 124 are mounted in a v-groove 126 of IPS 102. An optical fiber 124 may be mounted in each v-groove 126 such that the optical fiber 124 is aligned to optically couple to a waveguide (e.g., 120 or 122) or mode coupler 121. As shown in fig. 3M, in some embodiments, photonic system 300 is attached to a package substrate 350 to form a photonic package. The package substrate 350 may include or be connected to additional photonic or electronic components. The external connections 332 of the photonic system 300 may be electrically connected to the package substrate 350.

The photonic system 300 depicted in fig. 3A through 3M may achieve some advantages. In some cases, the use of a TV108 formed within an opening 104 as described herein may allow for improved electrical connections to the photonic system 300. For example, electrical signals transmitted to or from components of photonic system 300 (e.g., from processor die 112 or EIC114 or to processor die 112 or EIC 114) through TV108 may have improved signal-to-noise ratios and may have less signal loss at higher frequencies. The use of the TV108 may also reduce the total path length for some electrical signal transmissions, which may further improve the signal-to-noise ratio of the signal and reduce power consumption. In addition, using sacrificial material 320 to protect v-grooves 126 may reduce the number of process steps required, as sacrificial material 320 may be easier to remove than other materials. In some cases, by selecting a molding compound 106 having a Coefficient of Thermal Expansion (CTE) similar to the material of the package substrate 350, the likelihood of warping or cracking may be reduced. Additionally, forming additional or more openings 104 within IPS102 and filling the openings 104 with molding compound 106 may improve CTE matching between photonic system 300 and package substrate 350 and further reduce warpage or cracking.

Turning to fig. 4, a schematic diagram of a portion of a photonic system 400 is shown. Photonic system 400 may be similar to photonic system 100 shown in fig. 1 or fig. 2A-2B, photonic system 300 shown in fig. 3L-3M, or other photonic systems described herein. The schematic shown in fig. 4 illustrates optical communication between two

sites

110A and 110B (which may be similar to site 110 described previously). Site 110A includes processor die 112A and EIC 114A. Site 110A also includes an optical modulator 210A and a photodetector 212A formed in IPS102 of photonic system 400. EIC114A includes driver circuit 116A electrically coupled to modulator 210A and configured to control modulator 210A by sending an electrical signal to modulator 210A. The EIC114A also includes a transimpedance amplifier circuit (TIA)118A electrically coupled to the photodetector 212A and configured to receive electrical signals from the photodetector 212A and process the signals. TIA 118A may amplify the current signal, for example, by converting the current signal to a voltage signal, or may amplify the voltage signal by converting the voltage signal to a current signal. Site 110B includes processor die 112B, EIC 114B including driver 116B and TIA 118B, modulator 210B, and photodetector 212B, each of which may be similar to the corresponding components of site 110A. Other configurations, components, arrangements, or combinations thereof are also possible.

IPS102 of photonic system 400 includes a power WG120 that provides optical power 220 (e.g., in the form of continuous light) to each of sites 110A-110B. In some embodiments, the optical power is provided by an external source (e.g., a laser source) and transmitted to the power WG120 through an optical fiber (e.g., the optical fiber 124 shown in fig. 1) coupled to the power WG120 (e.g., through the mode converter 121 shown in fig. 1). IPS102 also includes data WG122, which extends in part between

sites

110A and 110B and transmits optical data signals 222A-222B. As shown in fig. 4, the power WG120 may also be connected to other sites, and the data WG122 may also be connected to other sites or to external components (e.g., via optical fibers).

In the embodiment shown in fig. 4, data WG122 transmits data signal 222A from site 110A to site 110B. The data signal 222A may be, for example, a modulated or pulsed light signal that represents data generated by the processor die 112A. To generate modulated light for data signal 222A, optical power 220 is modulated as it is transmitted through optical modulator 210A, which optical modulator 210A is coupled to power WG120 and data WG 122. The optical modulator 210A may optionally absorb or transmit optical power 220, for example, in accordance with an electrical signal received from the driver 116A, thereby generating a data signal 222A.

Data WG122 may be coupled to photodetector 212B at site 110B such that photodetector 212B receives data signal 222A from site 110A. The photodetector 212B converts the data signal 222A from an optical signal to an electrical signal, which is transmitted to TIA 118B. TIA 118B converts and/or amplifies the electrical signals, which may then be transmitted to processor die 112B and processed. Similarly, site 110B may communicate with site 110A by using modulator 210B of site 110B to generate data signal 222B that is received by photodetector 212A of site 110A. In this manner, data signals 222A-222B may be generated by one site and received by another site, allowing the sites to communicate using the greater communication speeds or bandwidths allowed by these photonic technologies.

Turning to fig. 5A-5C, portions of a photonic system 500 are shown, according to an embodiment. Photonic system 500 may be similar to photonic system 100 or photonic system 300 described previously. In some embodiments, photonic system 500 is formed using a process flow similar to that shown in fig. 3A-3M. Fig. 5A shows a representative plan view, fig. 5B shows a sectional view through a section C-C 'shown in fig. 5A, and fig. 5C shows a sectional view through a section D-D' shown in fig. 5C. In the photonic system 500 of fig. 5A-5C, the processor die 112 and the EIC114 are disposed above the IPS 102. Fig. 5A-5B show processor die 112 and EIC114 disposed directly above IPS102 and TV 108. In other cases, however, processor die 112 and/or EIC114 may be disposed in different locations relative to IPS102 or TV 108.

In the photonic system 500 shown in fig. 5A-5C, two optical fibers 124A-124B are mounted in two v-grooves 126A-126B, respectively. In other embodiments, there may be only one optical fiber or more than two optical fibers. In some embodiments, one or both of the optical fibers 124A-124B may be configured to carry optical power or data signals. The data signals may be transmitted from an external component to photonic system 500 or may be transmitted from photonic system 500 to an external component. In some embodiments, the v-grooves 126A-126B may not be adjacent, and portions of the

dielectric layers

322 and 324 may be disposed between the v-grooves 126A-126B. As shown in fig. 5A-5C, opening 326 in

dielectric layers

322 and 324 exposes v-grooves 126A-126B, and opening 326 may also expose a region of IPS102 around v-grooves 126A-126B. For example, in some cases, the edges of the opening 326 may be offset from the v-grooves 126A-126B by between about 1 μm and about 2 μm.

Turning now to fig. 6A-6C, portions of a photonic system 600 are shown, according to an embodiment. Photonic system 600 may be similar to photonic system 500 described in fig. 5A through 5C or other photonic systems described herein. In some embodiments, photonic system 600 is formed using a process flow similar to that shown in fig. 3A-3M. Fig. 6A shows a representative plan view, fig. 6B shows a sectional view through a section C-C 'shown in fig. 6A, and fig. 6C shows a sectional view through a section D-D' shown in fig. 6A.

In photonic system 600 of fig. 6A-6C, processor die 112, EIC114, and light source die 620 are disposed above IPS 102. The IPS102 shown in fig. 6A-6C also includes grating couplers 610 formed at and near the top surface of the IPS 102. In some embodiments, IPS102 may include more than one grating coupler 610. The grating coupler 610 is a photonic structure configured to receive light (e.g., optical power or optical signal) and couple the light to a waveguide or other photonic structure, such as a power WG120 or a data WG 122.

In some embodiments, light source die 620 is coupled to IPS102 via grating coupler 610. Light source die 620 includes an optical transmitter 621 such as a laser (e.g., a semiconductor laser) or a Light Emitting Diode (LED), which optical transmitter 621 provides optical power or an optical signal that can be transmitted to IPS 102. By incorporating light source die 620 within photonic system 600, optical power may be provided to photonic system 600 without the use of an external light source, such as an external light source coupled to photonic system 600 using an optical fiber. In this manner, optical power may be more efficiently provided to photonic system 600. Any suitable arrangement of TV108, processor die 112, EIC114, or light source die 620 may be used. In some embodiments, light source die 620 is electrically coupled to EIC114 or processor die 112 (e.g., via RDL 323), and signals may be transmitted between light source die 620, EIC114, or processor die 112. For example, processor die 112 may send signals to light source die 620 to control the operation of light source die 620.

In the photonic system 600 shown in fig. 6A-6C, two optical fibers 124A-124B are mounted in two v-grooves 126A-126B, respectively. In other embodiments, there may be only one optical fiber or more than two optical fibers. In some embodiments, one or both of the optical fibers 124A-124B may be configured to carry optical power or data signals. The data signals may be transmitted from an external component to the photonic system 600 or may be transmitted from the photonic system 600 to an external component. In some embodiments, the v-grooves 126A-126B may not be adjacent, and portions of the

dielectric layers

322 and 324 may be disposed between the v-grooves 126A-126B. As shown in fig. 6A-6C, opening 326 in

dielectric layers

322 and 324 exposes v-grooves 126A-126B, and opening 326 may expose a region of IPS102 around v-grooves 126A-126B. For example, in some cases, the edges of the opening 326 may be offset from the v-grooves 126A-126B by between about 1 μm and about 2 μm.

Turning to fig. 7A-7I, cross-sectional views of intermediate steps in the formation of a photonic system 700 (see fig. 7I) are shown, according to some embodiments. Photonic system 700 may be similar to photonic system 100 (see fig. 1 or fig. 2A-2B), or other photonic systems previously described. Similar to photonic system 600 described in fig. 6A-6C, photonic system 700 includes a light source die 620 coupled to IPS 120 via a grating coupler 610. By incorporating light source die 620 within photonic system 700, optical power may be more efficiently provided to photonic system 700 without the use of an external light source.

In fig. 7A, a redistribution layer (RDL)305 and

dielectric layers

304 and 306 are formed over a carrier substrate 302, and then a via (TV)108 is formed over the RDL 305. The carrier substrate 302 may be similar to the carrier substrate 302 described above with reference to fig. 3A-3M. RDL305 and

dielectric layers

304 and 306 may be similar to RDL305 and dielectric layers described above with reference to fig. 3A-3M, and may be formed in a similar manner. The TV108 may be similar to the TV108 described above with reference to fig. 2A-2B or 3A-3M, and may be formed in a similar manner.

Turning to fig. 7B, IPS102 is placed on dielectric layer 306. In some embodiments, IPS102 is mounted onto dielectric layer 306 using an adhesive layer (not shown) disposed on dielectric layer 306. As shown in FIG. 7B, the opening 104 in the IPS102 is aligned with one or more TVs 108. The IPS102 may include previously described components, such as a waveguide (e.g., a power WG120 or a data WG122, not shown in fig. 7B-7I) or a mode converter 121. The IPS102 shown in fig. 7B also includes contact pads 123 that can provide electrical connections to components (e.g., photonic devices) formed in the IPS 102. IPS102 also includes one or more v-grooves 126, and one or more grating couplers 610 formed at or near a top surface of IPS 102. As shown in fig. 7B, a protective layer 318 is formed over IPS102, leaving exposed v-grooves 126. IPS102 may also include other components not shown, such as photonic devices, metal wiring, and the like.

Fig. 7C shows the formation of the sacrificial material 320 over the v-groove 126 and the formation of the molding compound 106 around the TV 108. Sacrificial material 320 is deposited within v-groove 126 to protect v-groove 126 during subsequent process steps and may be similar to the sacrificial material previously described with respect to fig. 3C. A molding compound 106 is deposited within the opening 104 of the IPS102 and may also be deposited over the TV108 or IPS 102. The molding compound 106 may be similar to the molding compound 106 previously described with reference to fig. 3C. In some cases, the molding compound 106 is formed over the sacrificial material 320, and the sacrificial material 320 prevents the molding compound 106 from forming within the v-groove 126. In some cases, removing the sacrificial material 320 within the v-grooves 126 may use fewer process steps than if the molding compound 106 were formed within the v-grooves 126. After depositing the molding compound 106, a planarization process may be performed to remove excess portions of the molding compound 106 and may expose a top surface of the TV108, the sacrificial material 320, or the protective layer 318. In some embodiments, prior to planarization of the molding compound 106, a separate planarization process is used to remove excess portions of the TV108, the protective layer 318, or the sacrificial material 320.

In FIG. 7D, a dielectric layer 322 is then formed over IPS102, sacrificial material 320, TV108 and molding compound 106. In other embodiments, the sacrificial material 320 is removed prior to forming the dielectric layer 322, similar to the process described in fig. 3E-3F. The RDL323 is formed over the dielectric layer 322 and in contact with the TV108 or IPS 102. A dielectric layer 324 is formed over dielectric layer 322 and RDL 323. Dielectric layer 322, RDL323, or dielectric layer 324 may be similar to those described above with reference to fig. 3F-3G, and may be formed in a similar manner.

Still referring to fig. 7D,

openings

326 and 712 are formed extending through the

dielectric layers

322 and 324 to expose the sacrificial material 320 and the protective layer 318 over the grating coupler 610, respectively. In some embodiments,

openings

326 and 712 are formed by forming a photoresist over dielectric layer 324, and then patterning openings in the photoresist that correspond to the locations of

openings

326 and 712.

Dielectric layers

322 and 324 may be etched using a suitable etch process, such as a wet etch process or a dry etch process, to form

openings

326 and 712. For example, an anisotropic dry etch process may be used. In some embodiments, openings 326 and/or 712 have sloped sidewalls as shown in fig. 7D, but in other embodiments, openings 326 and/or 712 may have vertical sidewalls. In some embodiments, opening 326 is formed in a manner similar to that described above with reference to fig. 3G.

Turning to fig. 7E, the structure is mounted to a tape 330, which tape 330 may be an adhesive tape, a die attach film, a carrier, or the like. The carrier substrate 302 is then peeled from the dielectric layer 304. For example, in embodiments where the carrier substrate 302 is attached to the dielectric layer 304 using a release layer, the release layer may be decomposed by exposure to light (e.g., UV light) or heat, and then the carrier substrate 302 is separated from the dielectric layer 304.

In fig. 7F, an external connection 332 is formed. An opening is formed in dielectric layer 304 to expose RDL305, and then an external connection 332 is formed that extends through the opening and electrically connects RDL 305. In an embodiment, the openings in the dielectric layer 304 may be patterned using, for example, a laser drilling method, which may be similar to the method described above with reference to fig. 3I. In some embodiments, external connections 332 may be formed over openings in the dielectric layer 304 to provide external connections to the RDL305 and the TV 108. The external connections 332 may be similar to those previously described with reference to fig. 3I, and may be formed in a similar manner.

In fig. 7G, the structure is attached to a carrier structure 340. The carrier structure 340 may be, for example, a frame, a metal ring, etc., which is intended to provide support and stability to the structure during and after the lift-off process. In an embodiment, the structure is attached to the carrier structure 340 using an adhesive 342. The carrier structure 340 or adhesive 342 may be similar to those previously described with reference to fig. 3J.

Turning to fig. 7H, processor die 112, EIC114, and light source die 620 are mounted to contact pads 325. Each site 110 may include one or more processor dies 112 and one or more EICs 114. Each light source die 620 is mounted above the grating coupler 610 and aligned so that the light emitter 621 emits light towards the grating coupler 610. In some embodiments, processor die 112, EIC114, or light source die 620 are placed using, for example, a pick and place process. Processor die 112, EIC114, or light source die 620 may be connected to contact pads 325, for example, by optionally dipping die's connectors 334 (e.g., conductive bumps, contact pads, solder balls, etc.) into the flux, and then using a pick and place tool to physically align connectors 334 with respective contact pads 325. In some cases, reflow may be performed to bond connector 334 to contact pad 325.

Underfill 336 may be formed between processor die 112 or EIC114 at site 110 and dielectric layer 324. In some cases, underfill 336 may surround connector 334. In an embodiment, the underfill 336 may be a material such as a molding compound, an epoxy, an underfill, a Molded Underfill (MUF), a resin, or the like. An optical underfill 337 may be formed between the light source die 620 and the grating coupler 610. In some embodiments, optical underfill 337 may be a material that is optically transparent (or relatively transparent) to the wavelengths of light used for optical communication within IPS102, or a material that is otherwise selected according to its optical properties (e.g., refractive index). In this manner, light emitted by light emitter 621 may be transmitted through optical underfill 337 to grating coupler 610. The grating coupler 610 may be configured to transmit a portion of the light emitted by the light emitter 621 to another photonic structure, such as a waveguide, a light modulator, a mode coupler, and the like. In some embodiments, underfill 336 and optical underfill 337 are the same material.

In fig. 7I, a structure is subjected to a segmentation process, forming a photonic system 700. In addition, one or more optical roots 124 are mounted into a v-groove 126 of IPS 102. FIG. 7I shows a cross-sectional view aligned with the optical fiber 124, similar to section A-A' labeled above in FIG. 1. In some embodiments, the singulation process cuts through the v-groove 126 such that one end of the v-groove 126 is open. The singulation process may be, for example, a sawing process. In some embodiments, after singulation, the v-groove 126 has a length of between about 500 μm and about 2 mm. After splitting, the optical fiber 124 may be mounted in each v-groove 126 such that the optical fiber 124 is aligned for optical coupling to the waveguide or mode coupler 121. As shown in fig. 7I, EIC114 and light source die 720 are disposed above IPS 102. In some embodiments, photonic system 700 may have a thickness H7 of between about 1mm and about 2 mm. In some embodiments, photonic system 700 is attached to a package substrate (not shown), which may be similar to package substrate 350 depicted in fig. 3M.

In some cases, the photonic system 700 described in fig. 7A through 7I may achieve some advantages. By installing an optical power source (e.g., light source die 620) coupled through grating coupler 610 above IPS102, optical power may be more efficiently provided to photonic system 700. For example, optical power may be more efficiently coupled into the power WG120 as continuous optical power or into the data WG122 as a modulated optical signal. Multiple optical power sources may be coupled in this manner. This allows for increased design flexibility in component placement and increases the design flexibility of how optical power is provided to the photonic system 700.

Fig. 8A-8C illustrate portions of a photonic system 800 according to one embodiment. The photonic system 800 may be similar to the photonic system 700 depicted in fig. 7I or other photonic systems described herein, except that the optical fiber array 802 is used to transmit or receive optical power or optical signals. In some embodiments, photonic system 800 is formed using a process flow similar to that shown for photonic system 700 in fig. 7A-7I. Fig. 8A shows a representative plan view, fig. 8B shows a sectional view through a section C-C 'in fig. 8A, and fig. 8C shows a sectional view through a section D-D' shown in fig. 8A. In photonic system 800 of fig. 8A-8C, processor die 112, EIC114, and light source die 620 are disposed above IPS 102. Any suitable arrangement of the TV108, processor die 112, EIC114, or light source die 620 may be used. In some embodiments, light source die 620 is electrically coupled to EIC114 or processor die 112 (e.g., via RDL 323), and signals may be transmitted between light source die 620, EIC114, or processor die 112. For example, processor die 112 may send signals to light source die 620 to control the operation of light source die 620.

The light source die 620 is coupled to the IPS102 through the grating coupler 610. In other embodiments, light source die 620 may not be present. The optical fiber array 802 is optically coupled to the IPS102 through one or more grating couplers 812 and may be, for example, a polished optical fiber array. For example, grating coupler 812 may couple optical power or optical signals between a waveguide of IPS102 and one or more optical fibers of fiber array 802. Openings 326 are formed in dielectric layers 322 and 324 (see, e.g., fig. 7D), and fiber array 802 is mounted to IPS102 through openings 326. In some embodiments, multiple fiber arrays 802 may be used. The arrangement of the components of photonic system 800 is merely illustrative and any suitable arrangement of components may be used. For example, the fiber array 802 may be mounted in a suitable location away from the edge of the IPS 102. In some embodiments, the photonic system may be coupled to an array of optical fibers similar to those shown in fig. 8A-8C and to optical fibers similar to those shown in fig. 1 or elsewhere herein.

In some cases, the photonic system 800 depicted in fig. 8A through 8C may achieve some advantages. By mounting the fiber array 802 above the IPS102 and coupling through the grating coupler 812, the photonic system 800 can communicate with external components through the fiber array 802. This allows for increased design flexibility in the arrangement of the fiber arrays and components, and increased design flexibility in how external components communicate with the photonic system 800.

Embodiments may realize advantages. By using multiple vias (TVs) disposed within an opening in an Integrated Photonic Substrate (IPS), larger sized vias may be formed than if individual vias were formed in individual openings in the IPS. Better electrical performance can be achieved using larger vias. For example, larger vias may have less resistance and may reduce signal loss, especially at high frequency operation. The TV may be surrounded by a molding compound having a similar Coefficient of Thermal Expansion (CTE) as the IPS and thus reduce the likelihood of warping, cracking, or other problems associated with CTE mismatch. Additionally, the use of a sacrificial material (e.g., sacrificial material 320 or another polymer material) to protect the v-grooves for fiber installation may allow for improved processing. For example, the removal of the sacrificial material may be a process that is more reliable and less prone to damage of the IPS than, for example, patterning a molding compound or removing a molding compound formed over the v-shaped grooves. The thickness of the photonic system may also be reduced by incorporating other dies within the opening of the IPS. In some cases, this may also reduce the metal routing distance between the electrical connection components.

In an embodiment, a method includes forming a plurality of openings through a photonic substrate, wherein the photonic substrate includes a slot configured to receive an optical fiber, wherein the slot is formed in a top surface of the photonic substrate, forming a plurality of vias electrically connected to a first redistribution structure over the first redistribution structure, placing the photonic substrate over the first redistribution structure, wherein the plurality of vias extend through the plurality of openings in the photonic substrate, forming a sacrificial material in the slot, forming a molding compound within the plurality of openings in the photonic substrate, wherein the molding compound surrounds the plurality of vias, forming a second redistribution structure over the top surface of the photonic substrate, wherein the second redistribution structure is electrically connected to the plurality of vias and the photonic substrate, removing a portion of the second redistribution to expose the sacrificial material, removing the sacrificial material to expose the slot, and mounting the optical fiber within the slot. In an embodiment, the method includes performing a planarization process on the molded plastic to expose the sacrificial material. In an embodiment, the method includes placing a plurality of second semiconductor devices over and electrically connected to a second redistribution structure. In an embodiment, the method includes forming a plurality of waveguides within a photonic substrate. In an embodiment, the method includes forming a plurality of photonic devices within a photonic substrate, the plurality of photonic devices optically coupled to a plurality of waveguides. In an embodiment, two or more vias of the plurality of vias extend through the same opening in the photonic substrate. In an embodiment, the method includes forming an opening in the second redistribution structure, and placing a light source die on the second redistribution structure and extending over the opening in the second redistribution structure, the light source die configured to provide optical power to the photonic substrate. In an embodiment, the photonic substrate comprises a semiconductor wafer. In an embodiment, the sacrificial material comprises a polymeric material.

In an embodiment, a method includes forming a plurality of photonic devices in a semiconductor wafer, forming V-grooves in a first side of the semiconductor wafer, forming openings extending through the semiconductor wafer, forming a plurality of conductive features within the openings, wherein the conductive features extend from the first side of the semiconductor wafer to a second side of the semiconductor wafer, forming a polymer material over the V-grooves, depositing a molding material within the openings, wherein the conductive features of the plurality of conductive features are separated by the molding material, removing the polymer material to expose the V-grooves after depositing the molding material, and placing optical fibers within the V-grooves. In an embodiment, the method includes forming a redistribution layer over the semiconductor wafer, the redistribution layer electrically connected to the plurality of photonic devices and electrically connected to the plurality of conductive features. In an embodiment, the redistribution layer is formed after depositing the molding material and before removing the polymer material. In an embodiment, the method includes disposing an Electronic Integrated Circuit (EIC) over a redistribution layer, wherein the EIC is electrically connected to the redistribution layer. In an embodiment, the method includes sawing the semiconductor wafer at the V-shaped grooves after removing the polymer material. In an embodiment, the method includes forming a grating coupler in a first side of a semiconductor wafer. In an embodiment, removing the polymer material includes using laser drilling.

In an embodiment, a photonic system includes a photonic substrate including a set of waveguides formed in the photonic substrate, the set of waveguides optically coupled to at least one photonic device formed in the photonic substrate, a molding compound located in a first region of the photonic substrate, the molding compound extending from a first side of the photonic substrate to a second side of the photonic substrate, at least one via extending through the molding compound from the first side of the molding compound to the second side of the molding compound, a redistribution structure disposed over the at least one via and the photonic substrate, the redistribution structure electrically coupled to the at least one via and the at least one photonic device, and at least one semiconductor device electrically coupled to the at least one photonic device through the redistribution structure. In an embodiment, a coefficient of thermal expansion of a material of the molding compound is about the same as a coefficient of thermal expansion of a material of the photonic substrate. In an embodiment, the at least one semiconductor device comprises a light source. In an embodiment, the photonic substrate includes at least one grating coupler configured to optically couple the array of optical fibers to the set of waveguides.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.

Claims

1. A method of forming a photonic semiconductor device, comprising:

forming a plurality of openings through a photonic substrate, wherein the photonic substrate comprises a slot configured to receive an optical fiber, wherein the slot is formed in a top surface of the photonic substrate;

forming a plurality of vias over the first redistribution structure electrically connected to the first redistribution structure;

placing the photonic substrate over the first redistribution structure, wherein the plurality of vias extend through the plurality of openings in the photonic substrate;

forming a sacrificial material in the trench;

forming a molding compound within the plurality of openings in the photonic substrate, wherein the molding compound surrounds the plurality of vias;

forming a second redistribution structure over the top surface of the photonic substrate, wherein the second redistribution structure is electrically connected to the plurality of vias and the photonic substrate;

removing the second redistributed portion to expose the sacrificial material;

removing the sacrificial material to expose the trench; and

an optical fiber is mounted in the groove.

2. The method of claim 1, further comprising performing a planarization process on the molding compound to expose the sacrificial material.

3. The method of claim 1, further comprising placing a plurality of second semiconductor devices over and electrically connected to the second redistribution structure.

4. The method of claim 1, further comprising forming a plurality of waveguides within the photonic substrate.

5. The method of claim 4, further comprising forming a plurality of photonic devices within the photonic substrate, the plurality of photonic devices optically coupled to the plurality of waveguides.

6. The method of claim 1, wherein two or more vias of the plurality of vias extend through the same opening in the photonic substrate.

7. The method of claim 1, further comprising:

forming an opening in the second redistribution structure; and

placing a light source die on the second redistribution structure and extending over an opening in the second redistribution structure, the light source die configured to provide optical power to the photonic substrate.

8. The method of claim 1, wherein the photonic substrate comprises a semiconductor wafer.

9. A method of forming a photonic semiconductor device, comprising:

forming a plurality of photonic devices in a semiconductor wafer;

forming a v-shaped groove in a first side of the semiconductor wafer;

forming an opening extending through the semiconductor wafer;

forming a plurality of conductive features within the openings, wherein the conductive features extend from a first side of the semiconductor wafer to a second side of the semiconductor wafer;

forming a polymer material over the v-shaped groove;

depositing a molding material within the opening, wherein the conductive components of the plurality of conductive components are separated by the molding material;

after depositing the molding material, removing the polymer material to expose the V-shaped grooves; and

placing an optical fiber within the V-groove.

10. A photonic system comprising:

a photonic substrate comprising a set of waveguides formed in the photonic substrate, the set of waveguides optically coupled to at least one photonic device formed in the photonic substrate;

a molding compound in a first region of the photonic substrate, the molding compound extending from a first side of the photonic substrate to a second side of the photonic substrate;

at least one via extending through the molding compound from a first side of the molding compound to a second side of the molding compound;

a redistribution structure disposed over the at least one via and the photonic substrate, the redistribution structure electrically coupled to the at least one via and the at least one photonic device; and

at least one semiconductor device electrically coupled to the at least one photonic device through the redistribution structure.