CN110634529A - Detection method and memory device - Google Patents
Detection method and memory device Download PDFInfo
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- CN110634529A CN110634529A CN201810641764.7A CN201810641764A CN110634529A CN 110634529 A CN110634529 A CN 110634529A CN 201810641764 A CN201810641764 A CN 201810641764A CN 110634529 A CN110634529 A CN 110634529A
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
- G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/38—Response verification devices
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- For Increasing The Reliability Of Semiconductor Memories (AREA)
Abstract
The invention provides a detection method and a memory device. The detection method comprises the following steps: a first detection procedure is performed. The first detection procedure includes: applying a first positive voltage to a P-well of a flash memory array; applying a ground voltage to all word lines; floating bit lines and source lines; judging whether the leakage current flowing through the P-type trap exceeds a leakage threshold value; and determining that at least one of the word lines is shorted to at least one of the bit lines or the source line when the leakage current exceeds a leakage threshold. By implementing the detection method provided by the invention, the system can know which flash memory array is damaged, so that the system can execute a series of operations to protect the data stored in the flash memory array.
Description
Technical Field
The invention relates to a method for detecting errors of a NOR gate flash memory and a memory device.
Background
Nor gate flash memory utilizes ECC to correct some bit read errors, however some process defects, such as word line to bit line shorts or word line to source line shorts, cause the entire memory array to be erased, or result in read or write errors, or even result in data not being recoverable using ECC.
Therefore, a method for detecting defects in a flash memory array, such as word line to bit line shorts or word line to source line shorts, is needed. In addition, a special reading method is also required to read data stored in a damaged word line, which has data retention. Because the damaged array cannot be erased, a special read method can be used to move the data stored in the damaged array to a redundant array or other arrays for storage.
Disclosure of Invention
In view of the above, the present invention provides a method for testing a flash memory array, wherein the flash memory array comprises a plurality of word lines, a plurality of bit lines and a source line, comprising: executing a first detection procedure, wherein the first detection procedure comprises: applying a first positive voltage to a P-well (well) of the flash memory array; applying a ground voltage to all of the word lines; floating the bit line and the source line; judging whether a leakage current flowing through the P-type well exceeds a leakage threshold value; and determining that at least one of the word lines is shorted to at least one of the bit lines or the source line when the leakage current exceeds the leakage threshold.
According to an embodiment of the present invention, after the step of determining whether at least one of the word lines is shorted to at least one of the bit lines or the source line, the method further includes: executing a second detection procedure, wherein the second detection procedure comprises: sequentially selecting one of the word lines as a selected word line; charging the selected word line to a second positive voltage using a first constant current; applying the ground voltage to all of the bit lines and the source lines; determining whether the selected word line is at a high logic level or a low logic level; determining that the selected word line is not shorted to either of the bit lines or the source line when the selected word line is at the high logic level; and determining that the selected word line is shorted to at least one of the bit lines or the source line when the selected word line is at the low logic level.
According to an embodiment of the present invention, after the step of executing the second detection program, the detection method further includes: executing a third detection procedure, wherein the third detection procedure further comprises: applying a third positive voltage to the selected word line by using a second constant current, so that a plurality of memory cells on the selected word line are not conducted; floating all the bit lines; applying the ground voltage to the source line; determining whether the selected word line is at the high logic level or the low logic level; determining that the selected word line is not shorted to the source line when the selected word line is at the high logic level; and determining that the selected word line is shorted to the source line when the selected word line is at the low logic level.
According to an embodiment of the present invention, after the step of executing the third detection program, the detection method further includes: executing a fourth detection procedure, wherein the fourth detection procedure comprises: applying a fourth positive voltage to the selected word line to render a plurality of memory cells on the selected word line non-conductive; sequentially selecting one of the bit lines as a selected bit line, wherein the rest of the bit lines are a plurality of unselected bit lines; discharging the selected bit line to the ground voltage using a fourth constant current; floating the source line and the unselected bit line; determining whether the selected bit line is at the high logic level or the low logic level; when the selected bit line is at high logic level, judging the selected bit line is short-circuited to the selected word line; and determining that the selected bit line is not shorted to the selected word line when the selected bit line is at the low logic level.
The present invention further provides a memory device, comprising: the flash memory device comprises a flash memory array, a bias circuit, a sensing circuit and a controller. The flash memory array includes a plurality of word lines, a plurality of bit lines, a source line, and a P-well. The bias circuit generates a voltage and a current of the flash memory array. The sensing circuit is used for sensing logic levels of the word line, the bit line and the source line and leakage current of the P-type well. The controller selects one of the word lines and one of the bit lines and performs a detection method, wherein the detection method includes a first detection procedure, wherein the first detection procedure includes: applying a first positive voltage to the P-well of the flash memory array; applying a ground voltage to all of the word lines; floating the bit line and the source line; determining whether the leakage current flowing through the P-type well exceeds a leakage threshold value; and determining whether at least one of the word lines is shorted to at least one of the bit lines or the source line when the leakage current exceeds the leakage threshold.
According to an embodiment of the present invention, after the step of determining whether at least one of the word lines is shorted to at least one of the bit lines or the source line, the method further includes a second detecting process, wherein the second detecting process includes: sequentially selecting one of the word lines as a selected word line; charging the selected word line to a second positive voltage by a first constant current; applying the ground voltage to all of the bit lines and the source lines; determining whether the selected word line is at a high logic level or a low logic level; determining that the selected word line is not shorted to either of the bit lines or the source line when the selected word line is at the high logic level; and determining that the selected word line is shorted to at least one of the bit lines or the source line when the selected word line is at the low logic level.
According to an embodiment of the present invention, after the step of executing the second detection procedure, the detection method further includes a third detection procedure, wherein the third detection procedure further includes: applying a third positive voltage to the selected word line by using a second constant current, so that a plurality of memory cells on the selected word line are not conducted; floating all the bit lines; applying the ground voltage to the source line; determining whether the selected word line is at the high logic level or the low logic level; determining that the selected word line is not shorted to the source line when the selected word line is at the high logic level; and determining that the selected word line is shorted to the source line when the selected word line is at the low logic level.
According to an embodiment of the present invention, after the step of executing the third detection procedure, the detection method further includes a fourth detection procedure, wherein the fourth detection procedure includes: applying a fourth positive voltage to the selected word line to render a plurality of memory cells on the selected word line non-conductive; sequentially selecting one of the bit lines as a selected bit line, wherein the rest of the bit lines are a plurality of unselected bit lines; discharging the selected bit line to the ground voltage using a fourth constant current; floating the source line and the unselected bit line; determining whether the selected bit line is at the high logic level or the low logic level; when the selected bit line is at high logic level, judging the selected bit line is short-circuited to the selected word line; and determining that the selected bit line is not shorted to the selected word line when the selected bit line is at the low logic level.
By implementing the detection method provided by the invention, the system can know which flash memory array is damaged, so that the system can execute a series of operations to protect the data stored in the flash memory array.
Drawings
Fig. 1 is a block diagram of a flash memory device according to an embodiment of the invention.
Fig. 2 is a circuit diagram of a flash memory array according to an embodiment of the invention.
FIG. 3 is a cross-sectional view of a flash memory cell according to an embodiment of the invention.
Fig. 4 is a flowchart illustrating a detection method according to an embodiment of the invention.
Fig. 5 is a flowchart illustrating a first detection procedure according to an embodiment of the invention.
Fig. 6 is a circuit diagram illustrating a bias circuit according to an embodiment of the invention.
Fig. 7 is a flowchart illustrating a second detection procedure according to an embodiment of the invention.
FIG. 8 is a diagram illustrating a second testing procedure for testing a flash memory array according to an embodiment of the present invention.
Fig. 9 is a flowchart illustrating a third detection procedure according to an embodiment of the invention.
FIG. 10 is a diagram illustrating a flash memory array being tested by a third testing procedure according to an embodiment of the present invention.
Fig. 11A-11B are flowcharts illustrating a fourth detection procedure according to an embodiment of the invention.
FIG. 12 is a diagram illustrating a flash memory array being tested by a fourth testing procedure according to an embodiment of the present invention.
Reference numerals
100 flash memory device
200. 110, 810, 1010, 1210 flash memory array
120. 600, 820, 1020, 1220 bias circuit
130. 1230 sense Circuit
140 controller
BL <0>, BL <1>, …, BL < k >, …, BL < n >, BL bit line
WL <0>, WL <1>, …, WL < p >, …, WL < m >, WL word line
SL source line
201. 300 memory cell
310P-type trap
320 first N-type doped region
330 second N-type doped region
340 third N-type doped region
350 gate terminal
400 detection method
500 first test procedure
700 second test procedure
900 third test procedure
1100 fourth test procedure
610 current mirror
620 first current source
821 second current source
822. 1022 confinement N-type transistor
1021 third current source
1221 fourth Current Source
VP1 first positive voltage
VP2 second positive voltage
VP3 third positive voltage
VB bias voltage
VG gate voltage
N1 first node
P1 first P-type transistor
P2 second P-type transistor
S1 first output node
S2 second output node
S3 third output node
I1 first fixed Current
I2 second fixed Current
I3 third fixed Current
I4 fourth fixed Current
S41-S44, S501-S506, and S701-S708 steps
Step flows of S901-S908 and S1101-S1111
Detailed Description
The following description is an example of the present invention. The general principles of the present invention are intended to be illustrative, but not limiting, of the scope of the invention, which is defined by the claims.
It is noted that the following disclosure provides many different embodiments, or examples, for implementing different features of the invention. The following specific examples and arrangements of components are merely illustrative of the spirit of the invention and are not intended to limit the scope of the invention. Moreover, the following description may repeat reference numerals and/or letters in the various examples. However, this repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed below. Moreover, the description below of one feature connected to, coupled to, and/or formed on another feature may actually encompass a variety of different embodiments that may include the feature in direct contact, or that may include other additional features formed between the features, etc., such that the features are not in direct contact.
Fig. 1 is a block diagram of a flash memory device according to an embodiment of the invention. As shown in fig. 1, the flash memory device 100 includes a flash memory array 110, a bias circuit 120, a sensing circuit 130, and a controller 140. Flash memory array 110 includes a plurality of word lines, negative bit line, source line, and P-well, as described in more detail in the following paragraphs.
According to one embodiment of the present invention, flash array 110 is a NOR gate flash array. According to other embodiments of the present invention, the flash memory device 100 may have a plurality of flash memory arrays 110. Fig. 1 is merely illustrative of one flash memory array 110 and is not intended to be limiting in any way.
The bias circuit 120 is used to generate voltages and currents to be supplied to the flash memory array 110, and the sense circuit 130 is used to sense logic levels and currents of the word lines, bit lines, source lines, and P-wells.
Fig. 2 is a circuit diagram of a flash memory array according to an embodiment of the invention. As shown in fig. 2, flash array 200 corresponds to flash array 110 of fig. 1, and includes a plurality of bit lines BL <0>, BL <1>, …, BL < k >, …, BL < n >, a plurality of word lines WL <0>, WL <1>, …, WL < p >, …, WL < m >, and source lines SL, wherein flash array 200 includes m × n flash memory cells.
According to an embodiment of the invention, when the controller 140 of fig. 1 selects the memory cell 201 of fig. 2, the bias circuit 120 generates corresponding voltages to the word line WL <1>, the bit line BL <2>, and the source line SL, so that the sensing circuit 130 can read out the data stored in the memory cell 201 and transmit the read data to the controller 140.
FIG. 3 is a cross-sectional view of a flash memory cell according to an embodiment of the invention. According to an embodiment of the present invention, the cross-sectional view of flash memory array 110 is illustrated as flash memory cell 300. As shown in fig. 3, the flash cell 300 includes a P-well 310, a first N-doped region 320, a second N-doped region 330, a third N-doped region 340, and a gate terminal 350. The second N-type doped region 330 and the third N-type doped region 340 are coupled to a source line SL, the first N-type doped region 320 is coupled to a bit line BL, and the gate terminal 350 is coupled to a word line WL.
After a series of erase operations is performed on the flash memory array, the bit lines or source lines may be shorted to the word lines. Therefore, the present invention proposes a method of detecting the defect.
Fig. 4 is a flowchart illustrating a detection method according to an embodiment of the invention. As shown in the inspection method 400 of fig. 4, a first inspection process is first performed (step S41) to determine whether the flash memory array 110 has defects. When it is determined that the flash memory array 110 has at least one defect, a second testing procedure is performed (step S42) to determine which of the word lines the defect occurs in.
A third testing procedure is performed (step S43) to determine whether the source line is shorted to the damaged word line. Then, a fourth detection procedure is performed (step S44) to determine which bit line is shorted to the damaged word line. The first detection procedure, the second detection procedure, the third detection procedure and the fourth detection procedure will be described in detail in the following paragraphs. According to an embodiment of the invention, the detection method 400 may be terminated after step S41.
Fig. 5 is a flowchart illustrating a first detection procedure according to an embodiment of the invention. The following description of the first detection procedure 500 of fig. 5 will be combined with fig. 1-3 to facilitate the detailed description. As shown in fig. 5, the first testing procedure 500 corresponds to step S41 of the testing method 400 of fig. 4, wherein the bias circuit 120 provides a first positive voltage to the P-well 310 of the flash array 110 (shown in fig. 3) (step S501). The bias circuit 120 provides a ground voltage to all word lines WL <0>, WL <1>, …, WL < p >, …, WL < m > of the flash array 110 (step S502), and floats (floating) all bit lines BL <0>, BL <1>, …, BL < k >, …, BL < n >, and source lines SL (step S503).
Next, the controller 140 determines whether the leakage current flowing through the P-well 310 exceeds a leakage threshold (step S504). When the leakage current exceeds the leakage threshold, the controller 140 determines that at least one of the word lines WL <0>, WL <1>, …, WL < p >, …, and WL < m > of the flash memory array 110 is shorted to at least one of the bit lines BL <0>, BL <1>, …, BL < k >, …, and BL < n >, or shorted to the source line SL (step S505). Then, after the first testing procedure 500 is terminated, step S42 is executed to further determine which word line is shorted to at least one of the bit lines or to the source line.
Returning to FIG. 3, in accordance with one embodiment of the present invention, the P-well 310 is biased to a first positive voltage, all bit lines BL <0>, BL <1>, …, BL < k >, …, BL < n >, and source line SL, as illustrated by bit line BL, in FIG. 3 are floating, and all word lines WL <0>, WL <1>, …, WL < P >, …, WL < m >, as illustrated by word line WL, in FIG. 3 are biased to ground. When the controller 140 determines that the leakage current flowing through the P-well 310 exceeds the leakage threshold, the leakage current flowing through the P-well 310 is generated, which is represented by the short circuit between the bit line BL or the source line SL in fig. 3 and the word line WL in fig. 3.
After the controller 140 determines that at least one of the word lines is shorted to at least one of the bit lines and the source lines, the process returns to step S504, and when the controller 140 determines that the leakage current does not exceed the leakage threshold, the flash memory array 110 functions normally, and the detection method is terminated (step S506). After the first test procedure 500, it is determined whether at least one of the word lines of the flash memory array 110 is shorted to at least one of the bit lines or the source line.
Fig. 6 is a circuit diagram illustrating a bias circuit according to an embodiment of the invention. As shown in fig. 6, a bias circuit 600 corresponding to the bias circuit 120 of fig. 1 includes a current mirror 610 and a first current source 620. The current mirror 610 is powered by a first positive voltage VP1 and is coupled to a first node N1 and a first output node S1, wherein the current mirror 610 includes a first P-type transistor P1 and a second P-type transistor P2 coupled in a diode configuration. The first node N1 is coupled to the P-well 310 of fig. 3.
The first current source 620 generates a first fixed current I1, wherein the first fixed current I1 is the leakage threshold of step S504 in FIG. 5. According to an embodiment of the present invention, when the leakage current flowing through the P-well 310 of FIG. 3 exceeds the first constant current I1, the first output node S1 is at a high logic level.
According to another embodiment of the present invention, the first output node S1 is at a low logic level when the leakage current flowing through the P-well 310 of FIG. 3 does not exceed the first constant current I1. Therefore, the controller 140 of fig. 1 can determine whether the leakage current exceeds the leakage threshold according to the logic level of the first output node S1.
Fig. 7 is a flowchart illustrating a second detection procedure according to an embodiment of the invention. The following description of the second detection procedure 700 of fig. 7 is combined with fig. 1-3 to facilitate detailed description. As shown in fig. 7, the second detection routine 700 corresponds to step S42 of the detection method 400 of fig. 4. The controller 140 selects at least one of the word lines WL <0>, WL <1>, …, WL < p >, …, WL < m > as the selected word line (step S701).
According to an embodiment of the present invention, the controller 140 may sequentially select one of the word lines WL <0>, WL <1>, …, WL < p >, …, WL < m > as the selected word line. According to other embodiments of the present invention, the controller 140 may select one of the word lines WL <0>, WL <1>, …, WL < p >, …, WL < m > as the selected word line in any particular order.
When one of the word lines WL <0>, WL <1>, …, WL < p >, …, WL < m > is selected, the bias circuit 120 charges the selected word line to a second positive voltage with a second constant current (step S702). The bias circuit 120 also applies the ground voltage to all the bit lines BL <0>, BL <1>, …, BL < k >, …, BL < n >, and the source line SL (step S703). The controller 140 determines whether the selected word line is at a high logic level or a low logic level (step S704).
When determining that the selected word line is at the high logic level, the controller 140 determines that the selected word line is not shorted to any of the bit lines BL <0>, BL <1>, …, BL < k >, …, BL < n >, or the source line SL (step S705). When determining that the selected word line is at the low logic level, the controller 140 determines that the selected word line is shorted to at least one of the bit lines BL <0>, BL <1>, …, BL < k >, …, BL < n >, or the source line SL (step S706).
After step S705 and step S706, the controller 140 further determines whether the selected word line is the last word line of the word lines WL <0>, WL <1>, …, WL < p >, …, and WL < m > (step S707). When the selected word line is not the last of the word lines WL <0>, WL <1>, …, WL < p >, …, WL < m >, the controller 140 selects the next of the word lines WL <0>, WL <1>, …, WL < p >, …, WL < m > as the selected word line (step S708), and returns to step S702. When the selected word line is the last of the word lines WL <0>, WL <1>, …, WL < p >, …, WL < m >, the controller 140 ends the second detection procedure 700 and starts to execute step S43.
FIG. 8 is a diagram illustrating a second testing procedure for testing a flash memory array according to an embodiment of the present invention. As shown in fig. 8, flash array 810 is the same as flash array 200 of fig. 2 corresponding to flash array 110 of fig. 1, and bias circuit 820 corresponds to bias circuit 120 of fig. 1. According to one embodiment of the present invention, the bias circuit 820 can bias the flash memory array 810 through an X decoder, which is not shown in FIG. 8.
The bias circuit 820 includes a second current source 821 and a limiting N-type transistor 822. The second current source 822 generates a second constant current I2 from the second positive voltage VP2, wherein the second constant current I2 is used to charge the selected word line to the second positive voltage VP 2. As shown in FIG. 8, the selected word line is exemplified by word line WL < p >. The N-type transistor 822 is restricted such that the bias voltage VB of the selected word line is not limited by the gate voltage VG. According to an embodiment of the present invention, when the second detection procedure 700 of fig. 7 is performed, the gate voltage VG exceeds the second positive voltage VP2, such that the bias voltage VB is not limited by the gate voltage VG.
The bias circuit 820 also applies a ground voltage to the bit lines BL <0>, BL <1>, …, BL < k >, …, BL < n >, and the source line SL. According to an embodiment of the present invention, when the selected word line (for example, word line WL < p > in FIG. 8) is shorted to at least one of the bit lines BL <0>, BL <1>, …, BL < k >, …, BL < n >, the second output node S2 is at a low logic level.
According to other embodiments of the present invention, when the selected word line (for example, word line WL < p > in FIG. 8) is not shorted to at least one of the bit lines BL <0>, BL <1>, …, BL < k >, …, BL < n >, or the source line SL, the second output node S2 is at a high logic level. Therefore, the controller 140 determines whether the selected word line is shorted to at least one of the bit lines BL <0>, BL <1>, …, BL < k >, …, BL < n >, or the source line SL according to the logic level of the second output node S2.
Fig. 9 is a flowchart illustrating a third detection procedure according to an embodiment of the invention. The following description of the third detection procedure 900 of fig. 9 will be combined with fig. 1-3 to facilitate detailed description. As shown in fig. 9, the third sensing procedure 900 corresponds to step S43 of the sensing method 400 of fig. 4, wherein the bias circuit 120 applies a third positive voltage to the selected word line by using a second constant current (step S901), and does not turn on the memory cell coupled to the selected word line.
According to an embodiment of the present invention, once the memory cells on the selected word line are turned on, the source lines SL and the bit lines shorted to the selected word line are shorted with each other, resulting in an erroneous detection result. According to an embodiment of the present invention, the word line selected in step S901 is one of the word lines determined to be damaged in the second detection procedure 700. Therefore, the second detection procedure 700 is used to identify which word line is damaged, so that the damaged word line can be directly selected in the third detection procedure 900.
Then, the bias circuit 120 floats all the bit lines BL <0>, BL <1>, …, BL < k >, …, BL < n > (step S902), and couples the ground voltage to the source line SL (step S903). The controller 140 determines whether the selected word line is at a high logic level or a low logic level (step S904).
When the selected word line is at the high logic level, the controller 1440 determines that the selected word line is not shorted to the source line SL (step S905). When the selected word line is at the low logic level, the controller 140 determines that the selected word line is shorted to the source line SL (step S906).
After step S905 and step S906, the controller 140 determines whether the selected word line is the last word line determined to be damaged in the second detection procedure 700 (step S907). When the selected word line is the last of the damaged word lines, the controller 140 ends the third detection procedure 900. When the selected word line is not the last of the damaged word lines, the controller 140 selects the next of the damaged word lines as the selected word line (step S908), and returns to step S901.
According to an embodiment of the present invention, when the selected word line is shorted to the source lines SL, the data stored in the selected word line of the flash memory array 110 is lost and cannot be recovered by using ECC.
FIG. 10 is a diagram illustrating a flash memory array being tested by a third testing procedure according to an embodiment of the present invention. As shown in fig. 10, the flash memory array 1010 is the same as the flash memory array 110 of fig. 1 and the flash memory 200 of fig. 2, and the bias circuit 1020 corresponds to the bias circuit 120 of fig. 1. According to an embodiment of the present invention, the bias circuit 1020 may bias the flash memory array 1010 through an X decoder, which is not shown in FIG. 10.
The bias circuit 1020 includes a third current source 1021 and a limiting N-type transistor 1022. The third current source 1022 generates a third constant current I3 from the third positive voltage VP3, wherein the third current source 1022 charges the selected word line with the third constant current I3. As shown in FIG. 10, the selected word line is exemplified by word line WL < p >. The N-type transistor 1022 is limited by the gate voltage VG to limit the bias voltage VB of the selected word line.
According to an embodiment of the present invention, when the third detection procedure 900 of fig. 9 is performed, the gate voltage VG is equal to the sum of the erase threshold voltage of the memory cells on the selected word line (i.e., the memory cells on the word line WL < p >) and the threshold voltage of the limiting N-type transistor 1022, so that the memory cells on the selected word line remain non-conductive.
The bias circuit 1020 applies a ground voltage to the source line SL and floats all the bit lines BL <0>, BL <1>, …, BL < k >, …, BL < n >. According to an embodiment of the present invention, when the selected word line (for example, word line WL < p > in fig. 10) is shorted to the source line SL, the third output node S3 is at a low logic level.
According to another embodiment of the present invention, when the selected word line is not shorted to the ground voltage, the leakage current of the selected word line does not exceed the third constant current I3, such that the third output node S3 is at a high logic level. Therefore, the controller 140 may determine whether the selected word line is shorted to the source line SL according to the logic level of the third output node S3.
Fig. 11A-11B are flowcharts illustrating a fourth detection procedure according to an embodiment of the invention. The following description of the fourth detection procedure 1100 of fig. 11A and 11B will be described in detail with reference to fig. 1 to 3. As shown in fig. 11A and 11B, the fourth sensing procedure 1100 corresponds to step S44 of the sensing method 400 of fig. 4, wherein the bias circuit 120 applies a fourth positive voltage to the selected word line (step S1101), and none of the memory cells on the selected word line are turned on. According to an embodiment of the present invention, the selected word line is one of the word lines determined to be damaged in the second detection procedure 700.
The controller 140 selects one of the bit lines as a selected bit line (step S1102), wherein the remaining bit lines are unselected bit lines. According to an embodiment of the present invention, the controller 140 sequentially selects one of the bit lines as the selected bit line. According to another embodiment of the present invention, the controller 140 selects one of the bit lines as the selected bit line in any particular order.
The bias circuit 120 discharges the selected bit line to the ground voltage by the fourth fixed current (step S1103), and floats the source line SL and the unselected bit lines (step S1104). The controller 140 determines whether the selected bit line is at a high logic level or a low logic level (step S1105).
When the selected bit line is at the high logic level, the controller 140 determines that the selected bit line is shorted to the selected word line (step S1106). When the selected bit line is at the low logic level, the controller 140 determines that the selected bit line is not shorted to the selected word line (step S1107).
The controller 140 further determines whether the selected bit line is the last bit line of the bit lines BL <0>, BL <1>, …, BL < k >, …, BL < n > (step S1108). When the selected bit line is not the last of the bit lines BL <0>, BL <1>, …, BL < k >, …, BL < n >, the controller 140 selects the next one of the bit lines BL <0>, BL <1>, …, BL < k >, …, BL < n > as the selected bit line (step S1109).
When the selected bit line is the last one of the next bit lines BL <0>, BL <1>, …, BL < k >, … and BL < n >, the controller 140 determines whether the selected word line is the last one of the word lines determined to be damaged by the second detection program 700 (step S1110). When the selected word line is not the last of the damaged word lines, the controller 140 selects the next of the damaged word lines (step S1111) and returns to step S1101. When the selected word line is the last of the damaged word lines, the fourth testing procedure 1100 is terminated, and the testing method 400 is also terminated.
FIG. 12 is a diagram illustrating a flash memory array being tested by a fourth testing procedure according to an embodiment of the present invention. As shown in fig. 12, the flash array 1210 is the same as the flash array 110 of fig. 1 and the flash array 200 of fig. 2, and the bias circuit 1220 corresponds to the bias circuit 120 of fig. 1.
As shown in fig. 12, the bias circuit 1220 includes a fourth current source 1221. The fourth current source 1221 discharges the selected bit line (in fig. 12, the bit line BL < k > is taken as an example) to the ground voltage by the fourth fixed current I4. Any memory cell on the selected word line may not be turned on when the selected word line is biased. According to an embodiment of the invention, the bias circuit 1220 may bias the selected word line shown in fig. 10, and the description thereof is not repeated.
According to an embodiment of the invention, the source lines SL may be floating. According to another embodiment of the present invention, since all the memory cells on the selected word line are non-conductive, the source line SL can be grounded without affecting the selected bit line.
When the selected bit line is discharged to the ground voltage, the sensing circuit 1230 determines whether the selected bit line is at a high logic level or a low logic level. When the selected bit line is at a high logic level, it represents that the selected bit line is shorted to the selected word line. When the selected bit line is at a low logic level, it means that the selected bit line is not shorted to the selected word line.
According to an embodiment of the present invention, when the selected bit line is shorted to the selected word line, the data stored on the selected bit line of the memory array is lost, but the data stored on the selected word line can be recovered by using ECC.
According to an embodiment of the present invention, when a selected bit line is shorted to a selected word line, data stored in memory cells corresponding to the selected word line and the selected bit line can be read by applying a positive voltage to the selected word line and floating the selected bit line. After reading the data stored in the selected word line, all bit lines are floated to discharge to ground.
After the detection method provided by the invention is executed, the system can know which flash memory array is damaged, so that the system can execute a series of operations to protect the data stored in the flash memory array.
What has been described above is a general characterization of the embodiments. Those skilled in the art should readily appreciate that they can readily use the present disclosure as a basis for designing or modifying other structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that the same may be used without departing from the spirit and scope of the present invention and that various changes, substitutions and alterations can be made therein without departing from the spirit and scope of the present invention. The illustrative method represents exemplary steps only, and the steps are not necessarily performed in the order represented. Additional, alternative, changed order and/or elimination steps may be added, substituted, changed order and/or eliminated as appropriate and consistent with the spirit and scope of the disclosed embodiments.
Claims (14)
1. A method for testing a flash memory array, the flash memory array including a plurality of word lines, a plurality of bit lines, and a source line, comprising:
executing a first detection procedure, wherein the first detection procedure comprises:
applying a first positive voltage to a P-well of the flash memory array;
applying a ground voltage to all of the word lines;
floating the bit line and the source line;
judging whether a leakage current flowing through the P-type trap exceeds a leakage threshold value; and
when the leakage current exceeds the leakage threshold value, at least one of the word lines is determined to be shorted to at least one of the bit lines or the source line.
2. The method of claim 1, further comprising, after the step of determining whether at least one of the word lines is shorted to at least one of the bit lines or the source line:
executing a second detection procedure, wherein the second detection procedure comprises:
sequentially selecting one of the word lines as a selected word line;
charging the selected word line to a second positive voltage with a first fixed current;
applying the ground voltage to all of the bit lines and the source line;
determining whether the selected word line is at a high logic level or a low logic level;
determining that the selected word line is not shorted to either of the bit lines or the source line when the selected word line is at the high logic level; and
when the selected word line is at the low logic level, determining that the selected word line is shorted to at least one of the bit lines or the source line.
3. The inspection method of claim 2, wherein after the step of performing the second inspection procedure, the inspection method further comprises:
executing a third detection procedure, wherein the third detection procedure further comprises:
applying a third positive voltage to the selected word line with a second fixed current such that a plurality of memory cells on the selected word line are non-conductive;
floating all the bit lines;
applying the ground voltage to the source line;
determining whether the selected word line is at the high logic level or the low logic level;
when the selected word line is at the high logic level, determining that the selected word line is not shorted to the source line; and
when the selected word line is at the low logic level, determining that the selected word line is shorted to the source line.
4. The method of claim 3, wherein when the selected word line is shorted to the source line, data stored on the selected word line of the flash memory array is lost and cannot be recovered using ECC.
5. The inspection method of claim 3, wherein after the step of performing the third inspection procedure, the inspection method further comprises:
executing a fourth detection procedure, wherein the fourth detection procedure comprises:
applying a fourth positive voltage to the selected word line such that a plurality of memory cells on the selected word line are non-conductive;
sequentially selecting one of the bit lines as a selected bit line, wherein the remaining bit lines are a plurality of unselected bit lines;
discharging the selected bit line to the ground voltage with a fourth fixed current;
floating the source line and the unselected bit line;
determining whether the selected bit line is at the high logic level or the low logic level;
when the selected bit line is at a high logic level, judging that the selected bit line is short-circuited to the selected word line; and
when the selected bit line is at the low logic level, it is determined that the selected bit line is not shorted to the selected word line.
6. The method of claim 5, wherein when the selected bit line is shorted to the selected word line, data stored on the selected bit line of the flash memory array is lost and the data stored on the selected word line can be recovered using ECC.
7. The method of claim 5, wherein when the selected bit line is shorted to the selected word line, data stored in a memory cell corresponding to the selected word line and the selected bit line can be read by applying a positive voltage to the selected word line and floating the selected bit line, wherein after reading the data stored on the selected word line, all of the bit lines are floating and discharged to the ground voltage.
8. A memory device, comprising:
a flash memory array including a plurality of word lines, a plurality of bit lines, a source line and a P-well;
a bias circuit for generating a voltage and a current for the flash memory array;
a sensing circuit for sensing logic levels of the word line, the bit line and the source line and a leakage current of the P-well; and
a controller selecting one of the word lines and one of the bit lines and performing a sensing method, wherein the sensing method includes a first sensing procedure, wherein the first sensing procedure includes:
applying a first positive voltage to the P-well of the flash memory array;
applying a ground voltage to all of the word lines;
floating the bit line and the source line;
judging whether the leakage current flowing through the P-type trap exceeds a leakage threshold value; and
when the leakage current exceeds the leakage threshold, determining whether at least one of the word lines is shorted to at least one of the bit lines or the source line.
9. The memory device of claim 8, wherein after the step of determining whether at least one of the word lines is shorted to at least one of the bit lines or the source line, the method further comprises a second sensing process, wherein the second sensing process comprises:
sequentially selecting one of the word lines as a selected word line;
charging the selected word line to a second positive voltage with a first fixed current;
applying the ground voltage to all of the bit lines and the source line;
determining whether the selected word line is at a high logic level or a low logic level;
determining that the selected word line is not shorted to either of the bit lines or the source line when the selected word line is at the high logic level; and
when the selected word line is at the low logic level, determining that the selected word line is shorted to at least one of the bit lines or the source line.
10. The memory device of claim 9, wherein after the step of performing the second detection procedure, the detection method further comprises a third detection procedure, wherein the third detection procedure further comprises:
applying a third positive voltage to the selected word line with a second fixed current such that a plurality of memory cells on the selected word line are non-conductive;
floating all the bit lines;
applying the ground voltage to the source line;
determining whether the selected word line is at the high logic level or the low logic level;
when the selected word line is at the high logic level, determining that the selected word line is not shorted to the source line; and
when the selected word line is at the low logic level, determining that the selected word line is shorted to the source line.
11. The memory device of claim 10, wherein when the selected word line is shorted to the source line, data stored on the selected word line of the flash memory array is lost and cannot be recovered using ECC.
12. The memory device according to claim 10, wherein after the step of executing the third detection procedure, the detection method further comprises a fourth detection procedure, wherein the fourth detection procedure comprises:
applying a fourth positive voltage to the selected word line such that a plurality of memory cells on the selected word line are non-conductive;
sequentially selecting one of the bit lines as a selected bit line, wherein the remaining bit lines are a plurality of unselected bit lines;
discharging the selected bit line to the ground voltage with a fourth fixed current;
floating the source line and the unselected bit line;
determining whether the selected bit line is at the high logic level or the low logic level;
when the selected bit line is at a high logic level, judging that the selected bit line is short-circuited to the selected word line; and
when the selected bit line is at the low logic level, it is determined that the selected bit line is not shorted to the selected word line.
13. The memory device of claim 12, wherein when the selected bit line is shorted to the selected word line, data stored on the selected bit line of the flash memory array will be lost, and data stored on the selected word line can be recovered using ECC.
14. The memory device of claim 12, wherein when the selected bit line is shorted to the selected word line, data stored in a memory cell corresponding to the selected word line and the selected bit line can be read by applying a positive voltage to the selected word line and floating the selected bit line, wherein after reading the data stored on the selected word line, all of the bit lines are floating and discharged to the ground voltage.
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