CN110619921A - Apparatus for testing memory - Google Patents

Abstract

An apparatus for testing a memory includes a first memory circuit and a second memory circuit. The second memory circuit is configured to store a first mapping of the first memory circuit. The device comprises a comparison circuit and a calculation circuit. The comparison circuit is configured to compare the first pair stored in the second memory circuit with a plurality of pairs of the first memory circuit operating under different conditions to generate a plurality of first comparison results. The calculation circuit is configured to output a maximum hamming distance according to the first comparison result, wherein the maximum hamming distance is between the first corresponding and two of the plurality of corresponding of the first memory circuit.

Description

Apparatus for testing memory

Technical Field

The present disclosure relates to a device for testing memory, and more particularly, to a Hamming Distance (Hamming Distance) analyzer and an analyzing method thereof.

Background

Each Integrated Circuit (IC) is unique due to many process factors, even though the ICs are fabricated with the same process and the same material. Each integrated circuit has the opportunity to operate in different operating environments depending on its actual application. Therefore, Robustness (Robustness) of one of the integrated circuits under different operating environments is a key issue in the field of semiconductor technology.

Disclosure of Invention

In one aspect of the disclosure, an apparatus for testing a memory is disclosed, and the memory includes a first memory circuit and a second memory circuit. The second memory circuit is configured to store a first mapping of the first memory circuit. The device comprises a comparison circuit and a calculation circuit. The comparison circuit is configured to compare the first pair stored in the second memory circuit with a plurality of pairs of the first memory circuit operating under different conditions to generate a plurality of first comparison results. The calculation circuit is configured to output a maximum hamming distance according to the first comparison result, wherein the maximum hamming distance is between the first corresponding and two of the plurality of corresponding of the first memory circuit.

Drawings

The aspects of the present disclosure are best understood from the following detailed description when read with the accompanying drawings. It is noted that, as is standard practice in the industry, many features are not drawn to scale. In fact, the dimensions of many of the features may be arbitrarily scaled for clarity of discussion.

FIG. 1 is a schematic diagram illustrating a device and a DUT according to various embodiments of the present disclosure;

FIG. 2 is a flow diagram illustrating a method of operation of the device of FIG. 1 with a device under test, according to various embodiments of the present disclosure;

FIG. 3 is a schematic diagram illustrating a comparison procedure for the device of FIG. 1 and a device under test according to various embodiments of the present disclosure;

FIG. 4 is a schematic diagram illustrating an apparatus and a memory according to various embodiments of the present disclosure;

FIG. 5 is a flow chart illustrating a method of the device of FIG. 4 performing an operation on a memory according to various embodiments of the present disclosure.

Detailed Description

The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the description that a first feature is formed over or on a second feature encompasses embodiments in which the first and second features are in direct contact, as well as embodiments in which other features are formed between the first and second features such that the first and second features are not in direct contact. The dimensions of many of the features may be drawn on different scales to simplify and clarify the same. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

The terms used in the specification generally have their meanings as they are in the art, and each term is used for a specific content. The embodiments used in this specification (including any embodiments described herein) are intended to be illustrative only and are not intended to limit the scope or meaning of the disclosure or any expressed terms. As such, the present disclosure is not intended to be limited to the various embodiments described herein.

Although the terms first and second may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be a second element, and similarly, a second element could be a first element, without departing from the scope of the embodiments. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.

The terms "comprising," including, "" having, "and the like as used in this specification are open-ended and mean" including, but not limited to.

Please refer to fig. 1. Fig. 1 is a schematic diagram of a device 100 and a device under test 105 according to various embodiments of the present disclosure.

In some embodiments, device 100 is a test device. The device 100 is configured to test the Robustness (Robustness) of the device under test 105. In some embodiments, the apparatus 100 is applied to or built as an Intra-hamming Analyzer (Intra-hamming Analyzer). The device 100 is configured to generate a maximum Hamming Distance (HD) for the device under test 105. The maximum hamming distance HD represents the robustness of the device under test 105. In some embodiments, the hamming distance HD indicates the number of different bits between two bins.

In some embodiments, the device under test 105 is a memory array under test. In some other embodiments, the device under test 105 includes a memory array under test. The memory array to be tested is, for example, a Static Random Access Memory (SRAM), a flash memory or the like, but is not limited thereto. It is within the scope of the present disclosure to implement various memory arrays or cells in the device under test 105 or various memory arrays or cells implemented in the device under test 105.

In some embodiments, the device under test 105 operates under different operating conditions depending on its actual application. The operating conditions correspond to different operating environments. For purposes of illustration, different operating conditions correspond to different supply voltages, different operating temperatures, different operating frequencies, or combinations of the foregoing.

In some embodiments, the correspondence of the device under test 105 is different when the device under test 105 operates under different operating conditions. In some embodiments, each correspondence is content in the device under test 105 under a particular operating environment. For illustrative purposes, the handling of the device under test 105 operating at 10 ℃ is different from the handling of the device under test 105 operating at 50 ℃.

As shown in FIG. 1, in some embodiments, the device 100 includes a memory array 120, a comparison circuit 140, and a calculation circuit 160. In some embodiments, the device 100 also includes a recorder 180. The memory array 120 is coupled to the dut 105. The comparison circuit 140 is coupled to the memory array 120 and the dut 105. The recorder 180 is coupled to the comparison circuit 140. The calculation circuit 160 is coupled to a recorder 180.

The above discussion merely describes example connection manners that may be used in accordance with various embodiments. It is to be understood that the various embodiments are not limited to the specific connections described above or shown in fig. 1.

In addition, in this specification, the term "coupled" may also be referred to as "electrically coupled", and the term "connected" may also be referred to as "electrically connected". "coupled" and "connected" may also be used to indicate that two or more elements co-operate or interact with each other.

As shown in FIG. 1, the memory array 120 is configured to generate at least one correspondence for the device under test 105 and to store the at least one correspondence. In some embodiments, the at least one reply is copied or rewritten from the device under test 105 to the memory array 120. In some embodiments, memory array 120 is a replica of device under test 105, whereby memory array 120 generates at least one counterpart that is identical to the at least one counterpart of device under test 105.

In some embodiments, the storage capacity of the memory array 120 corresponds to at least one corresponding number of bits of the dut 105. For example, if at least one of the dut 105 should have n bits, the storage capacity of the memory array 120 has at least n bits.

As shown in FIG. 1, the compare circuit 140 receives the responses from the memory array 120. The comparison circuit 140 also receives responses from the device under test 105 obtained under different operating conditions. The comparison circuit 140 is configured to sequentially compare the pair from the memory array 120 with the plurality of pairs from the device under test 105 to generate corresponding comparison results.

As shown in FIG. 1, in some embodiments, the comparison circuit 140 includes at least one exclusive OR gate (exclusive OR gate) 142. The XOR gate 142 has a first input terminal, a second input terminal, and an output terminal. The first input is coupled to the memory array 120 for receiving the response from the memory array 120. The second input is coupled to the device under test 105 to receive the responses from the device under test 105 under different operating conditions. The output of exclusive or gate 142 is coupled to recorder 180.

The XOR gate 142 is configured to sequentially perform a corresponding XOR operation from the memory array 120 and a corresponding counter from the device under test 105 to generate corresponding comparison results. These comparison results are output to the recorder 180.

The configuration of the comparison circuit 140 is for illustration purposes only. Various configurations of the comparison circuit 140 are within the scope of the present disclosure. For example, in some other embodiments, the comparison circuit 140 includes more than one exclusive-or gate, while in other embodiments, the comparison circuit 140 includes a number of exclusive-or gates corresponding to a corresponding same number from the device under test 105. In some other embodiments, the comparison circuit 140 is implemented by other logic elements.

As shown in FIG. 1, the recorder 180 is configured to temporarily store the comparison result generated by the comparison circuit 140. Then, based on the comparison result, the logger 180 generates a final comparison result FC. In some embodiments, the final comparison result FC indicates a comparison result generated by comparing the transactions from the memory array 120 with the final transactions from the device under test 105.

The number of recorders 180 is for illustrative purposes only. Various numbers of recorders 180 are within the scope of the present disclosure. In some other embodiments, the apparatus 100 includes more than one recorder. For example, in some other embodiments, the apparatus 100 includes two recorders. The first of the two registers is coupled to the comparison circuit 140 to temporarily store the comparison of the two corresponding bits from the comparison circuit 140. The second of the two recorders is coupled to the first recorder and is configured to generate a final comparison result FC based on a plurality of comparisons of different two corresponding bits from the first recorder.

As shown in fig. 1, the calculation circuit 160 is configured to receive the final comparison result FC from the recorder 180. The calculation circuit 160 is further configured to output the maximum hamming distance HD according to the final comparison result FC. The maximum hamming distance HD represents the maximum difference between the two correspondences from the device under test 105.

As shown in fig. 1, in some embodiments, the calculation circuit 160 includes a counter 162 and a maximum hamming distance generation circuit 164. The counter 162 is coupled to the recorder 180. The maximum hamming distance generating circuit 164 is coupled to the counter 162.

The counter 162 is configured to receive the final comparison result FC from the logger 180 as described above. Based on the final comparison result FC, the counter 162 counts a value indicating the number of bits of the final comparison result FC having the same logic value. In some embodiments, the same logical value is "1". In other words, if 4 bits of the final comparison result FC have a logic value of "1", the counter 162 outputs data indicating 4 to the maximum hamming distance generating circuit 164. In some embodiments, the counter 162 is implemented as a group counter composed of a plurality of adders (not shown). In other embodiments, counter 162 is implemented with other logic gates.

Then, the maximum hamming distance generating circuit 164 generates the maximum hamming distance HD according to the above values and the total number of bits of the final comparison result FC. The maximum hamming distance HD represents the maximum difference between the two correspondences from the device under test 105. In some embodiments, the maximum hamming distance generating circuit 164 is implemented by or includes a subtractor (not shown), but not limited thereto. In other embodiments, the maximum hamming distance generating circuit 164 is implemented with other logic gates.

The configuration of the computational circuitry 160 is for illustration purposes only. Various configurations of the computing circuit 160 are within the scope of the present disclosure.

Again, the configuration of the device 100 in FIG. 1 is for illustration purposes only. Various configurations of the device 100 are within the scope of the present disclosure.

Please refer to fig. 2 and fig. 3. FIG. 2 is a flow chart illustrating a method 200 of operating the device 100 of FIG. 1 on a device under test 105 according to various embodiments of the present disclosure. FIG. 3 is a schematic diagram illustrating a comparison procedure for the device 100 and the device under test 105 of FIG. 1 according to various embodiments of the present disclosure.

Operation between the device 100 of fig. 1 and the device under test 105 is described by the method 200 illustrated in fig. 2 below. For a better understanding of the present disclosure, the method 200 is described with reference to fig. 1 and 3.

In operation 202, a correspondence R1 for the device under test 105 may be obtained when the device under test 105 is operating under the first operating condition. In some embodiments, the first operating condition is an initial operating condition of the device under test 105, but not limited thereto. Thus, the correspondence R1 is the content of the device under test 105 under the initial operating conditions. As shown in fig. 3, the corresponding R1 is 01010101. In other words, when the dut 105 is operating under the initial condition, the content of the dut 105 is 01010101. Furthermore, when the device under test 105 is operating under the first operating condition, the start reference value C0 in the recorder 180 is reset to 0000000.

The number of bits corresponding to R1 and other responses of the dut 105 is for illustration only. Various numbers of bits for the response R1 and other responses of the dut 105 are within the scope of the present disclosure. For example, in other embodiments, the or each counterpart R1 of the dut 105 has fewer than 8 bits or more than 8 bits.

In operation 204, the pair R1 is rewritten into the memory array 120. In some embodiments, reply R1 is copied or duplicated from device under test 105 and retained in memory array 120. In other words, for illustrative purposes, in the following operation, the counterpart R1 of 01010101 is stored in memory array 120 and is unchangeable. In various embodiments, memory array 120 is a duplicate of device under test 105, and thus, memory array 120 generates at least one correspondence that is identical to the correspondence from device under test 105.

In operation 206, the operating conditions of the device under test 105 are changed. For example, the operating condition of the device under test 105 is changed from the first operating condition to the second operating condition. In some embodiments, the second operating condition is different from the first operating condition.

In operation 208, a new correspondence for the device under test 105 is obtained. As described above, when the operating conditions of the device under test 105 change, the contents of the device under test 105 change accordingly. In some embodiments, the newly coped R2 is what is considered to be a change in the device under test 105. For illustrative purposes, the counterpart R2 of the dut 105 is 01000101.

In operation 210, the comparison circuit 140 compares the corresponding R1 and the corresponding R2 of the device under test 105 to generate a comparison result C1. In some embodiments, the XOR gate 142 performs an XOR operation on each bit of R1 and on the corresponding bit of R2 to adjust the initial reference value C0 such that the initial reference value C0 is adjusted to the comparison result C1.

As described with reference to FIG. 3, the XOR gate 142 performs an XOR operation on the first bit corresponding to R1 and the first bit corresponding to R2. In some embodiments, the first bit is considered to correspond to the rightmost bit of the eight bits in R1, such as shown in fig. 3, and the second bit is considered to correspond to the bit adjacent to the rightmost bit of the eight bits in R1, and so on. As illustrated in FIG. 3, the first bit corresponding to R1 and the first bit corresponding to R2 have the same logic value "1", so the result of the XOR operation on the two bits is a logic value "0". Therefore, the first bit of the comparison result C1 remains to have a logical value of "0", which is the same as the first bit of the starting reference value C0.

Then, the XOR gate 142 performs an XOR operation on the second bit corresponding to R1 and the second bit corresponding to R2. Since the second bit corresponding to R1 and the second bit corresponding to R2 have the same logic value "0", the result of the exclusive-OR operation on the two bits is logic value "0". Therefore, the second bit of the comparison result C1 remains to have a logical value of "0", which is the same as the second bit of the starting reference value C0.

Accordingly, the third bit of the comparison result C1, the fourth bit of the comparison result C1, the sixth bit of the comparison result C1, the seventh bit of the comparison result C1, and the eighth bit of the comparison result C1 remain to have a logic value of "0".

For the sake of illustration, the fifth bit corresponding to R1 has a logic value "1", while the fifth bit corresponding to R2 has a logic value "0", so the result of the exclusive or operation on the two bits is a logic value "1". Therefore, the fifth bit of the comparison result C1 traverses from logic value "0" to logic value "1".

Therefore, the initial reference value C0 is adjusted to the comparison result C1. The comparison result C1 was 00010000. The comparison result C1 is temporarily stored in the recorder 180.

In operation 212, it is determined whether there are other operating conditions for testing the device under test 105. In some embodiments, the verification step is performed by a controller (not shown) or a processing circuit (not shown), but not limited thereto. If there are other operating conditions to test (e.g., the third operating condition), operation 206 is resumed. In other words, the operating condition of the device under test 105 is changed from the second operating condition to the third operating condition. In some embodiments, the third operating condition is different from the second operating condition and is different from the first operating condition.

When the device under test 105 is operating under the third operating condition, a new correspondence for the device under test 105 may be obtained. As shown in fig. 3, the new mapping for the dut 105 is 01111001. The XOR gate 142 then performs an XOR operation on the corresponding R1 and the corresponding R3 stored in the memory array 120.

In some embodiments, if the Xth bit of a comparison result has a predetermined logic value (e.g., logic value "1"), the Xth bit of the following comparison result is maintained. For illustrative purposes, the fifth bit of the comparison result C1 has a logic value of "1". Regardless of the result of the exclusive-OR operation on the fifth bit corresponding to R1 and the fifth bit corresponding to R3, the fifth bit of the comparison result C2 is maintained to have a logic value of "1", as shown in FIG. 3.

In addition, if the Y-th bit of the comparison result has a specific logic value (e.g., logic value "0"), the Y-th bit of the following comparison result has a chance to be changed. In some embodiments, X and Y are positive integers. For illustrative purposes, each of the pairs has n bits, as described above. X and Y are less than or equal to n, and Y is different from X.

For illustrative purposes, since the first bit corresponding to R1 and the first bit corresponding to R3 have the same logic value (e.g., logic value "0"), the result of the exclusive OR operation on the two bits is logic value "0". Therefore, the first bit of the comparison result C2 is maintained to have a logic value "0".

Accordingly, the second bit of the comparison result C2, the seventh bit of the comparison result C2, and the eighth bit of the comparison result C2 are maintained as logic values "0".

For illustration, since the third bit corresponding to R1 and the third bit corresponding to R3 have different logic values, the result of the exclusive-OR operation on the two bits is a logic value "1". Therefore, the third bit of the comparison result C2 is changed to logic value "1".

Accordingly, the third bit of the comparison result C2, the fourth bit of the comparison result C2, and the sixth bit of the comparison result C2 are maintained as having a logic value of "1".

Therefore, comparison result C1 of 00010000 is adjusted to form comparison result C2 of 00111100. The comparison result C2 is temporarily stored in the recorder 180. In other words, the comparison result C2 is generated by adjusting the previous comparison result C1.

After the comparison result C2 is generated, if there are further other operating conditions to test (e.g., a fourth operating condition), operation 206 is again entered. Next, the device under test 105 is operated under a fourth operating condition. A corresponding countermeasure R4 is thus available. In some embodiments, the fourth operating condition is different from the preceding operating condition.

As shown in fig. 3, the new correspondence R4 of the dut 105 is 01000101. The XOR gate 142 then performs an XOR operation on the corresponding R1 and the corresponding R4 from the memory array 120.

To illustrate with reference to fig. 3, only the fifth bit corresponding to R4 and the corresponding bit corresponding to R1 have different logic values from each other. The fifth bit of the comparison result C2 has a logic value of "1". Therefore, the fifth bit of the comparison result C3 still has a logic value of "1". Each of the other bits corresponding to R4 has the same logic value as the corresponding bit corresponding to R1. Therefore, the other bits of the comparison result C3 are maintained. Therefore, the comparison result C3 is the same as the comparison result C2. The comparison result C3 is temporarily stored in the recorder 180.

After the comparison result C3 is generated, if there are other operating conditions to test (e.g., a fifth operating condition), operation 206 is again entered. Next, the operating condition of the device under test 105 is changed from the fourth operating condition to the fifth operating condition. A corresponding countermeasure R5 is thus available. In some embodiments, the fifth operating condition is different from the preceding operating condition.

To illustrate with reference to fig. 3, the new mapping R5 for the dut 105 is 10000110. The XOR gate 142 then performs an XOR operation on the corresponding R1 and the corresponding R5 from the memory array 120.

The first bit for R5 and the first bit for R1 have different logic values. Therefore, the first bit of the comparison result C4 is adjusted to have a logic value "1". Accordingly, the second bit of the comparison result C4, the seventh bit of the comparison result C4, and the eighth bit of the comparison result C4 are adjusted to have a logic value of "1". Therefore, comparison result C3 of 00111100 is adjusted to form comparison result C4 of 11111111. The comparison result C4 is temporarily stored in the recorder 180.

To illustrate with respect to FIG. 3, after the comparison result C4 is generated, if there are no operating conditions to test, operation 214 of method 200 is performed. The comparison result C4 is regarded as the aforementioned final comparison result FC.

In other embodiments, the comparison circuit 140 includes a plurality of exclusive OR gates 142. Illustratively, the comparison circuit 140 includes eight exclusive OR gates 142. Each XOR gate performs an XOR operation on the corresponding bit of R1 and on the corresponding bit of one of R1.

The number of exclusive OR gates 142 within the comparison circuit 140 is for illustration purposes only. Various numbers of exclusive-or gates 142 within the comparison circuit 140 are within the scope of the present disclosure.

In operation 214, the counter 162 generates a value having the same logic value as the bit in the comparison result C4. In some embodiments, the logical value of the bit in the comparison result C4 is a logical value of "1". In other words, the counter 162 counts the number of bits having a logical value "1" within the comparison result FC. Illustratively, the comparison result FC is 11111111. Thus, the value counted by the counter 162 is equal to the value 8. As described above, in some embodiments, the counter 162 is implemented as a group counter composed of a plurality of adders (not shown). Therefore, in the above embodiments, the value 8 is a binary type, such as 1000, but not limited thereto.

In operation 216, the maximum hamming distance generating circuit 164 generates the maximum hamming distance HD according to the value from the counter 162 and the total number of bits of the comparison result FC. Illustratively, the maximum hamming distance generating circuit 164 calculates a ratio of the value generated by the counter to the total number of bits of the comparison result FC. In other words, if the comparison result C4 has n bits and the comparison result C4 has m bits with logic value "1", the maximum Hamming distance HD is substantially equal to m/n, where m and n are positive integers.

In some embodiments, the maximum hamming distance HD is presented in percentage. As shown in fig. 3, the total number of bits of the comparison result FC is 8. The number of bits of the bit having the logic value "1" in the comparison result FC is also 8. Thus, the maximum Hamming distance HD is 100%.

The foregoing method 200 includes exemplary operations, but the operations of the method 200 do not necessarily have to be performed in the order described. The order of the operations of the method 200 disclosed in this disclosure may be altered or the operations may be performed concurrently or with partial concurrence, as appropriate, without departing from the spirit and scope of the various embodiments of the present disclosure.

Furthermore, since the aforementioned maximum hamming distance HD is generated according to the correspondence of the same device under test 105, in some embodiments, the maximum hamming distance HD is an internal hamming distance of the device under test 105. The maximum Hamming distance HD represents the maximum difference between any two of the corresponding pairs R1-R5 depicted in FIG. 3. Taking fig. 3 as an illustration, among the corresponding R1-R5 of the dut 105, all bits corresponding to R3 are different from the corresponding bits corresponding to R5, respectively. In other words, the difference between the corresponding R3 and the corresponding R5 is 100%. Thus, the maximum Hamming distance HD of the device under test 105 is 100%.

In some embodiments, when the maximum hamming distance HD of the device under test is 0%, it represents that the device under test is perfectly repeatable and robust under different operating environments.

In some embodiments, when the maximum hamming distance HD is higher than the predetermined value, the device under test 105 needs to be corrected or debugged. The preset value is dynamically adjustable, but not limited thereto.

In some embodiments, device 100 and device under test 105 are disposed on the same wafer or the same die. Thus, the device 100 measures the device under test 105 directly on the wafer or wafer. In some embodiments, the device 100 measures the device under test 105 on a Wafer Acceptance Testing (WAT) station.

In the device 100 discussed in the present disclosure, the device 100 is measuring the device under test 105 inline without downloading any counterpart to the device under test 105. In addition to this, only the maximum hamming distance HD is output. Therefore, the time for downloading the response can be saved, and the storage space for storing the downloaded response can be saved.

Please refer to fig. 4. FIG. 4 is a schematic diagram illustrating an apparatus 100A and a memory 105A according to various embodiments of the disclosure.

In some embodiments, the device 100A is a test device. The apparatus 100A is configured to test the robustness of the memory 105A. In some embodiments, the apparatus 100A is applied to or built as an internal hamming distance analyzer. The apparatus 100A is configured to generate a maximum Hamming distance HD for the memory 105A. The maximum hamming distance HD represents the robustness of the memory 105A. In some embodiments, the hamming distance HD indicates the number of different bits between the two bins.

In some embodiments, the memory 105A is, for example, but not limited to, a static random access memory, a flash memory, or the like. It is within the scope of the present disclosure to implement the device under test 105 or the various memory arrays or cells implemented in the device under test 105. In other embodiments, the memory 105A includes the memory circuit 101A and the memory circuit 103A. In some embodiments, the memory circuit 101A is a device under test.

In some embodiments, the memory circuit 101A and the memory circuit 103A operate under various operating conditions according to the actual application. Various conditions correspond to various operating environments. Illustratively, the various operating conditions include various supply voltages, various operating temperatures, various operating frequencies, or combinations of the foregoing.

As shown in FIG. 4, in some embodiments, device 100A includes a comparison circuit 140A and a calculation circuit 160A. In some embodiments, the device 100A also includes a recorder 180A. The comparison circuit 140A is coupled to the memory 105A. The recorder 180A is coupled to the comparison circuit 140A. The calculation circuit 160A is coupled to a recorder 180A. In some embodiments, the comparison circuit 140A comprises or is implemented by an XOR gate.

The above discussion is merely illustrative of exemplary connections that may be used in accordance with various embodiments. It should be understood that the various embodiments are not limited to the specific connections described above or shown in fig. 4.

As shown in FIG. 4, the memory circuit 103A is configured to generate at least one response of the memory circuit 101A and to store the at least one response. In some embodiments, the at least one response is copied or rewritten by the memory circuit 101A to the memory circuit 103A, so that the at least one response generated by the memory circuit 103A is the same as the at least one response generated by the memory circuit 101A.

As shown in FIG. 4, the comparison circuit 140A receives the correspondence from the memory circuit 103A. In some embodiments, the comparison circuit 140A also receives the responses obtained from the memory circuit 101A under different operating conditions. The comparison circuit 140A is configured to sequentially compare the pair from the memory circuit 103A with the pair from the memory circuit 101A to generate corresponding comparison results.

In some embodiments, the comparison circuit 140A is configured to perform the exclusive-OR operation of the pair from the memory circuit 103A and the pair from the memory circuit 101A sequentially to generate the corresponding comparison result. These comparison results are output to the recorder 180A. In some embodiments, when the comparison result is obtained, the roles of the memory circuit 101A and the memory circuit 103A are exchanged, and the aforementioned operations are performed again.

As shown in FIG. 4, the register 180A is configured to temporarily store the comparison result generated by the comparison circuit 140A. Then, the recorder 180A generates a final comparison result FC based on the comparison result. In some embodiments, the final comparison result FC indicates a comparison result generated by comparing the response from the memory circuit 103A with the final response from the memory circuit 101A.

In some embodiments, recorder 180A includes recording circuit 182A and recording circuit 184A. The recording circuit 182A is configured to temporarily store comparison results generated by comparing the transactions from the memory circuit 103A and the transactions from the memory circuit 101A under different operating conditions. The recording circuit 184A is configured to temporarily store comparison results generated by comparing the transactions from the memory circuit 101A and the transactions from the memory circuit 103A under different operating conditions.

As shown in fig. 4, the calculation circuit 160A is configured to obtain the final comparison result FC from the recording circuit 182A and the recording circuit 184A. The calculation circuit 160A is further configured to output the maximum hamming distance HD according to the final comparison result FC. The maximum hamming distance HD represents the maximum difference between the two pairs from the memory circuit 101A and the two pairs from the memory circuit 103A.

As shown in fig. 4, in some embodiments, the calculation circuit 160A includes a counter 162A and a maximum hamming distance generation circuit 164A. The counter 162A is coupled to the recording circuit 182A and the recording circuit 184A. The maximum hamming distance generating circuit 164A is coupled to the counter 162A.

The counter 162A is configured to receive the final comparison result FC from the recording circuit 182A and the recording circuit 184A. Based on the final comparison result FC, the counter 162A counts a value indicating the number of bits of the final comparison result FC having the same logic value. In some embodiments, the same logical value is "1". In other words, if 4 bits of the final comparison result FC have a logic value of "1", the counter 162A outputs data indicating 4 to the maximum hamming distance generating circuit 164A. In some embodiments, the counter 162A is implemented as a group counter composed of a plurality of adders (not shown). In other embodiments, counter 162A is implemented with other logic gates.

Then, the maximum hamming distance generating circuit 164A generates the maximum hamming distance HD according to the above values and the total number of bits of the final comparison result FC. The maximum hamming distance HD represents the maximum difference between the two responses from the memory circuit 101A. In some embodiments, the maximum hamming distance generating circuit 164A is implemented by or includes a subtractor (not shown), but not limited thereto. In other embodiments, the maximum hamming distance generating circuit 164A is implemented with other logic gates.

Please refer to fig. 5. FIG. 5 is a flow chart illustrating a method 200A of operating the apparatus 100A and the memory 105A of FIG. 4 according to various embodiments of the present disclosure.

The following method 200A, illustrated in FIG. 5, describes the operation between the device 100A and the memory 105A. For ease of understanding, the method 200A is discussed in conjunction with FIG. 4.

In operation 202A, a countermeasure of the memory circuit 101A is obtained when the memory circuit 101A operates under the first operating condition. In some embodiments, the first operating condition is an initial operating condition of the memory circuit 101A, but is not limited thereto.

In operation 204A, a copy or a rewrite is applied to the memory circuit 103A. In some embodiments, the correspondence is copied or rewritten from the memory circuit 101A and maintained in the memory circuit 103A.

In operation 206A, the operating conditions of the memory circuit 101A are changed. For example, the operating condition of the memory circuit 101A is changed from the first operating condition to the second operating condition. In some embodiments, the second operating condition is different from the first operating condition.

In operation 208A, a new countermeasure for the memory circuit 101A is obtained. As described above, when the operating conditions of the memory circuit 101A change, the contents of the memory circuit 101A change accordingly.

In operation 210A, the comparison circuit 140A compares the new pair with the pair of the memory circuit 101A to generate a comparison result.

In operation 212A, it is determined whether there are other operating conditions for testing the memory circuit 101A. In some embodiments, the verification step is performed by a controller (not shown) or a processing circuit (not shown), but not limited thereto. If there are other operating conditions to test (e.g., the third operating condition), operation 206A is resumed. In other words, the operating condition of the memory circuit 101A is changed from the second operating condition to the third operating condition. In some embodiments, the third operating condition is different from the second operating condition and is different from the first operating condition.

If there are no other operating conditions to test, operation 202B of method 200A is performed. In some embodiments, the roles of memory circuit 101A and memory circuit 103A are reversed, as described below.

In operation 202B, a correspondence for the memory circuit 103A is obtained when the memory circuit 103A operates under the first corresponding operating condition.

In operation 204B, a copy or a rewrite is applied to the memory circuit 101A. In some embodiments, the correspondence is copied or rewritten from the memory circuit 103A and maintained at the memory circuit 101A.

In operation 206B, the operating conditions of the memory circuit 103A are changed. For example, the operating condition of the memory circuit 103A is changed from the first operating condition to the second operating condition. In some embodiments, the second operating condition is different from the first operating condition.

In operation 208B, a new countermeasure for the memory circuit 103A is obtained. As described above, when the operating condition of the memory circuit 103A changes, the contents of the memory circuit 103A change accordingly.

In operation 210B, the comparison circuit 140A compares the new pair with the pair of the memory circuit 103A to generate a comparison result.

In operation 212B, it is determined whether there are other operating conditions for testing the memory circuit 103A. If there are other operating conditions to test (e.g., the third operating condition), operation 206B is resumed.

If there are no other operating conditions to test, operation 214A of method 200A is performed.

In operation 214A, the counter 162A generates a value having the same logic value as the bit in the comparison result. In some embodiments, the logical value of the bit in the comparison result is a logical value of "1". In other words, the counter 162A counts the number of bits having a logical value "1" within the comparison result FC. Illustratively, the comparison result FC is 11111111 (binary). Therefore, the value counted by the counter 162A is equal to the value 8. As described above, in some embodiments, the counter 162A is implemented as a group counter composed of a plurality of adders (not shown). Therefore, in the above embodiments, the value 8 is a binary type, such as 1000, but not limited thereto.

In operation 216A, the maximum hamming distance generating circuit 164A generates the maximum hamming distance HD according to the value from the counter 162A and the total number of bits of the comparison result FC. Illustratively, the maximum hamming distance generating circuit 164A calculates a ratio of the value generated by the counter to the total number of bits of the comparison result FC. In other words, if the comparison result has n bits and the comparison result has m bits with logic value "1", the maximum Hamming distance HD is substantially equal to m/n, where m and n are positive integers.

In contrast to the memory array 120 and the device under test 105 shown in FIG. 1, which in some embodiments are memory arrays under test, the embodiment of FIG. 4 depicts only one memory 105A including memory circuit 101A and memory circuit 103A, configured as a memory array and a device under test, respectively, or vice versa. In the embodiment of FIG. 4, memory 105A may be configured as a device under test for generating PUF bits, and the memory array is used to store a correspondence from the device under test. Thus, the overall area of the device in fig. 4 can be reduced.

In some embodiments, an apparatus for testing a memory including a first memory circuit and a second memory circuit is disclosed. The second memory circuit is configured to store a first mapping of the first memory circuit. The device comprises a comparison circuit and a calculation circuit. The comparison circuit is configured to compare the first pair stored in the second memory circuit with a plurality of pairs of the first memory circuit operating under different conditions to generate a plurality of first comparison results. The calculation circuit is configured to output a maximum hamming distance according to the first comparison result, wherein the maximum hamming distance is between the first corresponding and two of the plurality of corresponding of the first memory circuit.

In some embodiments, the first memory circuit is configured to store a second mapping of the second memory circuit. The comparison circuit is configured to compare the second pair stored in the first memory circuit with a plurality of pairs of the second memory circuit operating under different conditions to generate a plurality of second comparison results.

In various embodiments, the calculation circuit is configured to output a maximum hamming distance according to the second comparison result, wherein the maximum hamming distance is between the second counterpart and two of the plurality of counterparts of the second memory circuit.

In some embodiments, the device also includes a recorder, and the recorder includes a first recording circuit and a second recording circuit. The first recording circuit is configured to store a first comparison result for calculating a maximum hamming distance, and the second recording circuit is configured to store a second comparison result for calculating the maximum hamming distance.

In various embodiments, the comparison circuit comprises an exclusive-or gate. The XOR gate is configured to perform an XOR operation for each of the first counter and the first memory circuit and to perform an XOR operation for each of the second counter and the second memory circuit.

In some embodiments, the computational circuitry includes a counter. The counter is configured to generate a first value, wherein the first value indicates a number of bits having a same logic value in a corresponding one of the first comparison results, and the counter is configured to generate a second value, wherein the second value indicates a number of bits having a same logic value in a corresponding one of the second comparison results.

In various embodiments, the calculation circuit is further configured to generate the maximum hamming distance according to the first value and the number of bits of the first comparison result corresponding to the comparison result, and generate the maximum hamming distance according to the second value and the number of bits of the second comparison result corresponding to the comparison result.

A method is also disclosed, which includes the following operations. A first mapping of a first memory circuit of the memory under a first operating condition is maintained. The first correspondences stored in the second memory circuits of the memory are sequentially compared with the correspondences of the first memory circuits under the operating condition to generate a plurality of first comparison results. The aforementioned operating conditions are different from each other. Each comparison result of the plurality of first comparison results is generated by adjusting a previous comparison result of the plurality of first comparison results. Obtaining a maximum difference value according to the first comparison results, wherein the maximum difference value is between the first corresponding pair and the corresponding pair of the first memory circuit.

In some embodiments, the method further comprises the following operations. Maintaining a second mapping of a second memory circuit of the memory under a second operating condition. The second pair stored in the first memory circuit of the memory is sequentially compared with a plurality of pairs of the second memory circuit under the operating condition to generate a plurality of second comparison results. The aforementioned operating conditions are different from each other. Each comparison result of the plurality of second comparison results is generated by adjusting a previous comparison result of the plurality of second comparison results.

In various embodiments, maintaining the first transaction of the first memory circuit includes the following operations. The first pair is copied into a second memory circuit of the memory. Maintaining the copied first pair in the second memory circuit.

In some embodiments, maintaining the first app includes the following operations. A first mapping is generated by the second memory circuit.

In various embodiments, maintaining the second correspondence for the second memory circuit includes the following operations. Copying the second pair into the first memory circuit of the memory. Maintaining the copied second pair in the first memory circuit.

In some embodiments, maintaining the second correspondence includes the following operations. A second mapping is generated by the first memory circuit.

In some embodiments, the method further comprises the following operations. The first comparison result and the second comparison result are temporarily stored to calculate the maximum hamming distance.

In various embodiments, obtaining the maximum difference value includes the following operations. A first value is generated, wherein the first value indicates the number of bits having the same logic value in the corresponding comparison result of the first comparison result. Generating a second value, wherein the second value indicates the number of bits having the same logic value in the corresponding comparison result of the second comparison result.

In some embodiments, outputting the maximum hamming distance also includes the following operations. The maximum Hamming distance is generated according to the first value and the bit number of the first comparison result corresponding to the comparison result. Generating the maximum Hamming distance according to the second value and the bit number of the second comparison result corresponding to the comparison result.

In various embodiments, comparing the first mapping of the second memory circuit stored in the memory with the mapping of the first memory circuit includes the following operations. An exclusive OR operation is performed on the first pair stored in the second memory circuit and each of the first memory circuits.

In some embodiments, comparing the second pair of the first memory circuit and the second memory circuit stored in the memory includes the following operations. An exclusive-OR operation is performed on the second pair stored in the first memory circuit and each of the second pairs.

A method is also disclosed, which includes the following operations. A first memory circuit of the memory under different conditions from each other is operated to obtain a plurality of correspondences of the first memory circuit. A plurality of transactions for the first memory circuit are stored in a second memory circuit of the memory. The plurality of correspondences of the first memory circuit of the second memory circuit stored in the memory are exclusive-ORed with other correspondences of the first memory circuit in sequence to generate a final comparison result. And outputting the maximum Hamming distance between the first corresponding and the other corresponding according to the final comparison result.

In some embodiments, outputting the maximum hamming distance includes the following operations. A value is generated, wherein the value indicates a number of bits having the same logic value in the final comparison result. The maximum Hamming distance is generated based on the value and the number of bits of the final comparison result.

The foregoing summary, as well as the following detailed description of the embodiments, is provided to enable one of ordinary skill in the art to make and use the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.

Claims (1)

1. An apparatus for testing a memory, the memory including a first memory circuit and a second memory circuit, the second memory circuit configured to store a first pair of the first memory circuit, the apparatus comprising:

a comparison circuit configured to compare the first pair stored in the second memory circuit with a plurality of pairs of the first memory circuit operating under different conditions to generate a plurality of first comparison results; and

a calculation circuit configured to output a maximum Hamming distance according to the first comparison results, wherein the maximum Hamming distance is between the first corresponding and two of the plurality of corresponding of the first memory circuit.