CN110618602A - Timing circuit, chip, time-amplitude converter and control method thereof - Google Patents
Timing circuit, chip, time-amplitude converter and control method thereof Download PDFInfo
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- CN110618602A CN110618602A CN201910821804.0A CN201910821804A CN110618602A CN 110618602 A CN110618602 A CN 110618602A CN 201910821804 A CN201910821804 A CN 201910821804A CN 110618602 A CN110618602 A CN 110618602A
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- G—PHYSICS
- G04—HOROLOGY
- G04F—TIME-INTERVAL MEASURING
- G04F10/00—Apparatus for measuring unknown time intervals by electric means
- G04F10/005—Time-to-digital converters [TDC]
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Abstract
The invention discloses a timing circuit, a chip, a time-amplitude converter and a control method thereof, wherein the timing circuit comprises a cascode current mirror module, a switch circuit module and a charging timing module; the first end of the cascode current mirror module receives the reference current, the first end of the cascode current mirror module is connected with the first end of the switch circuit module, and the second end of the switch circuit module is connected with the first end of the charging timing module; the cascode current mirror module is used for copying reference current; the switch circuit module is used for receiving the fine counting enable signal and controlling whether the charging timing module is charged or not according to the fine counting enable signal; and the charging timing module is used for receiving the reset signal, resetting according to the reset signal and timing charging according to the reference current. The method comprises the steps of firstly resetting for a period of time and then charging, and resetting for a short period of time, so that the problem of charge redistribution is solved, and the timing precision of the time-amplitude converter is improved.
Description
Technical Field
The invention relates to the technical field of time sequence control, in particular to a timing circuit, a chip, a time-amplitude converter and a control method thereof.
Background
The main function of a Time-to-Amplitude Converter (TAC) is to measure Time differences in the order of picoseconds. The basic working principle of the TAC is to charge a capacitor by using reference current, but the problem of charge distribution is easily caused when the capacitor is charged, the accuracy of the TAC is seriously affected by the problem of charge distribution, and the timing function of the TAC cannot be correctly executed in application.
Disclosure of Invention
The invention mainly aims to provide a timing circuit, a chip, a time amplitude converter and a control method thereof, and aims to solve the technical problem that the timing precision of the time amplitude converter in the prior art is not high.
In order to achieve the above object, the timing circuit provided by the present invention comprises a cascode current mirror module, a switch circuit module and a charging timing module;
the first end of the cascode current mirror module receives a reference current, the first end of the cascode current mirror module is connected with the first end of the switch circuit module, the second end of the switch circuit module is connected with the first end of the charging timing module, the second end of the charging timing module is grounded, the third end of the charging timing module receives a reset signal, and the third end of the switch circuit module receives a fine counting enable signal;
the cascode current mirror module is used for receiving the reference current and copying the reference current;
the switch circuit module is used for receiving a fine counting enable signal and controlling whether the charging timing module is charged or not according to the fine counting enable signal;
and the charging timing module is used for receiving a reset signal, resetting according to the reset signal and carrying out charging timing according to the reference current.
Preferably, the cascode current mirror module includes a first metal oxide semiconductor field effect transistor MOS transistor, a second MOS transistor, a third MOS transistor, and a fourth MOS transistor;
the first end of the switch circuit module is connected with the drain electrode of the fourth MOS tube, the grid electrode of the fourth MOS tube is connected with the grid electrode of the third MOS tube, the source electrode of the fourth MOS tube is connected with the drain electrode of the second MOS tube, the source electrode of the second MOS tube is connected with the source electrode of the first MOS tube, the grid electrode of the first MOS tube is connected with the grid electrode of the second MOS tube, the drain electrode of the first MOS tube is connected with the source electrode of the third MOS tube, the first end of the charging timing module is connected with the second end of the switch circuit module, and the drain electrode of the third MOS tube receives the reference current.
Preferably, the switch circuit module comprises a fifth MOS transistor;
the source electrode of the fifth MOS tube is connected with the drain electrode of the fourth MOS tube, the drain electrode of the fifth MOS tube is connected with the first end of the charging timing module, and the grid electrode of the fifth MOS tube receives the fine counting enabling signal.
Preferably, the charge timing module comprises a capacitor;
and the first end of the capacitor is connected with the drain electrode of the fifth MOS tube, and the second end of the capacitor is grounded.
Preferably, the charging timing module further comprises a sixth MOS transistor;
the drain electrode of the sixth MOS tube is connected with the first end of the capacitor, the source electrode of the sixth MOS tube is connected with the second end of the capacitor, and the grid electrode of the sixth MOS tube receives a reset signal.
The invention provides a control method of a time-amplitude converter, which is based on a timing circuit, wherein the timing circuit comprises a cascode current mirror module, a switch circuit module and a charging timing module;
the control method of the time amplitude converter comprises the following steps:
the cascode current mirror module receives a reference current and copies the reference current;
the switch circuit module receives a fine counting enabling signal and controls whether the charging timing module is charged or not according to the fine counting enabling signal;
the charging timing module receives a reset signal, resets according to the reset signal, and performs charging timing according to the reference current.
The invention also proposes a time-amplitude converter comprising a timing circuit as described above.
The invention also proposes a chip comprising a time-amplitude converter as described above, or applying a control method of a time-amplitude converter as described above.
The invention discloses a timing circuit which comprises a cascode current mirror module, a switch circuit module and a charging timing module, wherein the first end of the cascode current mirror module receives a reference current, the first end of the cascode current mirror module is connected with the first end of the switch circuit module, the second end of the switch circuit module is connected with the first end of the charging timing module, the second end of the charging timing module is grounded, the cascode current mirror module is used for receiving the reference current and copying the reference current so as to accurately copy the reference current, and the current capability cannot be weakened; the charging timing module is used for receiving a reset signal, resetting according to the reset signal, performing charging timing according to the reference current, resetting for a period of time and then charging, and resetting for a short period of time, so that the problem of charge redistribution is solved, and the timing precision of the time-amplitude converter is improved.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the structures shown in the drawings without creative efforts.
FIG. 1 is a functional block diagram of a first embodiment of a timing circuit of the present invention;
FIG. 2 is a circuit schematic of a second embodiment of the timing circuit of the present invention;
FIG. 3 is a first timing diagram of a timing circuit according to a second embodiment of the present invention;
FIG. 4 is a second timing diagram of the timing circuit according to the second embodiment of the present invention;
FIG. 5 is a third timing diagram of the timing circuit according to the second embodiment of the present invention;
FIG. 6 is a timing diagram of the timing circuit according to the second embodiment of the present invention;
fig. 7 is a flowchart illustrating a control method of a time-to-amplitude converter according to a first embodiment of the present invention.
The reference numbers illustrate:
| reference numerals | Name (R) | Reference numerals | Name (R) |
| 100 | Cascode current mirror module | M1 | First MOS transistor |
| 200 | Switch circuit module | M2 | Second MOS transistor |
| 300 | Charging timerModule | M3 | Third MOS transistor |
| C | Capacitor with a capacitor element | M4 | Fourth MOS transistor |
| M5 | Fifth MOS transistor | M6 | Sixth MOS transistor |
The implementation, functional features and advantages of the objects of the present invention will be further explained with reference to the accompanying drawings.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It should be noted that all the directional indicators (such as up, down, left, right, front, and rear … …) in the embodiment of the present invention are only used to explain the relative position relationship between the components, the movement situation, etc. in a specific posture (as shown in the drawing), and if the specific posture is changed, the directional indicator is changed accordingly.
In addition, the descriptions related to "first", "second", etc. in the present invention are for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In addition, the technical solutions in the embodiments may be combined with each other, but it must be based on the realization of those skilled in the art, and when the technical solutions are contradictory or cannot be realized, such a combination should be considered to be absent and not within the protection scope of the present invention.
The invention provides a timing circuit.
Referring to fig. 1, fig. 1 is a circuit block diagram of a timing circuit according to a first embodiment of the present invention.
As shown in fig. 1, in the embodiment of the present invention, the timing circuit includes a cascode current mirror module 100, a switch circuit module 200, and a charging timing module 300;
the first end of the cascode current mirror module 100 receives a reference current, the first end of the cascode current mirror module 100 is connected to the first end of the switch circuit module 200, the second end of the switch circuit module 200 is connected to the first end of the charging timing module 300, the second end of the charging timing module 300 is grounded, the third end of the charging timing module 300 receives a reset signal, and the third end of the switch circuit module 200 receives a fine count enable signal;
the cascode current mirror module 100 is configured to receive the reference current and copy the reference current;
the switch circuit module 200 is configured to receive a fine count enable signal, and control whether to charge the charging timing module 300 according to the fine count enable signal;
the charging timing module 300 is configured to receive a reset signal, reset according to the reset signal, and perform charging timing according to the reference current.
It should be understood that, as shown in fig. 1, IREF is a reference current, and charging of the capacitor by the power supply for a fixed period of time is achieved by externally supplying a fixed current; when the count down enable signal CUR _ CON is low, the switch circuit module 200 is turned on, and the power supply starts to charge the charging timing module 300, where the charging timing module 300 includes a capacitor, that is, the capacitor in the charging timing module 300 is charged, and when the count down enable signal CUR _ CON is high, the switch circuit module 200 is turned off, and an external circuit starts to read out a voltage across the capacitor in the charging timing module 300; RESET is a RESET signal, and when an external circuit reads out the voltage of the capacitor, the RESET signal is high, and RESETs the capacitor in the charging timing module 300 to wait for the next charging timing.
In this embodiment, the cascode current mirror module 100 is configured to copy the reference current to accurately copy the reference current, and the current capability is not weakened; the charging timing module 300 is configured to receive a reset signal, reset according to the reset signal, perform charging timing according to the reference current, and perform resetting for a period of time before performing charging, so as to solve the problem of charge redistribution and improve the timing accuracy of the time-amplitude converter after resetting for a short period of time.
Referring to fig. 2, fig. 2 is a schematic circuit diagram of a timing circuit according to a second embodiment of the present invention.
As shown in fig. 2, in the embodiment of the present invention, the cascode current mirror module 100 includes a first mosfet M1, a second mosfet M2, a third mosfet M3, and a fourth mosfet M4;
the first end of the switch circuit module 200 is connected to the drain of the fourth MOS transistor M4, the gate of the fourth MOS transistor M4 is connected to the gate of the third MOS transistor M3, the source of the fourth MOS transistor M4 is connected to the drain of the second MOS transistor M2, the source of the second MOS transistor M2 is connected to the source of the first MOS transistor M1, the gate of the first MOS transistor M1 is connected to the gate of the second MOS transistor M2, the drain of the first MOS transistor M1 is connected to the source of the third MOS transistor M3, the first end of the charge timing module 300 is connected to the second end of the switch circuit module 200, and the drain of the third MOS transistor M3 receives the reference current.
The switching circuit module 200 comprises a fifth MOS transistor M5;
the source of the fifth MOS transistor M5 is connected to the drain of the fourth MOS transistor M4, the drain of the fifth MOS transistor M5 is connected to the first end of the charging timing module 300, and the gate of the fifth MOS transistor M5 receives the fine count enable signal.
The charge timing module 300 includes a capacitor C;
the first end of the capacitor C is connected with the drain of the fifth MOS transistor M5, and the second end of the capacitor C is grounded.
The charging timing module 300 further includes a sixth MOS transistor M6;
the drain of the sixth MOS transistor M6 is connected to the first end of the capacitor C, the source of the sixth MOS transistor M6 is connected to the second end of the capacitor C, and the gate of the sixth MOS transistor M6 receives a reset signal.
Note that the structures formed by M1 to M4 are cascode current mirrors. The purpose is to accurately copy IREF given from the outside to the branch where M4 is located, and to charge the capacitor C when M5 is turned on. For current mirrors, since the devices all have channel length modulation effects, L is only increased as much as possible to make the current source more accurate, but then the current capability of the devices is reduced. In general, in order to suppress the influence of the channel length modulation effect, the current replication is performed by adopting the structure of the cascode current mirror module 100, and the current capability is not weakened. The source of the second MOS transistor M2 is connected to the source of the first MOS transistor M1, and an AVDD, which is an analog voltage or an analog positive power supply, is provided from the chip.
In a specific implementation, as shown in fig. 3, fig. 3 is a first timing diagram in a second embodiment of the timing circuit of the present invention, where the clock signal CLK is an external reference clock, an event occurrence is a START signal, a STOP termination signal is given from the outside, the STOP is a signal completely synchronized with the reference clock, in order to generate only a fine count, a part of the fine count is a time difference between a rising edge of the START signal and a rising edge of the next CLK immediately adjacent to the rising edge of the START signal, a remaining part of the fine count is a coarse count, the remaining part of the count is completed by a counter, the counter enable signal is synchronized with the CLK, the counter is shifted several times, which indicates that several clock cycles have elapsed, and finally, a coarse count part Td is a count number T, where T is a period of the CLK clock. The CUR CON signal is generated by other logic circuits, i.e. the time difference of the fine count, i.e. the time period during which the capacitor C is charged, during which the voltage on the capacitor C slowly increases and eventually settles at V.
It will be appreciated that, with respect to the calculation of the fine count: when the rising edge of the START signal comes together with the rising edge of CLK, as shown in fig. 4, fig. 4 is a second timing diagram of the second embodiment of the timing circuit of the present invention, the fine counting time is longest, i.e. a whole clock cycle, the voltage on the capacitor C also reaches the maximum value Vmax, and the fine counting time is (V/Vmax) × T, where T is the cycle of CLK.
In a specific implementation, the rationality is always not in good agreement with the reality, the TAC timing in actual operation is not as simple as the theoretical analysis, as shown in fig. 5, fig. 5 is a third timing diagram in the second embodiment of the timing circuit of the present invention, and when the capacitor C is charged in a fixed time period, the voltage on the capacitor C does not change from 0, but rises to a certain value, and then slowly increases based on the value. Since the fine counting is the conversion from time to voltage amplitude, if the voltage amplitude is changed, the timing is inaccurate, and the TAC function can not be realized accurately.
It should be understood that, in order to solve the above problem of inaccurate timing, we propose a new timing control, which uses the control of the over-RESET delay circuit to delay the RESET signal for a certain time, so as to solve the above problem of inaccurate timing and correctly implement the TAC function. The RESET delay circuit module has no special requirement, and the embodiment adopts voltage-controlled delay, and the delay can be controlled by voltage, so that the design and analysis of a later circuit are facilitated.
It should be noted that the above timing inaccuracy problem occurs because when the CUR _ CON is low, the M5 tube is turned on, the power supply starts to charge the capacitor C, but at the moment when the switch is opened, the charge accumulated in the source of the M5 tube is inconsistent with the charge on the upper plate of the capacitor C, and then the charge redistribution problem occurs, and the voltage on the capacitor C does not change from zero due to the charge redistribution.
In a specific implementation, in order to solve the problem of inaccurate timing, a control timing sequence as shown in fig. 6 is proposed, and fig. 6 is a control timing sequence diagram in a second embodiment of the timing circuit of the present invention. The control time sequence is mainly characterized in that the duration of the reset signal is long, after the M5 tube is conducted, the capacitor C is not immediately charged, but is reset for a period of time and then charged, so that the problem of charge redistribution can be solved after a short period of time, and the fine counting can be accurate.
It should be noted that, when the time difference between START and STOP, i.e. the fine count + the coarse count, is calculated, theoretically, when the START signal gradually approaches the STOP signal, the overall time difference should be linearly decreased, but due to the timing solution of TAC partial charge redistribution, a weak jump may occur in the periodic variation, and the later test may be solved by the scale, so that although TAC does not charge the capacitor C within an entire fine count time difference, this does not affect the measurement of the later time.
In the embodiment, the charge is carried out after the reset is carried out for a period of time, and the reset is carried out for a short period of time, so that the problem of charge redistribution is solved, and the timing precision of the time-amplitude converter is improved.
The present invention further provides a time-amplitude converter, which includes the above-mentioned timing circuit, and the specific structure of the timing circuit refers to the above-mentioned embodiments. The time-amplitude converter can be a time sequence control hand washer or other equipment.
Referring to fig. 7, based on the time-amplitude converter, fig. 7 is a flowchart of a first embodiment of a control method of the time-amplitude converter according to the present invention; the invention also provides a first embodiment of a control method of the time-amplitude converter.
The circuit is based on a timing circuit, and the timing circuit comprises a cascode current mirror module, a switch circuit module and a charging timing module;
the control method of the time amplitude converter comprises the following steps:
step S10: the cascode current mirror module receives a reference current and copies the reference current;
step S20: the switch circuit module receives a fine counting enabling signal and controls whether the charging timing module is charged or not according to the fine counting enabling signal;
step S30: the charging timing module receives a reset signal, resets according to the reset signal, and performs charging timing according to the reference current.
It should be understood that, as shown in fig. 1, IREF is a reference current, and charging of the capacitor by the power supply for a fixed period of time is achieved by externally supplying a fixed current; when the count down enable signal CUR _ CON is low, the switch circuit module is turned on, and the power supply starts to charge the charging timing module, wherein the charging timing module comprises a capacitor, namely the capacitor in the charging timing module is charged; RESET is a RESET signal, and when an external circuit reads out the voltage of the capacitor, the RESET signal is high, and RESETs the capacitor in the charging timing module to wait for the next charging timing.
In this embodiment, the cascode current mirror module is configured to copy the reference current to accurately copy the reference current, and the current capability is not weakened; the charging timing module is used for receiving a reset signal, resetting according to the reset signal, performing charging timing according to the reference current, resetting for a period of time and then charging, and resetting for a short period of time, so that the problem of charge redistribution is solved, and the timing precision of the time-amplitude converter is improved.
In addition, the invention also provides a chip, which comprises the time-amplitude converter or the control method applying the time-amplitude converter. It will be readily appreciated that the chip has at least the benefits associated with the above embodiments.
The above description is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention, and all modifications and equivalents of the present invention, which are made by the contents of the present specification and the accompanying drawings, or directly/indirectly applied to other related technical fields, are included in the scope of the present invention.
Claims (9)
1. A timing circuit is characterized by comprising a cascode current mirror module, a switch circuit module and a charging timing module;
the first end of the cascode current mirror module receives a reference current, the first end of the cascode current mirror module is connected with the first end of the switch circuit module, the second end of the switch circuit module is connected with the first end of the charging timing module, the second end of the charging timing module is grounded, the third end of the charging timing module receives a reset signal, and the third end of the switch circuit module receives a fine counting enable signal;
the cascode current mirror module is used for receiving the reference current and copying the reference current;
the switch circuit module is used for receiving a fine counting enable signal and controlling whether the charging timing module is charged or not according to the fine counting enable signal;
and the charging timing module is used for receiving a reset signal, resetting according to the reset signal and carrying out charging timing according to the reference current.
2. The timing circuit of claim 1, wherein the cascode current mirror module comprises a first metal oxide semiconductor field effect transistor (MOS) transistor, a second MOS transistor, a third MOS transistor, and a fourth MOS transistor;
the first end of the switch circuit module is connected with the drain electrode of the fourth MOS tube, the grid electrode of the fourth MOS tube is connected with the grid electrode of the third MOS tube, the source electrode of the fourth MOS tube is connected with the drain electrode of the second MOS tube, the source electrode of the second MOS tube is connected with the source electrode of the first MOS tube, the grid electrode of the first MOS tube is connected with the grid electrode of the second MOS tube, the drain electrode of the first MOS tube is connected with the source electrode of the third MOS tube, the first end of the charging timing module is connected with the second end of the switch circuit module, and the drain electrode of the third MOS tube receives the reference current.
3. The timing circuit of claim 2, wherein the switching circuit block includes a fifth MOS transistor;
the source electrode of the fifth MOS tube is connected with the drain electrode of the fourth MOS tube, the drain electrode of the fifth MOS tube is connected with the first end of the charging timing module, and the grid electrode of the fifth MOS tube receives the fine counting enabling signal.
4. A timing circuit in accordance with claim 3, wherein said charge timing module comprises a capacitor;
and the first end of the capacitor is connected with the drain electrode of the fifth MOS tube, and the second end of the capacitor is grounded.
5. The timing circuit of claim 4, wherein the charge timing module further comprises a sixth MOS transistor;
the drain electrode of the sixth MOS tube is connected with the first end of the capacitor, the source electrode of the sixth MOS tube is connected with the second end of the capacitor, and the grid electrode of the sixth MOS tube receives a reset signal.
6. A time-to-amplitude converter, characterized in that it comprises a timing circuit according to any one of claims 1-5.
7. A control method of a time-amplitude converter is applied to the time-amplitude converter as claimed in claim 6, and is characterized in that the control method is based on a timing circuit, and the timing circuit comprises a cascode current mirror module, a switch circuit module and a charging timing module;
the control method of the time amplitude converter comprises the following steps:
the cascode current mirror module receives a reference current and copies the reference current;
the switch circuit module receives a fine counting enabling signal and controls whether the charging timing module is charged or not according to the fine counting enabling signal;
the charging timing module receives a reset signal, resets according to the reset signal, and performs charging timing according to the reference current.
8. A chip, characterized in that it comprises a time-amplitude converter as claimed in claim 6.
9. A chip characterized in that it comprises a control method for the chip to which the time-amplitude converter according to claim 7 is applied.
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| CN201910821804.0A CN110618602B (en) | 2019-08-30 | 2019-08-30 | Timing circuit, chip, time-amplitude converter and control method thereof |
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| CN201910821804.0A CN110618602B (en) | 2019-08-30 | 2019-08-30 | Timing circuit, chip, time-amplitude converter and control method thereof |
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| CN110618602B CN110618602B (en) | 2021-04-09 |
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