CN110611301A - Protection device, protection circuit and terminal equipment - Google Patents

Protection device, protection circuit and terminal equipment Download PDF

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Publication number
CN110611301A
CN110611301A CN201810621645.5A CN201810621645A CN110611301A CN 110611301 A CN110611301 A CN 110611301A CN 201810621645 A CN201810621645 A CN 201810621645A CN 110611301 A CN110611301 A CN 110611301A
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CN
China
Prior art keywords
pmos transistor
signal
resistor
module
tvs
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CN201810621645.5A
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Chinese (zh)
Inventor
武渊
罗伟
王朝
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Honor Device Co Ltd
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Huawei Technologies Co Ltd
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Priority to CN201810621645.5A priority Critical patent/CN110611301A/en
Publication of CN110611301A publication Critical patent/CN110611301A/en
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
    • H02H3/00—Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition with or without subsequent reconnection ; integrated protection
    • H02H3/02—Details
    • H02H3/025—Disconnection after limiting, e.g. when limiting is not sufficient or for facilitating disconnection
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
    • H02H9/00—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection
    • H02H9/04—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage
    • H02H9/042—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage comprising means to limit the absorbed power or indicate damaged over-voltage protection device

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  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Electronic Switches (AREA)

Abstract

The application provides a protection device, protection circuit and terminal equipment, protection device includes: the TVS module is used for absorbing a second electric signal from the first electric signal and outputting a third electric signal to the control module; the first electrical signal is an electrical signal input from an external power supply input end of terminal equipment, the amplitude of the second electrical signal is greater than a first threshold, and the third signal is a signal of the first signal except the second signal absorbed by the TVS module; the control module is used for outputting a first control signal to the switch module when the amplitude of the third electric signal is greater than or equal to a second threshold value, and outputting a second control signal to the switch module when the amplitude of the third electric signal is less than the second threshold value; and the switch module is used for being in an off state under the control of the first control signal or being in a closed state under the control of the second control signal.

Description

Protection device, protection circuit and terminal equipment
Technical Field
The application relates to the technical field of circuits, in particular to a protection device, a protection circuit and terminal equipment.
Background
Electronic equipment (such as mobile phones, notebook computers and the like) is widely applied to various fields, and brings great convenience to production and life of people. However, when the electronic device is charged by using the power grid or is powered by using the power grid, a surge (electrical surge) signal may be generated on a charging path or a power supply path of the electronic device due to a voltage fluctuation of the power grid caused by factors such as instability of the power grid and transient change of a load, which may damage a connection component (e.g., a power management chip) on the charging path or the power supply path of the electronic device, and may even cause fire.
In order to solve the above problems, an Over Voltage Protection (OVP) chip is often used in electronic devices to protect the electronic devices. However, the response speed of the OVP chip is slow, and the duration of the surge signal is often short (several microseconds to tens of microseconds), so that the anti-surge capability of the OVP chip is poor.
Disclosure of Invention
The application provides a protection device, a protection circuit and terminal equipment to improve the anti-surge capacity of the terminal equipment.
In a first aspect, the present application provides a protection device, the protection device includes transient suppression TVS module, control module and switch module, wherein, the input of TVS module is connected with terminal equipment's external power supply input, the output ground connection of TVS module, control module's input with terminal equipment's external power supply input is connected, switch module's input respectively with terminal equipment's external power supply input and control module's output is connected.
The TVS module is used for absorbing a second electric signal from the first electric signal and outputting a third electric signal to the control module; the first electrical signal is an electrical signal input from an external power supply input end of terminal equipment, the amplitude of the second electrical signal is greater than a first threshold, and the third signal is a signal of the first signal except the second signal absorbed by the TVS module; the control module is configured to output a first control signal to the switch module to control the switch module to be in an off state when the amplitude of the third electrical signal is greater than or equal to a second threshold, and output a second control signal to the switch module to control the switch module to be in an on state when the amplitude of the third electrical signal is less than the second threshold; the switch module is used for being in a turn-off state under the control of the first control signal or being in a turn-on state under the control of the second control signal.
Through the scheme, the TVS module in the protection device can absorb the second signal with the amplitude larger than the first threshold value in the first signal input through the external power supply input end of the terminal equipment, reduce the signal with the larger amplitude in the first signal, and the control module can control the working state of the switch module according to the amplitude of a third signal output by the TVS module after absorbing the second signal and a second threshold value, controlling the switch module to be in an off state when the amplitude of the third electrical signal is greater than or equal to a second threshold value, controlling the switch module to be in a closed state when the amplitude of the third electrical signal is less than the second threshold value, so that a third signal having a magnitude not exceeding the second threshold can be input to a subsequent component through the switch module, the damage of the signal with the amplitude exceeding the safety value to subsequent components connected with the switch module can be further prevented. Namely, the control module and the switch module can further protect the subsequent components connected with the switch module under the condition that the TVS module cannot completely absorb the second signal or cannot absorb the second signal in time, and compared with the prior art, the surge prevention capability of the terminal equipment can be improved.
In one possible embodiment, the TVS module may be a TVS diode, one end of the TVS diode is connected to the external power input terminal of the terminal device, and the other end of the TVS diode is grounded, wherein the first threshold is a breakdown voltage of the TVS diode D1.
In one possible embodiment, the TVS module may further include a first capacitor connected in parallel to the TVS diode, and the first capacitor may rapidly respond to and absorb an overvoltage signal (or an overcurrent signal) having a shorter duration than a general surge signal due to static electricity or the like.
In one possible embodiment, the control module includes a first resistor, a second resistor, and a first P-channel Metal Oxide Semiconductor (MOS) transistor; one end of the first resistor is connected with an external power supply input end of the terminal device, the other end of the first resistor is connected with one end of the second resistor and a grid electrode of the first PMOS transistor respectively, the other end of the second resistor is grounded, a source electrode of the first PMOS transistor is connected with the external power supply input end of the terminal device, and a drain electrode of the first PMOS transistor is connected with an input end of the switch module. The second threshold is determined according to the resistance value of the first resistor, the resistance value of the second resistor and the starting voltage of the first PMOS transistor, and the starting voltage of the first PMOS transistor is the minimum voltage between the gate of the first PMOS transistor and the source of the first PMOS transistor when the first PMOS transistor is conducted.
In one possible embodiment, the switch module includes a second PMOS transistor and a third resistor; one end of the third resistor is connected with the output end of the control module and the grid electrode of the second PMOS transistor respectively, the other end of the third resistor is grounded, and the source electrode of the second PMOS transistor is connected with the external power supply input end of the terminal device.
In a possible implementation manner, when the control module includes the first resistor, the second resistor, and the first PMOS transistor, and the switch module includes the second PMOS transistor and the third resistor, the connection relationship between the control module and the switch module is: the one end of first resistance is connected with terminal equipment's external power supply input, the other end of first resistance respectively with the one end of second resistance and the grid of first PMOS transistor is connected, the other end ground connection of second resistance, the source electrode of first PMOS transistor respectively with terminal equipment's external power supply input and the source electrode of second PMOS transistor is connected, the drain electrode of first PMOS transistor respectively with the one end of third resistance and the grid of second PMOS transistor is connected, the other end ground connection of third resistance.
By the above scheme, when the third signal output by the TVS module is greater than or equal to the second threshold, the voltage across the second resistor is greater than or equal to the turn-on voltage of the first PMOS transistor, the first PMOS transistor is turned on, so that the voltage between the gate of the second PMOS transistor and the source of the second PMOS transistor is zero, and the second PMOS transistor is in the off state, so that the third signal cannot enter other components connected to the drain of the second PMOS transistor, and the third signal is prevented from damaging other components subsequently connected to the drain of the second PMOS transistor; when a third signal output by the TVS module is smaller than the second threshold, the voltage across the second resistor is smaller than the turn-on voltage of the first PMOS transistor, and the first PMOS transistor is turned off, so that the turn-on voltage of the second PMOS transistor, and the second PMOS transistor is in a conducting state, so that the third signal can normally enter other components connected to the drain of the second PMOS transistor to be supplied with power or charged, wherein the turn-on voltage of the first PMOS transistor is the minimum voltage between the gate and the source of the first PMOS transistor when the first PMOS transistor is turned on, and the turn-on voltage of the second PMOS transistor is the minimum voltage between the gate and the source of the second PMOS transistor when the second PMOS transistor is turned on. That is to say, the above scheme realizes the function of the OVP chip through the discrete device, can prevent the damage to other components connected with the second PMOS transistor through the signal with a large amplitude input at the external power input end of the terminal device, and has a lower cost compared with the OVP chip.
In a possible implementation manner, the switch module may further include a second capacitor, one end of the second capacitor is connected to the source of the second PMOS transistor, and the other end of the second capacitor is connected to the gate of the second PMOS transistor, so as to reduce a parasitic capacitance between the source of the second PMOS transistor and the gate of the second PMOS transistor, and further, the response speed of the second PMOS transistor may be improved.
In a second aspect, the present application further provides a protection circuit, which is used for protecting a connection component on a charging path or a power supply path of a terminal device in a scenario where the terminal device is charged through a power grid or is powered through the power grid. The circuit comprises a first resistor, a second resistor, a third resistor, a first PMOS transistor and a second PMOS transistor. Wherein, the one end of first resistance is connected with terminal equipment's external power supply input end, the other end of first resistance respectively with the one end of second resistance R2 and the gate of first PMOS transistor is connected, the other end ground connection of second resistance, the source electrode of first PMOS transistor respectively with terminal equipment's external power supply input end and the source electrode of second PMOS transistor is connected, the drain electrode of first PMOS transistor respectively with the one end of third resistance and the gate of second PMOS transistor is connected, the other end ground connection of third resistance.
According to the scheme, when the amplitude of a signal input through the external power supply input end of the terminal equipment is larger than or equal to a set threshold value, the voltage at two ends of the second resistor is larger than or equal to the starting voltage of the first PMOS transistor, the first PMOS transistor is conducted, so that the voltage between the grid electrode of the second PMOS transistor and the source electrode of the second PMOS transistor is zero, the second PMOS transistor is in a turn-off state, so that the signal input through the external power supply input end of the terminal equipment cannot enter other components connected with the second PMOS transistor, and further the signal with the larger amplitude and input through the external power supply input end of the terminal equipment can be prevented from damaging other components; when the amplitude of the signal input through the external power supply input end of the terminal device is smaller than the set threshold, the voltage at two ends of the second resistor is smaller than the starting voltage of the first PMOS transistor, the first PMOS transistor is cut off, so that the voltage between the grid electrode of the second PMOS transistor and the source electrode of the second PMOS transistor is larger than or equal to that of the second PMOS transistor, and the second PMOS transistor is in a conducting state, so that the signal input through the external power supply input end of the terminal device can normally enter other components connected with the second PMOS transistor to supply power or charge. The threshold setting unit is configured to set a threshold value according to a resistance value of the first resistor, a resistance value of the second resistor, and a turn-on voltage of the first PMOS transistor, where the turn-on voltage of the first PMOS transistor is a minimum voltage between a gate of the first PMOS transistor and a source of the first PMOS transistor when the first PMOS transistor Q1 is turned on, the turn-on voltage of the second PMOS transistor is a minimum voltage between a gate of the second PMOS transistor and a source of the second PMOS transistor when the second PMOS transistor Q2 is turned on, and the set threshold value is determined according to the resistance value of the first resistor, the resistance value of the second resistor, and the turn-on voltage of the first PMOS transistor.
That is to say, the protection circuit realizes the function of the OVP chip through discrete devices, can prevent the damage to other components connected with the protection circuit through signals with larger amplitude input by the external power input end of the terminal equipment, and has lower cost compared with the OVP chip. In addition, the PMOS transistor is a voltage-controlled component, so that the control precision is high, the power consumption is low, and the control precision and the power consumption of the protection circuit are low.
In a possible implementation manner, the protection circuit further includes a capacitor, one end of the capacitor is connected to the source of the second PMOS transistor, and the other end of the capacitor is connected to the gate of the second PMOS transistor, so as to reduce a parasitic capacitance between the source of the second PMOS transistor and the gate of the second PMOS transistor, and further improve a response speed of the second PMOS transistor.
In a third aspect, the present application provides a terminal device, where the terminal device includes the protection apparatus in any one of the embodiments of the first aspect.
In a fourth aspect, the present application provides a terminal device, where the terminal device includes the protection circuit in any one of the embodiments of the second aspect.
Drawings
FIG. 1 is a schematic diagram of a PMOS transistor;
fig. 2 is a schematic structural diagram of a protection device according to an embodiment of the present disclosure;
fig. 3 is a schematic structural diagram of a transient suppression module in a protection device according to an embodiment of the present disclosure;
fig. 4 is a second schematic structural diagram of a transient suppression module in a protection device according to an embodiment of the present disclosure;
fig. 5 is a schematic structural diagram of a control module in a protection device according to an embodiment of the present disclosure;
fig. 6 is a schematic structural diagram of a switch module in a protection device according to an embodiment of the present disclosure;
fig. 7 is a second schematic structural diagram of a switch module in a protection device according to an embodiment of the present disclosure;
fig. 8 is a schematic structural diagram of a protection device according to an embodiment of the present disclosure;
fig. 9 is a schematic structural diagram of a protection circuit according to an embodiment of the present disclosure;
fig. 10 is a schematic structural diagram of another protection circuit provided in the embodiment of the present application.
Detailed Description
In order to prevent the damage to the electronic equipment caused by surge signals generated by the voltage fluctuation of the power grid on a charging path or a power supply path of the electronic equipment in the process of charging the electronic equipment by using the power grid or supplying power by using the power grid, an OVP chip is adopted in the prior art to protect the electronic equipment. However, compared with the duration of the surge signal, the OVP chip has a slow response speed, so that the chip has a weak anti-surge capability, and the electronic device cannot be effectively protected.
In order to solve the problems in the prior art, the application provides a protection device, a protection circuit and a terminal device, so that the anti-surge capacity of the terminal device is improved.
In the following, the basic concept related to the present application is explained. It should be noted that these explanations are intended to make the present application more understandable, and should not be construed as limiting the scope of protection claimed in the present application.
(1) The surge signal refers to a current signal or a voltage signal which is instantaneously generated in the circuit and exceeds a stable value. The time for generating the surge signal is very short, and the amplitude of the surge voltage (or surge current) exceeds more than twice of the normal value. The cause of the surge (transient pulse) is mainly fluctuations in the grid voltage.
(2) Static electricity is usually formed by the redistribution of charges due to friction, and also by the mutual attraction of charges. The electric charges are classified into positive charges and negative charges, that is, static electricity is also classified into positive static electricity and negative static electricity. When positive charges are accumulated on an object, positive static electricity is formed, and when negative charges are accumulated on an object, negative static electricity is formed, but whether the positive static electricity or the negative static electricity, when an electrostatically charged object contacts a zero potential object (grounded object) or an object having a potential difference with the zero potential object, charge transfer occurs, and an electrostatic discharge (ESD) phenomenon occurs.
(3) A Transient Voltage Supply (TVS) diode is a high-efficiency circuit protection device, and has extremely fast response time (in the order of subnanosecond) and high surge absorption capability. When two ends of the TVS diode are subjected to instant high-energy impact (the voltage of the two ends of the TVS diode is higher than the breakdown voltage of the TVS diode), the TVS diode can change the impedance value between the two ends from high impedance to low impedance at a very high speed so as to absorb an instant large current and clamp the voltage of the two ends of the TVS diode at a safe value, thereby protecting the following circuit elements from the impact of transient high-voltage spike pulse.
(4) As shown in fig. 1, an internal structural schematic diagram of a P-channel metal oxide semiconductor (PMOS) transistor may include two regions formed by P-type semiconductors on an N (negative) type silicon substrate, which are respectively used as a source (S) and a drain (D), the two electrodes are not conducted, and when a sufficient voltage is applied between the source and the source, an N-type silicon surface under a gate (gate, G) presents a P-type inversion layer and becomes a channel connecting the source and the drain, so that the PMOS transistor is in a conducting state.
In addition, it is to be understood that the terms first, second, etc. in the description of the present application are used for distinguishing between the descriptions and not necessarily for describing a sequential or chronological order.
In order to make the objects, technical solutions and advantages of the present application more clear, the present application will be further described in detail with reference to the accompanying drawings.
The embodiment of the application provides a protection device, which is used for protecting a connecting element on a charging path or a power supply path of terminal equipment under the scene that the terminal equipment is charged through a power grid or is supplied with power through the power grid. Referring to fig. 2, the apparatus 200 includes a TVS module 201, a control module 202, and a switch module 203, wherein an input terminal of the TVS module 201 is connected to an external power input terminal of a terminal device, an output terminal of the TVS module 201 is grounded, an input terminal of the control module 202 is connected to the external power input terminal of the terminal device, and an input terminal of the switch module 203 is respectively connected to the external power input terminal of the terminal device and an output terminal of the control module 202. Wherein, the terminal device includes but is not limited to any one of the following: electronic equipment such as mobile phones, computers, tablet computers and televisions with requirements on surge and voltage resistance.
The TVS module 201 is configured to absorb a second electrical signal from the first electrical signal and output a third electrical signal to the control module; the first electrical signal is an electrical signal input from an external power supply input end of terminal equipment, the amplitude of the second electrical signal is larger than a first threshold, and the third signal is a signal of the first signal except the second signal absorbed by the TVS module.
The control module 202 is configured to output a first control signal to the switch module when the amplitude of the third electrical signal is greater than or equal to a second threshold, and output a second control signal to the switch module when the amplitude of the third electrical signal is smaller than the second threshold; the first control signal is used for controlling the switch module to be in an off state, and the second control signal is used for controlling the switch module to be in a closed state.
The switch module 203 is configured to be in an off state under the control of the first control signal, or in a closed state under the control of the second control signal.
In a possible embodiment, the TVS module 201 is a TVS diode D1, one end of the TVS diode D1 is connected to an external power input terminal of the terminal device, and the other end of the TVS diode D1 is grounded, wherein the first threshold is a breakdown voltage of the TVS diode D1, as shown in fig. 3, the TVS diode D1 in fig. 3 is a packaged TVS diode D1, VBUS/DC is an input terminal of the TVS diode D1, NC1-NC3 are floating input terminals, and GND1-GND4 are ground terminals.
The TVS diode D1 may be a unidirectional TVS diode or a bidirectional TVS diode.
When the amplitude of the first signal input from the external power input terminal of the terminal device is greater than the breakdown voltage of the TVS diode D1, that is, when the amplitude of the first signal is greater than the first threshold, the impedance of the TVS diode is rapidly decreased, and the second signal of the first signal is introduced to the ground terminal to absorb the second signal.
When the first signal input by the external power input terminal of the terminal device includes an overvoltage signal (or an overcurrent signal) caused by static electricity, the duration of the overvoltage signal (or the overcurrent signal) is very short compared to a normal surge signal, and the response duration of the TVS diode is long compared to the duration of the overvoltage signal (or the overcurrent signal), so that the TVS diode has no time to absorb the overvoltage signal (or the overcurrent signal). In order to solve the above problem and further improve the surge protection capability of the protection device 200, in a possible embodiment, the TVS module 201 may further include a first capacitor C1 in addition to the TVS diode D1, and the first capacitor C1 is connected in parallel with the TVS diode, as shown in fig. 4, and the overvoltage signal (or the overcurrent signal) is quickly responded to and absorbed by the first capacitor C1. The capacitance value of the first capacitor C1 may be 100nF, but other values may be selected according to the implementation environment.
In one possible embodiment, the control module 202 may include a first resistor R1, a second resistor R2, and a first PMOS transistor Q1, wherein one end of the first resistor R1 is connected to the external power input of the terminal device, the other end of the first resistor R1 is connected to one end of the second resistor R2 and the gate of the first PMOS transistor Q1, the other end of the second resistor R2 is grounded, the source of the first PMOS transistor Q1 is connected to the external power input of the terminal device, and the drain of the first PMOS transistor Q1 is connected to the input of the switch module 203, as shown in fig. 5. At this time, the second threshold may be determined according to a resistance value of the first resistor, a resistance value of the second resistor, and a turn-on voltage of the first PMOS transistor, where the turn-on voltage of the first PMOS transistor is a minimum voltage V between a gate of the first PMOS transistor and a source of the first PMOS transistor when the first PMOS transistor is turned ongs1。
Specifically, when the amplitude of the third signal output by the TVS module 201 is greater than or equal to the second threshold, the voltage across the second resistor R2 is greater than or equal to Vgs1The first PMOS transistor Q1 is turned on, and outputs the first control signal to the switch module 203, so as to control the switch module to be in an off state, so that the third signal cannot enter other components connected to the output terminal of the switch module 203, and the third signal is prevented from damaging other components; when the amplitude of the third signal output by the TVS module 201 is smaller than the second threshold, the voltage across the second resistor R2 is smaller than Vgs1The first PMOS transistor Q1 is turned off, and outputs the second control signal to the switch module 203, that is, the amplitude of the second signal is 0, and the switch module is controlled to be in a closed state, so that the third signal can normally enter other components connected to the output end of the switch module 203 to supply power or charge.
In one possible implementation, the switch module 203 includes a second PMOS transistor Q2 and a third resistor R3; one end of the third resistor R3 is connected to the output terminal of the control module 202 and the gate of the second PMOS transistor, the other end of the third resistor R3 is grounded, and the source of the second PMOS transistor Q2 is connected to the external power input terminal of the terminal device, as shown in fig. 6.
Specifically, when the third signal output by the TVS module 201 is greater than or equal to the second threshold, the control module 202 outputs the first control signal to the switch module 203 such that the voltage between the gate of the second PMOS transistor Q2 and the source of the second PMOS transistor Q2 is less than the turn-on voltage V of the second transistorgs2Controlling the second PMOS transistor Q2 to be in an off state, so that the third signal cannot enter other components connected to the output end of the switch module, and preventing the third signal from damaging other components; when the third signal output by the TVS module 201 is less than the second threshold, the control module 202 outputs the second control signal to the switch module 203 such that the voltage between the gate of the second PMOS transistor Q2 and the source of the second PMOS transistor Q2 is greater than or equal to the Vgs2And controlling the second PMOS transistor Q2 to be in a closed state, so that the third signal can normally enter other components connected to the output end of the switch module to supply power or charge, wherein V isgs2Is the minimum voltage between the gate of the second PMOS transistor and the source of the second PMOS transistor when the second PMOS transistor Q2 is on.
In one possible embodiment, the switch module 203 may further include a second capacitor C2, one end of the second capacitor C2 is connected to the source of the second PMOS transistor Q2, and the other end of the second capacitor C2 is connected to the gate of the second PMOS transistor Q2, as shown in fig. 7, so as to reduce the parasitic capacitance between the source of the second PMOS transistor Q2 and the gate of the second PMOS transistor Q2, and thus, the response speed of the second PMOS transistor Q2 may be increased.
In one possible embodiment, when the control module 202 includes the first resistor R1, the second resistor R2 and the first PMOS transistor Q1, and the switch module 203 includes the second PMOS transistor Q2 and the third resistor R3, the connection relationship between the first PMOS transistor Q1 in the control module 202 and the second PMOS transistor Q2 and the third resistor R3 in the switch module 203 is shown in fig. 8, which is exemplified by the TVS module 201 including a TVS diode D1 and a first capacitor C1 in fig. 8. One end of the third resistor R3 is connected to the drain of the first PMOS transistor Q1 and the gate of the second PMOS transistor Q2, respectively, the other end of the third resistor R3 is grounded, and the source of the second PMOS transistor Q2 is connected to the source of the first PMOS transistor.
Specifically, when the third signal output by the TVS module 201 is greater than or equal to the second threshold, the voltage across the second resistor R2 is greater than or equal to Vgs1The first PMOS transistor Q1 is turned on, so that the voltage between the gate of the second PMOS transistor Q2 and the source of the second PMOS transistor Q2 is zero, and the second PMOS transistor Q2 is in an off state, so that the third signal cannot enter other components connected to the drain of the second PMOS transistor Q2, and the third signal is prevented from damaging other components connected to the drain of the second PMOS transistor Q2; when the third signal output by the TVS module 201 is smaller than the second threshold, the voltage across the second resistor R2 is smaller than Vgs1The first PMOS transistor Q1 is turned off such that the voltage between the gate of the second PMOS transistor Q2 and the source of the second PMOS transistor Q2 is greater than or equal to the Vgs2The second PMOS transistor Q2 is in a conducting state, so that the third signal can normally enter the other components connected to the drain of the second PMOS transistor Q2 for power supply or charging.
In one embodiment, the resistance of the first resistor R1 may be 100K Ω, the resistance of the second resistor R2 may be 470K Ω, the resistance of the third resistor R3 may be 470K Ω, the capacitance of the second capacitor C2 may be 100nF, and the withstand voltage V between the drain of the first PMOS transistor Q1 and the source of the first PMOS transistor Q1ds1Can be used forA withstand voltage between the gate of the first PMOS transistor Q1 and the source of the first PMOS transistor Q1 is + -20V, -30V, a withstand voltage between the drain of the second PMOS transistor Q2 and the source of the second PMOS transistor Q2 is Vds2May be-30V, and a withstand voltage between the gate of the second PMOS transistor Q2 and the source of the second PMOS transistor Q2 may be ± 20V. In addition, the current capacity of the second PMOS transistor Q2 as a switch of the whole path needs to be larger than the maximum input current allowed by the terminal device, although the above device parameter values are only examples, other device parameter values may be selected according to the specific implementation of the present application, that is, the embodiments of the present application do not limit the specific parameters of the first resistor R1, the second resistor R2, the third resistor R3, the first PMOS transistor Q1, the second PMOS transistor Q2, the first capacitor C1, and the second capacitor C2, and the above specific parameters are only examples. In a specific implementation, specific parameters of the first resistor R1, the second resistor R2, the third resistor R3, the first PMOS transistor Q1, the second PMOS transistor Q2, the first capacitor C1, and the second capacitor C2 may be selected according to the type and cost of the device to be protected by the protection apparatus.
In the embodiment of the application, the TVS module in the protection device can absorb a second signal with an amplitude greater than a first threshold value in a first signal input through an external power input terminal of the terminal device, reduce a signal with a larger amplitude in the first signal, and the control module can control the working state of the switch module according to the amplitude of a third signal output by the TVS module after absorbing the second signal and a second threshold value, controlling the switch module to be in an off state when the amplitude of the third electrical signal is greater than or equal to a second threshold value, controlling the switch module to be in a closed state when the amplitude of the third electrical signal is less than the second threshold value, so that a third signal having a magnitude not exceeding the second threshold can be input to a subsequent component through the switch module, the damage of the signal with the amplitude exceeding the safety value to subsequent components connected with the switch module can be further prevented. Namely, the control module and the switch module can further protect the subsequent components connected with the switch module under the condition that the TVS module cannot completely absorb the second signal or cannot absorb the second signal in time, and compared with the prior art, the surge prevention capability of the terminal equipment can be improved.
The embodiment of the application further provides a protection circuit, which is used for protecting a connecting element on a charging path or a power supply path of the terminal equipment in a scene that the terminal equipment is charged through a power grid or is powered through the power grid. Referring to fig. 9, the circuit includes a first resistor R1, a second resistor R2, a third resistor R3, a first PMOS transistor Q1, and a second PMOS transistor Q2. Wherein the content of the first and second substances,
one end of the first resistor R1 is connected with an external power supply input end of the terminal equipment, the other end of the first resistor R1 is respectively connected with one end of the second resistor R2 and the grid of the first PMOS transistor Q1, the other end of the second resistor R2 is grounded, the source of the first PMOS transistor Q1 is respectively connected with the external power supply input end of the terminal equipment and the source of the second PMOS transistor Q2, the drain of the first PMOS transistor is respectively connected with one end of the third resistor and the grid of the second PMOS transistor Q2, the other end of the third resistor R3 is grounded, and the drain of the second PMOS transistor Q2 is the output end of the protection circuit and used for connecting other components and parts needing protection in the terminal equipment.
Specifically, when the amplitude of the signal input through the external power input end of the terminal device is greater than or equal to a set threshold, the voltage across the second resistor is greater than or equal to the turn-on voltage V of the first PMOS transistorgs1The first PMOS transistor Q1 is turned on, so that the voltage between the gate of the second PMOS transistor Q2 and the source of the second PMOS transistor Q2 is zero, and the second PMOS transistor Q2 is turned off, so that a signal input through the external power input terminal of the terminal device cannot enter other components connected to the second PMOS transistor, thereby preventing external power from passing through the terminal deviceSignals with larger amplitude input by the source input end damage other components; when the amplitude of the signal input through the external power supply input end of the terminal equipment is smaller than the set threshold, the voltage at two ends of the second resistor is smaller than Vgs1The first PMOS transistor Q1 is turned off such that the voltage between the gate of the second PMOS transistor Q2 and the source of the second PMOS transistor Q2 is greater than or equal to the turn-on voltage V of the second PMOS transistorgs2The second PMOS transistor Q2 is in a conducting state, so that a signal input through the external power input terminal of the terminal device can normally enter other components connected with the second PMOS transistor Q2 for power supply or charging. Wherein, the Vgs1The V is the minimum voltage between the gate of the first PMOS transistor and the source of the first PMOS transistor when the first PMOS transistor Q1 is turned ongs2When the second PMOS transistor Q2 is turned on, the set threshold is the minimum voltage between the gate of the second PMOS transistor and the source of the second PMOS transistor, and the set threshold is determined according to the resistance of the first resistor, the resistance of the second resistor and the Vgs1And (4) determining.
That is to say, the protection circuit realizes the function of the OVP chip through discrete devices, can prevent the damage to other components connected with the protection circuit through signals with larger amplitude input by the external power input end of the terminal equipment, and has lower cost compared with the OVP chip. In addition, the PMOS transistor is a voltage-controlled component, so that the control precision is high, the power consumption is low, and the control precision and the power consumption of the protection circuit are low.
Wherein, the terminal device includes but is not limited to any one of the following: electronic equipment such as mobile phones, computers, tablet computers and televisions with requirements on surge prevention and voltage resistance.
In one embodiment, the first resistor R1 may have a resistance of 100K Ω, the second resistor R2 may have a resistance of 470K Ω, the third resistor R3 may have a resistance of 470K Ω, and the drain of the first PMOS transistor Q1 and the source of the first PMOS transistor Q1 may be connected to each otherVoltage V ofds1May be-30V, a withstand voltage between the gate of the first PMOS transistor Q1 and the source of the first PMOS transistor Q1 is 20V, and a voltage V between the drain of the second PMOS transistor Q2 and the source of the second PMOS transistor Q2 is-ds2May be-30V, and the withstand voltage between the gate of the second PMOS transistor Q2 and the source of the second PMOS transistor Q2 is ± 20V. In addition, the second PMOS transistor Q2 acts as a switch for the entire path, whose current capacity needs to be larger than the maximum input current allowed by the terminal device.
In a possible embodiment, the protection circuit further includes a capacitor C, one end of the capacitor C is connected to the source of the second PMOS transistor Q2, and the other end of the capacitor C is connected to the gate of the second PMOS transistor Q2, as shown in fig. 10, so as to reduce the parasitic capacitance between the source of the second PMOS transistor Q2 and the gate of the second PMOS transistor Q2, and further, the response speed of the second PMOS transistor Q2 can be improved. The capacitance value of the capacitor C may be 100nF, but other values may be selected according to the implementation environment.
It should be noted that, in the embodiments of the present application, specific parameters of the first resistor R1, the second resistor R2, the third resistor R3, the first PMOS transistor Q1, the second PMOS transistor Q2, and the capacitor are not limited, and the specific parameters are only for example. In a specific implementation, specific parameters of the first resistor R1, the second resistor R2, the third resistor R3, the first PMOS transistor Q1, the second PMOS transistor Q2 and the capacitor C may be selected according to the type of the device to be protected by the protection device, the cost, and other factors.
It will be apparent to those skilled in the art that various changes and modifications may be made in the embodiments of the present application without departing from the spirit and scope of the embodiments of the present application. Thus, if such modifications and variations of the embodiments of the present application fall within the scope of the claims of the present application and their equivalents, the present application is also intended to encompass such modifications and variations.

Claims (11)

1. A protective device, comprising: the transient suppression TVS module, the control module and the switch module; the input end of the TVS module is connected with the external power supply input end of the terminal equipment, the output end of the TVS module is grounded, the input end of the control module is connected with the external power supply input end of the terminal equipment, and the input end of the switch module is respectively connected with the external power supply input end of the terminal equipment and the output end of the control module;
the TVS module is used for absorbing a second electric signal from the first electric signal and outputting a third electric signal to the control module; the first electrical signal is an electrical signal input from an external power supply input end of terminal equipment, the amplitude of the second electrical signal is greater than a first threshold, and the third signal is a signal of the first signal except the second signal absorbed by the TVS module;
the control module is used for outputting a first control signal to the switch module when the amplitude of the third electric signal is greater than or equal to a second threshold value, and outputting a second control signal to the switch module when the amplitude of the third electric signal is less than the second threshold value; the first control signal is used for controlling the switch module to be in an off state, and the second control signal is used for controlling the switch module to be in a closed state;
the switch module is used for being in a turn-off state under the control of the first control signal or being in a turn-on state under the control of the second control signal.
2. The apparatus of claim 1, wherein the TVS module is a TVS diode, one end of the TVS diode is connected to an external power input of the terminal device, and the other end of the TVS diode is grounded;
the first threshold is a breakdown voltage of the TVS diode.
3. The apparatus of claim 2, the TVS module further comprising a first capacitor connected in parallel with the TVS diode.
4. The apparatus of any of claims 1-3, wherein the control module comprises a first resistor, a second resistor, and a first P-channel Metal Oxide Semiconductor (MOS) transistor; one end of the first resistor is connected with an external power supply input end of the terminal device, the other end of the first resistor is respectively connected with one end of the second resistor and a grid electrode of the first PMOS transistor, the other end of the second resistor is grounded, a source electrode of the first PMOS transistor is connected with the external power supply input end of the terminal device, and a drain electrode of the first PMOS transistor is connected with an input end of the switch module;
the second threshold is determined according to the resistance value of the first resistor, the resistance value of the second resistor and the starting voltage of the first PMOS transistor, and the starting voltage of the first PMOS transistor is the minimum voltage between the grid electrode of the first PMOS transistor and the source electrode of the first PMOS transistor when the first PMOS transistor is conducted.
5. The apparatus of claim 4, the switch module comprising a second PMOS transistor and a third resistor;
one end of the third resistor is connected with the drain electrode of the first PMOS transistor and the grid electrode of the second PMOS transistor respectively, the other end of the third resistor is grounded, and the source electrode of the second PMOS transistor is connected with the source electrode of the first PMOS transistor.
6. The apparatus of any of claims 1-4, wherein the switch module comprises a second PMOS transistor and a third resistor;
one end of the third resistor is connected with the output end of the control module and the grid electrode of the second PMOS transistor respectively, the other end of the third resistor is grounded, and the source electrode of the second PMOS transistor is connected with the external power supply input end of the terminal device.
7. The apparatus of claim 5 or 6, wherein the switch module further comprises a second capacitor, one end of the second capacitor being connected to the source of the second PMOS transistor, the other end of the second capacitor being connected to the gate of the second PMOS transistor.
8. The protection circuit is characterized by comprising a first resistor, a second resistor, a third resistor, a first P-channel Metal Oxide Semiconductor (MOS) transistor and a second PMOS transistor;
wherein, the one end of first resistance is connected with terminal equipment's external power supply input end, the other end of first resistance respectively with the one end of second resistance and the grid of first PMOS transistor is connected, the other end ground connection of second resistance, the source electrode of first PMOS transistor respectively with terminal equipment's external power supply input end and the source electrode of second PMOS transistor is connected, the drain electrode of first PMOS transistor respectively with the one end of third resistance and the grid of second PMOS transistor is connected, the other end ground connection of third resistance.
9. The circuit of claim 8, further comprising a capacitor, one end of the capacitor being connected to the source of the second PMOS transistor, the other end of the capacitor being connected to the gate of the second PMOS transistor.
10. A terminal device, characterized in that it comprises a protection device according to any one of claims 1 to 7.
11. A terminal device, characterized in that it comprises a protection circuit according to claim 8 or 9.
CN201810621645.5A 2018-06-15 2018-06-15 Protection device, protection circuit and terminal equipment Pending CN110611301A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
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Application Number Priority Date Filing Date Title
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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN202651773U (en) * 2012-07-06 2013-01-02 南京志卓电子科技有限公司 Overvoltage protection device of direct current adapter
CN204333904U (en) * 2014-12-30 2015-05-13 环维电子(上海)有限公司 A kind of overvoltage crowbar
CN206226002U (en) * 2016-11-30 2017-06-06 电子科技大学中山学院 Surge current suppression circuit applied to ALD (atomic layer deposition) equipment
CN107230965A (en) * 2017-08-07 2017-10-03 东莞博力威电池有限公司 Port multi-level protection circuit
CN206595713U (en) * 2017-03-28 2017-10-27 深圳豪成通讯科技有限公司 A kind of surge protection circuit

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN202651773U (en) * 2012-07-06 2013-01-02 南京志卓电子科技有限公司 Overvoltage protection device of direct current adapter
CN204333904U (en) * 2014-12-30 2015-05-13 环维电子(上海)有限公司 A kind of overvoltage crowbar
CN206226002U (en) * 2016-11-30 2017-06-06 电子科技大学中山学院 Surge current suppression circuit applied to ALD (atomic layer deposition) equipment
CN206595713U (en) * 2017-03-28 2017-10-27 深圳豪成通讯科技有限公司 A kind of surge protection circuit
CN107230965A (en) * 2017-08-07 2017-10-03 东莞博力威电池有限公司 Port multi-level protection circuit

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Application publication date: 20191224