CN110610927A - Multi-chip packaging interconnection structure - Google Patents
Multi-chip packaging interconnection structure Download PDFInfo
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- CN110610927A CN110610927A CN201910710165.0A CN201910710165A CN110610927A CN 110610927 A CN110610927 A CN 110610927A CN 201910710165 A CN201910710165 A CN 201910710165A CN 110610927 A CN110610927 A CN 110610927A
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- Prior art keywords
- double
- temperature
- fired ceramic
- low
- positioning holes
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0652—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next and on each other, i.e. mixed assemblies
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0296—Conductive pattern lay-out details not covered by sub groups H05K1/02 - H05K1/0295
- H05K1/0298—Multilayer circuits
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
Abstract
The invention discloses a multi-chip packaging interconnection structure which comprises a shell, a mother board, an upper cover, a chip packaging assembly and BGA balls, wherein the chip packaging assembly is installed in the shell, the upper cover is arranged above the chip packaging assembly, and the upper cover and the shell are welded and fixed. According to the invention, the chip packaging assembly is arranged into three layers, namely an upper layer for mounting a control circuit, a middle layer for wiring and a bottom layer for mounting a power circuit, the power circuit and the control circuit are wired separately, interference of electromagnetic waves generated by the power circuit on the control circuit is prevented, meanwhile, a three-dimensional wiring mode is adopted, interconnection among multiple chips is realized, the three-dimensional wiring mode reduces the utilization of the chip on the surface area of a circuit board, so that more spaces are formed on the circuit board for arranging electronic components, the layers are connected through fuzz buttons, the fuzz buttons shrink when being pressed in the length direction, and are restored after the pressure is eliminated, so that the interconnected structure is prevented from being damaged due to external pressure.
Description
Technical Field
The invention relates to the technical field of chip packaging, in particular to a multi-chip packaging interconnection structure.
Background
The chip package is a shell for mounting semiconductor integrated circuit chip, and can be used for placing, fixing, sealing, protecting chip and raising electrothermal performance, and is also a bridge for communicating chip internal world with external circuit, and the contact point on the chip is connected with pin of package shell by means of wire, and these pins are connected with other devices by means of wire on the printed circuit board, so that the package can be used for making CPU and other LSI integrated circuits play important role.
Disclosure of Invention
The present invention is directed to solving, at least to some extent, one of the technical problems in the related art. Therefore, one objective of the present invention is to provide an interconnection structure for multi-chip package, which realizes interconnection between multiple chips, and reduces the surface area of a circuit board occupied by the chips in a three-dimensional wiring manner.
The multi-chip packaging interconnection structure comprises a shell, a mother board, an upper cover, a chip packaging assembly and BGA balls, wherein the chip packaging assembly is installed inside the shell, the upper cover is arranged above the chip packaging assembly and is fixedly welded with the shell, the mother board is installed at the lower end of the shell, the BGA balls are further arranged between the mother board and the shell, and the BGA balls are fixed with the shell.
Preferably, the chip package assembly includes an upper layer for mounting a control circuit, a middle layer for wiring, and a bottom layer for mounting a power circuit, wherein the upper layer is electrically connected to the middle layer, and the middle layer is electrically connected to the bottom layer.
Preferably, the upper layer internally mounted has a first double-sided substrate, the middle layer internally mounted has a second double-sided substrate, the bottom layer internally mounted has a third double-sided substrate, electronic components on first double-sided substrate, second double-sided substrate, the third double-sided substrate pass through the pad and distribute the copper wire electrical signal connection inside.
Preferably, the upper layer and the middle layer are connected through a fuzz button electrical signal, and the middle layer and the bottom layer are connected through a fuzz button electrical signal.
Preferably, the electric signal that the hair button transmitted is radio frequency signal, and the hair button adopts the four-wire structure, the four-wire structure includes that the hair button of a set of transmission radio frequency signal in middle part and three group's hair buttons of being connected with the ground wire on every side, and three group's hair buttons on every side constitute shielding ground structure.
Preferably, the double-sided substrate is a double-sided cavity low-temperature co-fired ceramic multilayer circuit substrate.
Preferably, the method for processing the double-sided substrate utilizes a laminated board with positioning pins at four corners, and comprises the following steps:
s1: placing stainless steel sheets with positioning holes at four corners on the laminated board, and ensuring that the positioning holes of the stainless steel sheets are sleeved on the positioning pin nails in a one-to-one correspondence manner;
s2: placing a polyester film on the stainless steel sheet in step S1;
s3: placing the low-temperature co-fired ceramic sheets with the positioning holes at four corners on the polyester film in the step S2, and ensuring that the positioning holes of the low-temperature co-fired ceramic sheets are sleeved on the positioning pin nails in a one-to-one correspondence manner;
s4: placing the other low-temperature co-fired ceramic wafer with positioning holes at four corners on the low-temperature co-fired ceramic wafer in the previous step, and ensuring that the positioning holes of the low-temperature co-fired ceramic wafer are sleeved on the positioning pin nails in a one-to-one correspondence manner;
s5: pressing through a tablet press;
s6: repeating the steps S4 and S5, and laminating the remaining low-temperature co-fired ceramic sheets with the positioning holes at four corners one by one in sequence;
s7: after the lamination of all the low-temperature co-fired ceramic sheets is finished, placing a layer of polyester film on the upper part of the last laminated low-temperature co-fired ceramic sheet;
s8: and (5) placing a stainless steel sheet with positioning holes at four corners on the polyester film in the step S7, ensuring that the positioning holes of the stainless steel sheet are sleeved on the positioning pin nails in a one-to-one correspondence manner, and performing pressing through a tablet press.
Preferably, lamination glue is uniformly coated on the periphery of the stainless steel sheet and the periphery of the low-temperature co-fired ceramic sheet.
According to the invention, the chip packaging assembly is arranged into three layers, namely an upper layer for mounting a control circuit, a middle layer for wiring and a bottom layer for mounting a power circuit, the power circuit and the control circuit are wired separately, interference of electromagnetic waves generated by the power circuit on the control circuit is prevented, meanwhile, a three-dimensional wiring mode is adopted, interconnection among multiple chips is realized, the three-dimensional wiring mode reduces the utilization of the chip on the surface area of a circuit board, so that more spaces are formed on the circuit board for arranging electronic components, the layers are connected through fuzz buttons, the fuzz buttons shrink when being pressed in the length direction, and the fuzz buttons are restored after the pressure is eliminated, so that the interconnected structure is prevented from being damaged due to external pressure.
Drawings
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the principles of the invention and not to limit the invention. In the drawings:
FIG. 1 is a schematic structural diagram of a multi-chip package interconnection structure according to the present invention;
fig. 2 is an assembly view of a semiconductor package assembly according to the present invention;
fig. 3 is a schematic structural diagram of a semiconductor package assembly according to the present invention;
FIG. 4 is a schematic structural diagram of a double-sided substrate according to the present invention;
fig. 5 is a schematic view of a connection structure between layers of the semiconductor package according to the present invention.
In the figure: 1-shell, 2-motherboard, 3-upper cover, 4-chip package assembly, 5-BGA ball, 41-upper layer, 42-middle layer, 43-bottom layer, 441-first double-sided substrate, 442-second double-sided substrate, 443-third double-sided substrate, 44-double-sided substrate, 45-hair button.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments.
Examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to the same or similar elements or elements having the same or similar function throughout. The embodiments described below with reference to the drawings are illustrative and intended to be illustrative of the invention and are not to be construed as limiting the invention.
In the description of the present invention, it is to be understood that the terms "central," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," "circumferential," and the like are used in the orientations and positional relationships indicated in the drawings for convenience in describing the invention and to simplify the description, and are not intended to indicate or imply that the referenced devices or elements must have a particular orientation, be constructed and operated in a particular orientation, and are therefore not to be considered limiting of the invention.
Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present invention, "a plurality" means two or more unless specifically defined otherwise.
In the present invention, unless otherwise expressly stated or limited, the terms "mounted," "connected," "secured," and the like are to be construed broadly and can, for example, be fixedly connected, detachably connected, or integrally formed; can be mechanically or electrically connected; either directly or indirectly through intervening media, either internally or in any other relationship. The specific meanings of the above terms in the present invention can be understood by those skilled in the art according to specific situations.
Referring to fig. 1-5, a multi-chip package interconnection structure comprises a housing 1, a motherboard 2, an upper cover 3, a chip package assembly 4 and BGA balls 5, wherein the chip package assembly 4 is installed inside the housing 1, the upper cover 3 is arranged above the chip package assembly 4, the upper cover 3 is welded and fixed with the housing 1, the motherboard 2 is installed at the lower end of the housing 1, the BGA balls 5 are also arranged between the motherboard 2 and the housing 1, and the BGA balls 5 are fixed with the housing 1; the chip packaging assembly comprises an upper layer 41 for mounting a control circuit, a middle layer 42 for wiring and a bottom layer 43 for mounting a power circuit, wherein the upper layer 41 is electrically connected with the middle layer 42, and the middle layer 42 is electrically connected with the bottom layer 43; a first double-sided substrate 441 is mounted in the upper layer 41, a second double-sided substrate 442 is mounted in the middle layer 42, a third double-sided substrate 443 is mounted in the bottom layer 43, and electronic components on the first double-sided substrate 441, the second double-sided substrate 442 and the third double-sided substrate 443 are electrically connected through bonding pads and copper wires distributed in the first double-sided substrate 441, the second double-sided substrate 442 and the third double-sided substrate 443; the upper layer 41 is electrically connected with the middle layer 42 through a fuzz button 45, and the middle layer 42 is electrically connected with the bottom layer 43 through a fuzz button; the electric signals transmitted by the hair buttons 45 are radio frequency signals, the hair buttons 45 adopt a four-wire structure, the four-wire structure comprises a group of hair buttons 45 which transmit the radio frequency signals in the middle and three groups of hair buttons 45 which are connected with the ground wire at the periphery, and the three groups of hair buttons 45 at the periphery form a shielding ground structure; the double-sided substrate 44 is a double-sided cavity low-temperature co-fired ceramic multilayer circuit substrate.
Preferably, the method for processing the double-sided substrate utilizes a laminated board with positioning pins at four corners, and comprises the following steps:
s1: placing stainless steel sheets with positioning holes at four corners on the laminated board, and ensuring that the positioning holes of the stainless steel sheets are sleeved on the positioning pin nails in a one-to-one correspondence manner;
s2: placing a polyester film on the stainless steel sheet in step S1;
s3: placing the low-temperature co-fired ceramic sheets with the positioning holes at the four corners on the polyester film in the step S2, and ensuring that the positioning holes of the low-temperature co-fired ceramic sheets are sleeved on the positioning pin nails in a one-to-one correspondence manner;
s4: placing the other low-temperature co-fired ceramic wafer with positioning holes at four corners on the low-temperature co-fired ceramic wafer in the previous step, and ensuring that the positioning holes of the low-temperature co-fired ceramic wafer are sleeved on the positioning pin nails in a one-to-one correspondence manner;
s5: pressing through a tablet press;
s6: repeating the steps S4 and S5, and laminating the remaining low-temperature co-fired ceramic sheets with the positioning holes at four corners one by one in sequence;
s7: after the lamination of all the low-temperature co-fired ceramic sheets is finished, placing a layer of polyester film on the upper part of the last laminated low-temperature co-fired ceramic sheet;
s8: and (5) placing a stainless steel sheet with positioning holes at four corners on the polyester film in the step S7, ensuring that the positioning holes of the stainless steel sheet are sleeved on the positioning pin nails in a one-to-one correspondence manner, and performing pressing by using a tablet press.
Lamination glue is uniformly coated on the periphery of the stainless steel sheet and the periphery of the low-temperature co-fired ceramic sheet.
In conclusion, this multi-chip package interconnect structure is through being provided with the chip packaging subassembly, set up the chip packaging subassembly into the three-layer, be the upper strata that is used for installing control circuit respectively, the middle level that is used for the wiring, a bottom layer that is used for installing power circuit, with power circuit and control circuit wiring separation, prevent the interference of the electromagnetic wave that power circuit produced to control circuit, adopt three-dimensional wiring mode simultaneously, interconnection between the multi-chip has been realized, three-dimensional wiring mode has reduced the utilization of chip to circuit board surface area, thereby make on the circuit board have more spaces to be used for arranging electronic components, and connect through the hair button between the layer and the layer, the hair button is shrink when length direction pressurized, restore after the pressure is eliminated, prevent that external pressure from leading to the interconnect structure to be destroyed.
In the present invention, unless otherwise expressly stated or limited, the first feature "on" or "under" the second feature may be directly contacting the first and second features or indirectly contacting the first and second features through an intermediate. Also, a first feature "on," "over," and "above" a second feature may be directly or diagonally above the second feature, or may simply indicate that the first feature is at a higher level than the second feature. A first feature being "under," "below," and "beneath" a second feature may be directly under or obliquely under the first feature, or may simply mean that the first feature is at a lesser elevation than the second feature.
In the description herein, references to the description of the term "one embodiment," "some embodiments," "an example," "a specific example," or "some examples," etc., mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
The above description is only for the preferred embodiment of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art should be considered to be within the technical scope of the present invention, and the technical solutions and the inventive concepts thereof according to the present invention should be equivalent or changed within the scope of the present invention.
Claims (8)
1. A kind of multi-chip encapsulation interconnection structure, characterized by: including shell, mother board, upper cover, chip packaging subassembly, BGA ball, the shell internally mounted the chip packaging subassembly, chip packaging subassembly top sets up the upper cover, the upper cover with shell welded fastening, the installation of shell lower extreme the mother board, the mother board with still be provided with the BGA ball between the shell, the BGA ball with the shell is fixed.
2. The multi-chip package interconnect structure of claim 1, wherein: the chip packaging assembly comprises an upper layer used for mounting a control circuit, a middle layer used for wiring and a bottom layer used for mounting a power circuit, wherein the upper layer is in electrical signal connection with the middle layer, and the middle layer is in electrical signal connection with the bottom layer.
3. The multi-chip package interconnect structure of claim 2, wherein: the utility model discloses a copper wire electric signal connection that upper strata internally mounted has first double-sided base plate, middle level internally mounted has the second double-sided base plate, bottom internally mounted has the third double-sided base plate, electronic components passes through the pad and distributes inside copper wire electric signal connection on first double-sided base plate, second double-sided base plate, the third double-sided base plate.
4. The multi-chip package interconnect structure of claim 3, wherein: the upper layer is connected with the middle layer through a hair button electrical signal, and the middle layer is connected with the bottom layer through a hair button electrical signal.
5. The multi-chip package interconnect structure of claim 4, wherein: the electric signal that the hair button transmitted is radio frequency signal, and the hair button adopts the four-wire structure, the four-wire structure includes that the hair button of a set of transmission radio frequency signal in middle part and three group's hair buttons of being connected with the ground wire on every side, and three group's hair buttons on every side constitute shielding ground structure.
6. The multi-chip package interconnect structure of claim 3, wherein: the double-sided substrate adopts a double-sided cavity low-temperature co-fired ceramic multilayer circuit substrate.
7. The method for processing the double-sided substrate according to any one of claims 3 to 6, which is performed by using a laminated board with positioning pins at four corners, and is characterized by comprising the following steps:
s1: placing stainless steel sheets with positioning holes at four corners on the laminated board, and ensuring that the positioning holes of the stainless steel sheets are sleeved on the positioning pin nails in a one-to-one correspondence manner;
s2: placing a polyester film on the stainless steel sheet in step S1;
s3: placing the low-temperature co-fired ceramic sheets with the positioning holes at four corners on the polyester film in the step S2, and ensuring that the positioning holes of the low-temperature co-fired ceramic sheets are sleeved on the positioning pin nails in a one-to-one correspondence manner;
s4: placing the other low-temperature co-fired ceramic wafer with positioning holes at four corners on the low-temperature co-fired ceramic wafer in the previous step, and ensuring that the positioning holes of the low-temperature co-fired ceramic wafer are sleeved on the positioning pin nails in a one-to-one correspondence manner;
s5: pressing through a tablet press;
s6: repeating the steps S4 and S5, and laminating the remaining low-temperature co-fired ceramic sheets with the positioning holes at four corners one by one in sequence;
s7: after the lamination of all the low-temperature co-fired ceramic sheets is finished, placing a layer of polyester film on the upper part of the last laminated low-temperature co-fired ceramic sheet;
s8: and (5) placing a stainless steel sheet with positioning holes at four corners on the polyester film in the step S7, ensuring that the positioning holes of the stainless steel sheet are sleeved on the positioning pin nails in a one-to-one correspondence manner, and performing pressing through a tablet press.
8. The method of processing a double-sided substrate according to claim 7, characterized in that: and lamination glue is uniformly coated on the periphery of the stainless steel sheet and the periphery of the low-temperature co-fired ceramic chip.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910710165.0A CN110610927A (en) | 2019-08-02 | 2019-08-02 | Multi-chip packaging interconnection structure |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201910710165.0A CN110610927A (en) | 2019-08-02 | 2019-08-02 | Multi-chip packaging interconnection structure |
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| CN110610927A true CN110610927A (en) | 2019-12-24 |
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| CN201910710165.0A Pending CN110610927A (en) | 2019-08-02 | 2019-08-02 | Multi-chip packaging interconnection structure |
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| CN1166912A (en) * | 1995-03-02 | 1997-12-03 | 电路元件股份有限公司 | A low cost, high performance package for microwave circuits in the up to 90 GHZ frequency range |
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Application publication date: 20191224 |