CN110600449A - Chip packaging structure and packaging method thereof - Google Patents
Chip packaging structure and packaging method thereof Download PDFInfo
- Publication number
- CN110600449A CN110600449A CN201910907219.2A CN201910907219A CN110600449A CN 110600449 A CN110600449 A CN 110600449A CN 201910907219 A CN201910907219 A CN 201910907219A CN 110600449 A CN110600449 A CN 110600449A
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- China
- Prior art keywords
- island region
- lead
- layer
- wafers
- base island
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49503—Lead-frames or other flat leads characterised by the die pad
- H01L23/4951—Chip-on-leads or leads-on-chip techniques, i.e. inner lead fingers being used as die pad
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49517—Additional leads
- H01L23/4952—Additional leads the additional leads being a bump or a wire
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/535—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including internal interconnections, e.g. cross-under constructions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
Abstract
The invention discloses a chip packaging structure which comprises a lead frame, wherein the lead frame comprises a base island region, a plurality of annular island regions are arranged on the outer side of the base island region, and a plurality of lead terminals are arranged on the outer side of the annular island region; the top and the bottom of the base island region are respectively provided with a bracket, the middle of the base island region is provided with an insulating plate, the two wafers are respectively fixed on the brackets, the active surfaces of the wafers are oppositely arranged, and the wafers are connected with the lead terminals through lead gold wires; the base island region and the ring island region are coated with bonding layers, and a plurality of isolation metal sheets are arranged in the bonding layers at the position of the ring island region; the outside cladding of lead frame has the layer of moulding plastics, and the outside end of lead terminal is located the layer outside of moulding plastics. The invention can improve the defects of the prior art and improve the suppression of the parasitic capacitance of the laminated chip.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a chip packaging structure and a packaging method thereof.
Background
Chip packaging is a chip fabrication process that secures and protects a wafer and connects to an external circuit. The quality of the chip packaging structure directly affects the service life and performance of the chip. The existing chip packaging structure has insufficient suppression on parasitic capacitance of the laminated wafer, so that the performance of the chip is affected.
Disclosure of Invention
The technical problem to be solved by the invention is to provide a chip packaging structure and a packaging method thereof, which can solve the defects of the prior art and improve the suppression of the parasitic capacitance of a laminated chip.
In order to solve the technical problems, the technical scheme adopted by the invention is as follows.
A chip packaging structure comprises a lead frame, wherein the lead frame comprises a base island region, a plurality of annular island regions are arranged on the outer side of the base island region, and a plurality of lead terminals are arranged on the outer side of the annular island region; the top and the bottom of the base island region are respectively provided with a bracket, the middle of the base island region is provided with an insulating plate, the two wafers are respectively fixed on the brackets, the active surfaces of the wafers are oppositely arranged, and the wafers are connected with the lead terminals through lead gold wires; the base island region and the ring island region are coated with bonding layers, and a plurality of isolation metal sheets are arranged in the bonding layers at the position of the ring island region; the outside cladding of lead frame has the layer of moulding plastics, and the outside end of lead terminal is located the layer outside of moulding plastics.
Preferably, the lead gold wires are divided into a plurality of groups and respectively penetrate through the adjacent isolation metal sheets, the lead gold wires in the same group are connected with the same wafer, grounding metal sheets are respectively arranged above and below the lead gold wires, and the grounding metal sheets are connected with a grounding end in the lead terminal.
Preferably, the edge of the ring island region is uniformly provided with a tooth-shaped part, and two sides of the bottom position of the tooth-shaped part are respectively provided with an inclined plane part.
Preferably, the top surface and the bottom surface of the bonding layer are respectively provided with a plurality of blind holes, and the blind holes and the isolation metal sheets are arranged in a staggered mode.
Preferably, the inner side of the injection layer is provided with a positioning pin, the bottom of the positioning pin is fixedly connected with the bottom of the blind hole, and the side wall of the positioning pin is in clearance fit with the side wall of the blind hole.
Preferably, the inner wall of the injection molding layer is provided with a plurality of grooves, and the grooves are located in the annular island region.
A packaging method of the chip packaging structure comprises the following steps:
A. fixing the wafer on a bracket, and connecting the wafer with a lead terminal by using a lead gold wire;
B. fixedly bonding the substrate by using bonding glue to manufacture a bonding layer;
C. and manufacturing the injection molding layer by an injection molding process.
Adopt the beneficial effect that above-mentioned technical scheme brought to lie in: the invention makes two wafers oppositely fixed in the base island region by improving the structure of the lead frame, and then the two wafers are isolated by the insulating plate. The mounting mode not only can reduce the interference between two wafers, but also can reduce the loop area formed by lead gold wires, thereby playing the role of reducing parasitic capacitance. The adhesive layer is used for protecting and fixing the wafer and the lead gold wires, the isolation metal sheet is used for reducing the capacitance among different groups of lead gold wires, and the grounding metal sheet is used for quickly releasing the charges generated when parasitic capacitance is generated. The tooth-shaped part with the inclined surface part can improve the bonding firmness between the bonding layer and the lead frame, and more importantly, can release the stress on the contact surface of the bonding layer and the lead frame. The blind holes on the bonding layer are used for releasing the stress on the surface of the bonding layer and providing positioning points for the injection molding layer. The groove on the inner wall of the injection layer is used for releasing the stress between the injection layer and the bonding layer. By eliminating stress, the structural stability and the service life of the packaged chip can be effectively improved, and the influence of small change of the bonding layer structure on parasitic capacitance in the chip caused by stress accumulation is reduced.
Drawings
FIG. 1 is a block diagram of one embodiment of the present invention.
FIG. 2 is a block diagram of a foundation island region in accordance with one embodiment of the present invention.
FIG. 3 is a diagram of a ring island configuration in accordance with one embodiment of the present invention.
Fig. 4 is a sectional view taken in the direction of a-a in fig. 3.
In the figure: 1. a lead frame; 2. a base island region; 3. a ring island region; 4. a lead terminal; 5. a bracket; 6. an insulating plate; 7. a wafer; 8. a lead gold wire; 9. a bonding layer; 10. an isolation metal sheet; 11. an injection molding layer; 12. a grounding metal sheet; 13. blind holes; 14. a tooth-shaped portion; 15. an inclined plane part; 16. positioning pins; 17. and (4) a groove.
Detailed Description
The standard parts used in the invention can be purchased from the market, the special-shaped parts can be customized according to the description and the description of the attached drawings, and the specific connection mode of each part adopts the conventional means of mature bolts, rivets, welding, sticking and the like in the prior art, and the detailed description is not repeated.
Referring to fig. 1-4, a specific embodiment of the present invention includes a lead frame 1, where the lead frame 1 includes a base island region 2, a plurality of ring island regions 3 are disposed outside the base island region 2, and a plurality of lead terminals 4 are disposed outside the ring island regions 3; the top and the bottom of the base island region 2 are respectively provided with a bracket 5, the middle of the base island region 2 is provided with an insulating plate 6, two wafers 7 are respectively fixed on the brackets 5, the active surfaces of the wafers 7 are oppositely arranged, and the wafers 7 are connected with the lead terminals 4 through lead gold wires 8; the base island region 2 and the annular island region 3 are coated with bonding layers 9, and a plurality of isolation metal sheets 10 are arranged in the bonding layers 9 at the positions of the annular island region 3; the lead frame 1 is covered with an injection molding layer 11, and the outer ends of the lead terminals 4 are located outside the injection molding layer 11. The lead gold wires 8 are divided into a plurality of groups and respectively penetrate through the adjacent isolation metal sheets 10, the lead gold wires 8 in the same group are connected with the same wafer 7, grounding metal sheets 12 are respectively arranged above and below the lead gold wires 8, and the grounding metal sheets 12 are connected with a grounding end in the lead terminal 4. Two wafers 7 are fixed to each other in the base island region 2 and then separated by an insulating plate 6. This mounting method can reduce the interference between the two chips 7, and also can reduce the loop area formed by the gold lead wires 8, thereby reducing the parasitic capacitance. The adhesive layer 9 is used to protect and fix the wafer 7 and the lead gold wires 8, the isolation metal sheet 10 is used to reduce the capacitance between different groups of lead gold wires 8, and the grounding metal sheet 12 is used to rapidly discharge the charge when the parasitic capacitance is generated. Tooth-shaped parts 14 are uniformly arranged at the edge of the annular island region 3, and inclined plane parts 15 are respectively arranged on two sides of the bottom position of the tooth-shaped part 14. The tooth-shaped portions 14 with the inclined surface portions 15 can not only improve the bonding firmness between the bonding layer 9 and the lead frame 1, but also release the stress on the contact surface of the bonding layer 9 and the lead frame 1. The top surface and the bottom surface of the bonding layer 9 are respectively provided with a plurality of blind holes 13, and the blind holes 13 and the isolation metal sheets 10 are arranged in a staggered mode. The inner side of the injection layer 11 is provided with a positioning pin 16, the bottom of the positioning pin 16 is fixedly connected with the bottom of the blind hole 13, and the side wall of the positioning pin 16 is in clearance fit with the side wall of the blind hole 13. The blind holes 13 in the adhesive layer 9 serve, on the one hand, to relieve the surface stress of the adhesive layer 9 and, in addition, to provide anchor points for the injection-molded layer 11. The inner wall of the injection molding layer 11 is provided with a plurality of grooves 17, and the grooves 17 are positioned in the annular island region 3. The grooves 17 on the inner wall of the injection layer 11 are used for releasing the stress between the injection layer 11 and the bonding layer 9.
A packaging method of the chip packaging structure comprises the following steps:
A. fixing the wafer 7 on the bracket 5, and connecting the wafer 7 with the lead terminal 4 by using a lead gold wire 8;
B. using adhesive glue to carry out fixed adhesion to manufacture an adhesive layer 9; wherein, adhesive glue is used for layering and curing, and each isolation metal sheet 10 and each grounding metal sheet 12 are fixed in sequence; the adhesive glue is layered and cured from the area far away from the base island region 2, and the tension of the gold lead wire 8 in the uncured part is adjusted and homogenized when the adhesive glue is cured;
C. the injection molded layer 11 is manufactured by an injection molding process.
The packaging method can effectively reduce the stress between the lead gold wire 8 and the bonding layer 9, thereby further improving the packaging quality of the chip.
In the description of the present invention, it is to be understood that the terms "longitudinal", "lateral", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like, indicate orientations or positional relationships based on those shown in the drawings, are merely for convenience of description of the present invention, and do not indicate or imply that the referenced devices or elements must have a particular orientation, be constructed and operated in a particular orientation, and thus, are not to be construed as limiting the present invention.
The foregoing shows and describes the general principles and broad features of the present invention and advantages thereof. It will be understood by those skilled in the art that the present invention is not limited to the embodiments described above, which are described in the specification and illustrated only to illustrate the principle of the present invention, but that various changes and modifications may be made therein without departing from the spirit and scope of the present invention, which fall within the scope of the invention as claimed. The scope of the invention is defined by the appended claims and equivalents thereof.
Claims (7)
1. A chip packaging structure comprises a lead frame (1), and is characterized in that: the lead frame (1) comprises a base island region (2), a plurality of ring island regions (3) are arranged on the outer side of the base island region (2), and a plurality of lead terminals (4) are arranged on the outer side of the ring island regions (3); the top and the bottom of the base island region (2) are respectively provided with a bracket (5), the middle of the base island region (2) is provided with an insulating plate (6), two wafers (7) are respectively fixed on the brackets (5), the active surfaces of the wafers (7) are oppositely arranged, and the wafers (7) are connected with the lead terminal (4) through lead gold wires (8); the base island region (2) and the annular island region (3) are coated with bonding layers (9), and a plurality of isolation metal sheets (10) are arranged in the bonding layers (9) at the position of the annular island region (3); the lead frame (1) is coated with an injection molding layer (11), and the outer side end of the lead terminal (4) is positioned outside the injection molding layer (11).
2. The chip package structure according to claim 1, wherein: the lead gold wires (8) are divided into a plurality of groups and respectively penetrate through the adjacent isolation metal sheets (10), the lead gold wires (8) in the same group are connected with the same wafer (7), grounding metal sheets (12) are respectively arranged above and below the lead gold wires (8), and the grounding metal sheets (12) are connected with a grounding end in the lead terminal (4).
3. The chip package structure according to claim 2, wherein: tooth-shaped parts (14) are uniformly arranged on the edge of the annular island region (3), and inclined plane parts (15) are respectively arranged on two sides of the bottom position of each tooth-shaped part (14).
4. The chip package structure according to claim 3, wherein: the top surface and the bottom surface of the bonding layer (9) are respectively provided with a plurality of blind holes (13), and the blind holes (13) and the isolation metal sheets (10) are arranged in a staggered mode.
5. The chip package structure according to claim 4, wherein: the inner side of the injection molding layer (11) is provided with a positioning pin (16), the bottom of the positioning pin (16) is fixedly connected with the bottom of the blind hole (13), and the side wall of the positioning pin (16) is in clearance fit with the side wall of the blind hole (13).
6. The chip package structure according to claim 5, wherein: the inner wall of the injection molding layer (11) is provided with a plurality of grooves (17), and the grooves (17) are located in the annular island region (3).
7. A method for packaging the chip package structure according to any one of claims 1 to 6, comprising the steps of:
A. fixing the wafer (7) on the bracket (5), and connecting the wafer (7) with the lead terminal (4) by using a lead gold wire (8);
B. using adhesive glue to carry out fixed adhesion to manufacture an adhesive layer (9);
C. the injection layer (11) is produced by an injection molding process.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910907219.2A CN110600449A (en) | 2019-09-24 | 2019-09-24 | Chip packaging structure and packaging method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910907219.2A CN110600449A (en) | 2019-09-24 | 2019-09-24 | Chip packaging structure and packaging method thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN110600449A true CN110600449A (en) | 2019-12-20 |
Family
ID=68862879
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201910907219.2A Withdrawn CN110600449A (en) | 2019-09-24 | 2019-09-24 | Chip packaging structure and packaging method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN110600449A (en) |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020074638A1 (en) * | 2000-12-14 | 2002-06-20 | Kuang-Ho Liao | Multi-chip semiconductor package structure |
| CN1455455A (en) * | 2002-05-03 | 2003-11-12 | 海力士半导体有限公司 | Lamina ball grid array package piece of central welding-spot chip and mfg. method thereof |
| US20160190918A1 (en) * | 2014-12-31 | 2016-06-30 | Dominique Ho | Isolator with reduced susceptibility to parasitic coupling |
| CN106449610A (en) * | 2015-08-07 | 2017-02-22 | 瑞萨电子株式会社 | Semiconductor device and manufacturing method thereof |
-
2019
- 2019-09-24 CN CN201910907219.2A patent/CN110600449A/en not_active Withdrawn
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020074638A1 (en) * | 2000-12-14 | 2002-06-20 | Kuang-Ho Liao | Multi-chip semiconductor package structure |
| CN1455455A (en) * | 2002-05-03 | 2003-11-12 | 海力士半导体有限公司 | Lamina ball grid array package piece of central welding-spot chip and mfg. method thereof |
| US20160190918A1 (en) * | 2014-12-31 | 2016-06-30 | Dominique Ho | Isolator with reduced susceptibility to parasitic coupling |
| CN106449610A (en) * | 2015-08-07 | 2017-02-22 | 瑞萨电子株式会社 | Semiconductor device and manufacturing method thereof |
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| Date | Code | Title | Description |
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| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| WW01 | Invention patent application withdrawn after publication | ||
| WW01 | Invention patent application withdrawn after publication |
Application publication date: 20191220 |