CN110600362B - Silicon-based heterogeneous integrated material, preparation method thereof and semiconductor device - Google Patents

Silicon-based heterogeneous integrated material, preparation method thereof and semiconductor device Download PDF

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CN110600362B
CN110600362B CN201910708203.9A CN201910708203A CN110600362B CN 110600362 B CN110600362 B CN 110600362B CN 201910708203 A CN201910708203 A CN 201910708203A CN 110600362 B CN110600362 B CN 110600362B
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layer
ingap
silicon
forming
nanometers
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CN110600362A (en
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常虎东
孙兵
杨枫
丁武昌
刘洪刚
金智
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Institute of Microelectronics of CAS
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
    • H01L21/02175—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
    • H01L21/02178—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing aluminium, e.g. Al2O3
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/022—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being a laminate, i.e. composed of sublayers, e.g. stacks of alternating high-k metal oxides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Abstract

The application provides a silicon-based heterogeneous integrated material, a preparation method thereof and a semiconductor device2A dielectric layer; in the SiO2Forming an aluminum gallium arsenide (AlGaAs) protective layer on the dielectric layer, forming an indium gallium phosphide (InGaP) buffer layer on the AlGaAs protective layer, forming an indium gallium arsenide (InGaAs) channel layer on the InGaP buffer layer, forming an indium gallium phosphide (InGaP) InGaP barrier layer on the InGaAs channel layer, and forming a gallium arsenide (GaAs) cap layer on the InGaP barrier layer2As the dielectric layer and the AlGaAs material are used as the intermediate insulating material and the protective material of the whole material, the capability of preventing electric leakage of the device substrate is integrally improved, the noise characteristic of the manufactured device and the integrated circuit is favorably improved, and the design and the performance of the heterogeneous integrated circuit can be improved.

Description

Silicon-based heterogeneous integrated material, preparation method thereof and semiconductor device
Technical Field
The application relates to the technical field of microelectronics, in particular to a silicon-based heterogeneous integrated material, a preparation method thereof and a semiconductor device.
Background
Modern integrated circuits based on silicon-based Complementary Metal Oxide Semiconductor (CMOS) technology are continuously advancing in terms of integration level, power consumption and device characteristics as the feature size of CMOS devices is continuously shrinking.
On the other hand, compound semiconductor devices and integrated circuits have been developed in the fields of ultra-high-speed circuits, microwave circuits, terahertz circuits, optoelectronic integrated circuits, and the like.
Because the silicon-based CMOS chip and the compound semiconductor chip are difficult to produce in the same wafer factory and can not realize process compatibility, if the silicon-based CMOS chip and the compound semiconductor chip are organically combined, the problems that the device selection is limited and various devices made of different materials can not be mixed and integrated in the field of integrated circuit design are further solved, and the design and the performance of the integrated circuit can be greatly improved.
Disclosure of Invention
The application aims to provide a silicon-based heterogeneous integrated material, a preparation method thereof and a semiconductor device, which are used for realizing the design and performance improvement of an integrated circuit.
The application provides a preparation method of a silicon-based heterogeneous integrated material, which comprises the following steps:
providing a silicon-based semiconductor substrate;
forming silicon dioxide SiO on the silicon-based semiconductor substrate2A dielectric layer;
in the SiO2Forming an aluminum gallium arsenide (AlGaAs) protective layer on the dielectric layer;
forming an indium gallium phosphide InGaP buffer layer on the AlGaAs protective layer;
forming an indium gallium arsenide (InGaAs) channel layer on the InGaP buffer layer;
forming an InGaP barrier layer on the InGaAs channel layer;
and forming a gallium arsenide GaAs cap layer on the InGaP barrier layer.
In one possible implementation, in the above method provided herein, the SiO is2The thickness of the dielectric layer was 200 nm.
In one possible implementation, the AlGaAs protective layer has a thickness in the range of 100 nm to 300 nm and an Al composition in the AlGaAs material in the range of 0.1 to 0.3 in the above-described method provided in the present application.
In one possible implementation, the InGaP buffer layer has a thickness In a range of 200 nm to 400 nm and an In composition of 0.49 In the InGaP material In the above-described method provided herein.
In one possible implementation, the InGaAs channel layer has a thickness In the range of 10 nm to 100 nm and In composition In the InGaAs material is In the range of 0 to 0.4 In the above method provided by the present application.
In one possible implementation, the InGaP barrier layer has a thickness In a range from 30 nm to 100 nm and the In composition of the InGaP material is 0.49 In the above method provided by the present application.
In one possible implementation manner, in the above method provided by the present application, the thickness of the GaAs cap layer ranges from 100 nm to 200 nm, the doping type is N-type, and the doping concentration is greater than 5 × 1018cm-3。
A second aspect of the present application provides a silicon-based heterogeneous integrated material, which is manufactured by the method of the first aspect, and includes:
a silicon-based semiconductor substrate;
silicon dioxide SiO formed on the silicon-based semiconductor substrate2A dielectric layer;
in the SiO2An AlGaAs protective layer formed on the dielectric layer;
an InGaP buffer layer formed on the AlGaAs protective layer;
an InGaAs channel layer formed on the InGaP buffer layer;
an InGaP barrier layer formed on the InGaAs channel layer;
a GaAs cap layer formed on the InGaP barrier layer.
In a third aspect of the present application, a semiconductor device is provided, where the material of the semiconductor device is the silicon-based heterogeneous integrated material described in the second aspect.
Compared with the prior art, the silicon-based heterogeneous integrated material, the preparation method thereof and the semiconductor device provided by the application have the advantages that silicon dioxide SiO is formed on the silicon semiconductor substrate2A dielectric layer; in the SiO2Forming an aluminum gallium arsenide (AlGaAs) protective layer on the dielectric layer, forming an indium gallium phosphide (InGaP) buffer layer on the AlGaAs protective layer, forming an indium gallium arsenide (InGaAs) channel layer on the InGaP buffer layer, forming an indium gallium phosphide (InGaP) InGaP barrier layer on the InGaAs channel layer, and forming a gallium arsenide (GaAs) cap layer on the InGaP barrier layer2As a dielectric layer, and AlGaAs material is used as the intermediate insulating material and protective material of the whole material, the capability of preventing electric leakage of the device substrate is improved as a whole, and the device and the assembly are improvedThe noise characteristic of the integrated circuit is very beneficial, and the design and the performance of the heterogeneous integrated circuit can be improved.
Drawings
Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The drawings are only for purposes of illustrating the preferred embodiments and are not to be construed as limiting the application. Also, like reference numerals are used to refer to like parts throughout the drawings. In the drawings:
fig. 1 illustrates a flow diagram of a method for preparing a silicon-based heterogeneous integrated material according to some embodiments of the present disclosure;
fig. 2 illustrates a block diagram of a silicon-based heterogeneous integrated material provided by some embodiments of the present application.
Detailed Description
Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.
It is to be noted that, unless otherwise specified, technical terms or scientific terms used herein shall have the ordinary meaning as understood by those skilled in the art to which this application belongs.
In addition, the terms "first" and "second", etc. are used to distinguish different objects, rather than to describe a particular order. Furthermore, the terms "include" and "have," as well as any variations thereof, are intended to cover non-exclusive inclusions. For example, a process, method, system, article, or apparatus that comprises a list of steps or elements is not limited to only those steps or elements listed, but may alternatively include other steps or elements not listed, or inherent to such process, method, article, or apparatus.
Embodiments of the present application provide a method for preparing a silicon-based heterogeneous integrated material, and a semiconductor device, which are described below with reference to the accompanying drawings.
Referring to fig. 1 and fig. 2, fig. 1 shows a flow chart of a method for manufacturing a silicon-based heterogeneous integrated material according to some embodiments of the present application, fig. 2 shows a structural diagram of a silicon-based heterogeneous integrated material according to some embodiments of the present application, and the silicon-based heterogeneous integrated material in fig. 2 is manufactured by the method for manufacturing a silicon-based heterogeneous integrated material in fig. 1, which may include the following steps:
step S101: providing a silicon-based semiconductor substrate 101;
step S102: forming silicon dioxide SiO on the silicon-based semiconductor substrate 1012A dielectric layer 102;
step S103: in the SiO2Forming an AlGaAs protective layer 103 on the dielectric layer 102;
step S104: forming an indium gallium phosphide InGaP buffer layer 104 on the AlGaAs protective layer 103;
step S105: forming an indium gallium arsenide InGaAs channel layer 105 on the InGaP buffer layer 104;
step S106: forming an indium gallium phosphide InGaP barrier layer 106 on the InGaAs channel layer 105;
step S107: a gallium arsenide GaAs cap layer 107 is formed on the InGaP barrier layer 106.
Specifically, realizing the epitaxy of gallium arsenide (GaAs) materials on a silicon-based semiconductor is an important way to realize the integration of silicon-based semiconductor devices and indium phosphide-based (InP) semiconductor devices, and a good silicon-based compound semiconductor structure can certainly improve the performance of heterogeneous integrated circuits. By forming SiO on silicon-based semiconductors2The GaAs-based material structure on the medium makes full use of the advantages of GaAs material in realizing large-size growth and industrial production, and the GaAs material is also the most mature compound semiconductor material at present. On the other hand, SiO is used2As a dielectric layer and AlGaAs material is adopted as the intermediate insulating material and the protective material of the whole material, the high-performance silicon-based compound is realizedThe characteristics of the semiconductor material can finally realize the improvement of the design and the performance of the heterogeneous integrated circuit.
In order to ensure the optimal film forming quality, the application also provides the film forming thickness and components of each film layer in the silicon-based heterogeneous integrated material.
In some embodiments, the SiO is based on the above examples2The dielectric layer may have a thickness of 200 nm.
In some embodiments, based on the above examples, the AlGaAs protective layer has a thickness in the range of 100 nm to 300 nm and an Al composition in the AlGaAs material in the range of 0.1 to 0.3.
In some embodiments, based on the above examples, the thickness of the InGaP buffer layer ranges from 200 nm to 400 nm, and the In composition of the InGaP material is 0.49.
In some embodiments, based on the above example, the thickness of the InGaAs channel layer ranges from 10 nm to 100 nm, and the In composition of the InGaAs material ranges from 0 to 0.4.
In some embodiments, based on the above example, the InGaP barrier layer has a thickness In the range of 30 nanometers to 100 nanometers and the In composition of the InGaP material is 0.49.
In some embodiments, based on the above embodiment, the thickness of the GaAs cap layer ranges from 100 nm to 200 nm, the doping type is N-type, and the doping concentration is greater than 5 × 1018cm-3。
The preparation method of the silicon-based heterogeneous integrated material provided by the application comprises the step of forming silicon dioxide SiO on a silicon semiconductor substrate2A dielectric layer; in the SiO2Forming an aluminum gallium arsenide (AlGaAs) protective layer on the dielectric layer, forming an indium gallium phosphide (InGaP) buffer layer on the AlGaAs protective layer, forming an indium gallium arsenide (InGaAs) channel layer on the InGaP buffer layer, forming an indium gallium phosphide (InGaP) InGaP barrier layer on the InGaAs channel layer, and forming a gallium arsenide (GaAs) cap layer on the InGaP barrier layer2As a dielectric layer, and AlGaAs material is used as the intermediate insulating material and the protective material of the whole material, the capability of preventing the electric leakage of the device substrate is improved as a wholeThe noise characteristics of the high-performance device and the integrated circuit are very beneficial, and the design and the performance of the heterogeneous integrated circuit can be improved.
Based on the same inventive concept, the embodiment of the present application further provides a silicon-based heterogeneous integrated material, and since the principle of solving the problem of the silicon-based heterogeneous integrated material is similar to that of the aforementioned manufacturing method, the implementation of the silicon-based heterogeneous integrated material can refer to the implementation of the manufacturing method, and repeated parts are not described again.
Specifically, referring to fig. 2, some embodiments of the present disclosure provide a silicon-based heterogeneous integrated material including:
a silicon-based semiconductor substrate 101;
silicon dioxide SiO formed on the silicon-based semiconductor 101 substrate2 A dielectric layer 102;
in the SiO2An aluminum gallium arsenide (AlGaAs) protective layer 103 formed on the dielectric layer 102;
an indium gallium phosphide InGaP buffer layer 104 formed on the AlGaAs protective layer 103;
an indium gallium arsenide InGaAs channel layer 105 formed on the InGaP buffer layer 104;
an indium gallium phosphide InGaP barrier layer 106 formed on the InGaAs channel layer 105;
a GaAs cap layer 107 formed on the InGaP barrier layer 106.
Optionally, the SiO2The thickness of the dielectric layer was 200 nm.
Optionally, the AlGaAs protective layer has a thickness in a range of 100 nm to 300 nm, and the Al composition in the AlGaAs material is in a range of 0.1 to 0.3.
Optionally, the thickness of the InGaP buffer layer ranges from 200 nm to 400 nm, and the In composition In the InGaP material is 0.49.
Optionally, the thickness of the InGaAs channel layer ranges from 10 nm to 100 nm, and the In composition range of the InGaAs material ranges from 0 to 0.4.
Optionally, the InGaP barrier layer has a thickness In a range of 30 nm to 100 nm, and the In composition In the InGaP material is 0.49.
Optionally, the thickness of the GaAs cap layer ranges from 100 nm to 200 nm, the doping type of the GaAs cap layer is N-type, and the doping concentration is greater than 5 × 1018cm-3。
Based on the same inventive concept, the embodiment of the application also provides a semiconductor device, and the material of the semiconductor device is the silicon-based heterogeneous integrated material provided by the embodiment. The semiconductor device may be implemented in the embodiments of the silicon-based heterogeneous integrated material, and repeated details are not repeated.
Finally, it should be noted that: the above embodiments are only used for illustrating the technical solutions of the present application, and not for limiting the same; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; such modifications and substitutions do not depart from the spirit and scope of the present disclosure, and the present disclosure should be construed as being covered by the claims and the specification.

Claims (3)

1. A preparation method of a silicon-based heterogeneous integrated material is characterized by comprising the following steps:
providing a silicon-based semiconductor substrate;
forming silicon dioxide SiO on the silicon-based semiconductor substrate2A dielectric layer; the SiO2The thickness of the dielectric layer is 200 nanometers;
in the SiO2Forming an AlGaAs protective layer on the medium layer; the thickness range of the AlGaAs protective layer is 100 nanometers to 300 nanometers, and the Al component range in the AlGaAs material is 0.1 to 0.3;
forming an InGaP buffer layer on the AlGaAs protective layer; the thickness range of the InGaP buffer layer is 200 nanometers to 400 nanometers, and the In component In the InGaP material is 0.49;
forming an indium gallium arsenide (InGaAs) channel layer on the InGaP buffer layer; the thickness range of the InGaAs channel layer is 10 nanometers to 100 nanometers, and the composition range of In the InGaAs material is 0 to 0.4;
forming an InGaP barrier layer on the InGaAs channel layer; the thickness range of the InGaP barrier layer is 30 nanometers to 100 nanometers, and the In component In the InGaP material is 0.49;
forming a gallium arsenide (GaAs) cap layer on the InGaP barrier layer; the thickness range of the GaAs cap layer is 100 nanometers to 200 nanometers, the doping type of the GaAs cap layer is N type, and the doping concentration is more than 5 multiplied by 1018cm-3。
2. A silicon-based heterogeneous integrated material, wherein the silicon-based heterogeneous integrated material is fabricated by the method of claim 1, and the silicon-based heterogeneous integrated material comprises:
a silicon-based semiconductor substrate;
silicon dioxide SiO formed on the silicon-based semiconductor substrate2A dielectric layer;
in the SiO2An AlGaAs protective layer formed on the dielectric layer;
an InGaP buffer layer formed on the AlGaAs protective layer;
an InGaAs channel layer formed on the InGaP buffer layer;
an InGaP barrier layer formed on the InGaAs channel layer;
and the gallium arsenide GaAs cap layer is formed on the InGaP barrier layer.
3. A semiconductor device, wherein the material of the semiconductor device is the silicon-based heterogeneous integrated material according to claim 2.
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Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1416591A (en) * 2000-02-10 2003-05-07 摩托罗拉公司 Semiconductor structure
WO2004059744A1 (en) * 2002-12-25 2004-07-15 Sumitomo Chemical Company, Limited Compound semiconductor epitaxial substrate and method for manufacturing same
CN102569364A (en) * 2010-12-08 2012-07-11 中国科学院微电子研究所 Substrate structure with high mobility and preparation method thereof
CN205159336U (en) * 2015-12-16 2016-04-13 成都嘉石科技有限公司 Silica -based heterogeneous integrated MHEMT structure
CN205670542U (en) * 2016-06-17 2016-11-02 成都海威华芯科技有限公司 A kind of silica-based heterogeneous integrated P-channel HFET device
US20160327737A1 (en) * 2014-01-14 2016-11-10 Massachusetts Institute Of Technology Method of forming an integrated circuit and related integrated circuit

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1416591A (en) * 2000-02-10 2003-05-07 摩托罗拉公司 Semiconductor structure
WO2004059744A1 (en) * 2002-12-25 2004-07-15 Sumitomo Chemical Company, Limited Compound semiconductor epitaxial substrate and method for manufacturing same
CN102569364A (en) * 2010-12-08 2012-07-11 中国科学院微电子研究所 Substrate structure with high mobility and preparation method thereof
US20160327737A1 (en) * 2014-01-14 2016-11-10 Massachusetts Institute Of Technology Method of forming an integrated circuit and related integrated circuit
CN205159336U (en) * 2015-12-16 2016-04-13 成都嘉石科技有限公司 Silica -based heterogeneous integrated MHEMT structure
CN205670542U (en) * 2016-06-17 2016-11-02 成都海威华芯科技有限公司 A kind of silica-based heterogeneous integrated P-channel HFET device

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