CN110596959B - Array substrate and friction alignment method thereof - Google Patents

Array substrate and friction alignment method thereof Download PDF

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Publication number
CN110596959B
CN110596959B CN201910815037.2A CN201910815037A CN110596959B CN 110596959 B CN110596959 B CN 110596959B CN 201910815037 A CN201910815037 A CN 201910815037A CN 110596959 B CN110596959 B CN 110596959B
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array substrate
electrode layer
liquid crystal
display area
layer
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CN110596959A (en
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林建伟
卓然然
庄崇营
李林
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Truly Semiconductors Ltd
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Truly Semiconductors Ltd
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    • GPHYSICS
    • G02OPTICS
    • G02FOPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333Constructional arrangements; Manufacturing methods
    • G02F1/1337Surface-induced orientation of the liquid crystal molecules, e.g. by alignment layers
    • G02F1/13378Surface-induced orientation of the liquid crystal molecules, e.g. by alignment layers by treatment of the surface, e.g. embossing, rubbing or light irradiation
    • G02F1/133784Surface-induced orientation of the liquid crystal molecules, e.g. by alignment layers by treatment of the surface, e.g. embossing, rubbing or light irradiation by rubbing

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  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Spectroscopy & Molecular Physics (AREA)
  • Mathematical Physics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • General Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)
  • Liquid Crystal (AREA)

Abstract

The invention discloses an array substrate, which comprises a display area and a quick-check binding area, wherein the quick-check binding area is positioned outside the display area, and a liquid crystal alignment layer covers the display area; a plurality of rapid detection PADs are arranged in the rapid detection binding region, and a plurality of through holes are formed in the rapid detection PADs; the plurality of via holes are arranged along a straight line. The array substrate can reduce the deformation degree of the bristles on the surface of the roller for rubbing the liquid crystal alignment layer, and improve the friction uniformity of the liquid crystal alignment layer. The invention also discloses a friction alignment method of the array substrate.

Description

Array substrate and friction alignment method thereof
Technical Field
The invention relates to a display technology, in particular to an array substrate and a friction alignment method thereof.
Background
With the development of display technology and the improvement of quality of life of users, liquid crystal display devices are increasingly used in daily life of people, such as vehicle-mounted displays, televisions, computers, tablets, mobile phones, and the like. When a liquid crystal display panel is manufactured, a corresponding liquid crystal alignment layer needs to be manufactured on the inner side surface of a color film substrate of an array substrate of the panel respectively, and a pre-tilt angle is provided for liquid crystal molecules between the color film substrates of the array substrate by utilizing a saw-tooth-shaped groove of the liquid crystal alignment layer. And a fast detection binding area exists outside the display area of the array substrate, and a plurality of fast detection PADs are arranged in the fast detection binding area and used for fast detecting the display circuit on the array substrate before box forming. As shown in fig. 1 and 2, the fast PAD 205 'is composed of a first electrode layer 21', an insulating layer 22 'and a second electrode layer 23' which are stacked, the insulating layer 22 'is provided with a plurality of via holes 206', the second electrode layer 23 'is electrically connected with the first electrode layer 21' through the via holes 206 ', so that the surface of the fast PAD 205' is uneven, the plurality of via holes 206 'are arranged in a lattice manner in the fast PAD 205', and when a roller for rubbing the liquid crystal alignment layer sweeps over the fast PAD 205 ', some places on the surface of the roller sweep over at least two via holes 206', so that bristles on the surface of the roller are seriously deformed, and the friction on the liquid crystal alignment layer is not uniform.
Disclosure of Invention
In order to solve the above-mentioned deficiencies of the prior art, the present invention provides an array substrate, which can reduce the deformation degree of the brush bristles on the roller surface of the rubbing liquid crystal alignment layer and improve the rubbing uniformity of the liquid crystal alignment layer.
The invention also provides a friction alignment method of the array substrate.
The technical problem to be solved by the invention is realized by the following technical scheme:
an array substrate comprises a display area and a quick-check binding area located outside the display area, wherein a liquid crystal alignment layer covers the display area; a plurality of rapid detection PADs are arranged in the rapid detection binding region, and a plurality of through holes are formed in the rapid detection PADs; the plurality of via holes are arranged along a straight line.
Further, the liquid crystal alignment layer has an alignment direction in a transverse, longitudinal, or oblique direction.
Furthermore, the rapid detection PAD comprises a first electrode layer, an insulating layer and a second electrode layer which are stacked, wherein the via holes are formed in the insulating layer, and the second electrode layer is electrically connected with the first electrode layer through the via holes.
Further, the first electrode layer is a metal electrode layer, and/or the second electrode layer is an ITO electrode layer.
Further, the rapid inspection PAD comprises a connecting portion and a straight portion, and the via holes are arranged on the straight portion in a straight line.
Further, the quick detection PAD is connected with a display circuit in the display area.
Furthermore, a display circuit is arranged in the display area, a plurality of peripheral wires are arranged in the wire routing area, a plurality of binding PADs are arranged in the quick detection binding area, and the plurality of peripheral wires are connected between the display circuit and the plurality of binding PADs.
Further, the quick detection PAD is connected to the plurality of peripheral areas and is connected to the display circuit in the display area through the plurality of peripheral areas.
A rubbing alignment method of an array substrate comprises the following steps:
step 1: providing a large-panel substrate with at least one array substrate, wherein the array substrate comprises a display area and a quick-check binding area positioned outside the display area, and the display area is covered with a liquid crystal alignment layer; a plurality of rapid detection PADs are arranged in the rapid detection binding region, and a plurality of through holes are formed in the rapid detection PADs; the plurality of through holes are arranged along a straight line;
step 2: and rubbing the liquid crystal alignment layer on the array substrate by using a roller to form an alignment direction of the liquid crystal alignment layer, wherein the moving direction of the roller is not parallel to the arrangement direction of the via holes.
Further, the moving direction of the roller forms a certain angle with the arrangement direction of the via holes, so that any point on the surface of the roller can sweep through at most one via hole.
The invention has the following beneficial effects: the array substrate is provided with the via holes in the rapid inspection PAD in a linear arrangement mode, so that when a roller rubbing the liquid crystal alignment layer passes through the rapid inspection PAD, the number of the via holes swept by the surface of the roller is greatly reduced, the deformation degree of bristles on the surface of the roller is reduced, and the friction uniformity of the liquid crystal alignment layer is improved.
Drawings
FIG. 1 is a schematic diagram of a prior art rapid test PAD;
FIG. 2 is a cross-sectional view A '-A' of the rapid test PAD of FIG. 1;
FIG. 3 is a schematic view of an array substrate according to the present invention;
FIG. 4 is a schematic diagram of a rapid test PAD provided by the present invention;
FIG. 5 is a cross-sectional view A-A of a rapid test PAD provided by the present invention;
fig. 6 is a block diagram illustrating a rubbing method for an array substrate according to the present invention.
Detailed Description
The present invention will be described in detail below with reference to the accompanying drawings and examples.
Example one
As shown in fig. 3, an array substrate includes a display area 201, and a routing area 202 and a quick test binding area 203 located outside the display area 201, where the routing area 202 is located between the display area 201 and the quick test binding area 203 and surrounds the display area 201, and the quick test binding area 203 is located on at least one side of the routing area 202; the display area 201 is covered with a liquid crystal alignment layer, and a plurality of quick-check PADs 205 are arranged in the quick-check binding area 203; as shown in fig. 4, the fast inspection PAD 205 is provided with a plurality of vias 206, and the plurality of vias 206 are arranged in a straight line.
The through holes 206 in the rapid detection PAD 205 of the array substrate are arranged in a linear arrangement mode, so that when a roller rubbing the liquid crystal alignment layer passes through the rapid detection PAD 205, the number of the through holes 206 swept by the surface of the roller is greatly reduced, the deformation degree of bristles on the surface of the roller is reduced, and the friction uniformity of the liquid crystal alignment layer is improved.
When the roller rubs the liquid crystal alignment layer, the roller can move along the transverse direction, the longitudinal direction or the oblique direction to sweep the liquid crystal alignment layer, so that the liquid crystal alignment layer has the alignment direction along the transverse direction, the longitudinal direction or the oblique direction, and the liquid crystal alignment layer forms a zigzag groove to provide a pretilt angle for liquid crystal molecules in the alignment direction.
However, the moving direction of the roller is not parallel to the arrangement direction of the plurality of via holes 206, and needs to be at a certain angle; most preferably, the moving direction of the roller forms an angle with the arrangement direction of the plurality of through holes 206, so that any point on the surface of the roller sweeps at most one through hole 206, and is not limited to 90 ° in this embodiment, as long as the orthographic projections of the plurality of through holes 206 on the central axis of the roller do not contact each other.
As shown in fig. 5, the quick test PAD 205 includes a first electrode layer 21, an insulating layer 22, and a second electrode layer 23, which are stacked, wherein the plurality of via holes 206 are opened in the insulating layer 22, and the second electrode layer 23 is electrically connected to the first electrode layer 21 through the plurality of via holes 206; the first electrode layer 21 is not limited to a metal electrode layer, and the second electrode layer 23 is not limited to an ITO electrode layer.
The rapid inspection PAD 205 comprises a connecting part 2051 and a straight part 2052, wherein the connecting part 2051 is used for being connected with a metal probe of a rapid inspection device so as to rapidly inspect a display circuit on the array substrate, the straight part 2052 is used for being connected with the connecting part 2051, and the through holes 206 are arranged in the straight part 2052 along a straight line.
A display circuit is arranged in the display area 201, a plurality of peripheral wires are arranged in the wire area 202, a plurality of binding PADs 204 are arranged in the quick test binding area 203, and the plurality of peripheral wires are connected between the display circuit and the plurality of binding PADs 204; the plurality of binding PADs 204 are used for binding the driving IC and the flexible circuit board after the array substrate and the color film substrate are oppositely attached to form a box.
The quick detection PAD is connected with a display circuit in the display area. Specifically, the quick test PAD 205 is connected to the plurality of peripheral traces through the first electrode layer 21 of the straight portion 2052, and is connected to the display circuit through the plurality of peripheral traces. The first electrode layer 21 of the linear portion 2052 of the quick detection PAD 205 may be led out from the plurality of bonding PADs 204, or may be directly led out from the plurality of peripheral traces. When the plurality of peripheral traces or the plurality of bonding PADs 204 are manufactured, the first electrode layer 21 is manufactured on the same layer, the first electrode layer 21 includes first electrode wires led out from the plurality of peripheral traces or the plurality of bonding PADs 204, then the insulating layer 22 is manufactured on the first electrode layer 21 and the plurality of via holes 206 are formed, finally the second electrode layer 23 is manufactured on the insulating layer 22, the second electrode layer 23 includes a second electrode wire connected with the connecting portion 2051 through the connecting portion 2051, and the second electrode wire and the first electrode wire are overlapped through the insulating layer 22 and are electrically connected through the plurality of via holes 206.
Example two
As shown in fig. 6, a rubbing alignment method of an array substrate according to an embodiment includes:
step 1: providing a large-panel substrate with at least one array substrate, wherein the array substrate comprises a display area 201 and a quick check binding area 203 positioned outside the display area 201, and the display area 201 is covered with a liquid crystal alignment layer; a plurality of quick detection PADs 205 are arranged in the quick detection binding region 203, and a plurality of through holes 206 are arranged on the quick detection PADs 205; the plurality of vias 206 are arranged along a straight line;
step 2: rubbing the liquid crystal alignment layer on the array substrate by using a roller to form an alignment direction of the liquid crystal alignment layer, wherein the moving direction of the roller is not parallel to the arrangement direction of the plurality of via holes 206.
The large-plate substrate is formed by manufacturing a plurality of array substrates on the same glass substrate.
Preferably, the moving direction of the roller forms a certain angle with the arrangement direction of the plurality of via holes, so that any point on the surface of the roller sweeps through at most one via hole.
The above-mentioned embodiments only express the embodiments of the present invention, and the description is more specific and detailed, but not understood as the limitation of the patent scope of the present invention, but all the technical solutions obtained by using the equivalent substitution or the equivalent transformation should fall within the protection scope of the present invention.

Claims (9)

1. A rubbing alignment method of an array substrate is characterized by comprising the following steps:
step 1: providing a large-panel substrate with at least one array substrate, wherein the array substrate comprises a display area and a quick-check binding area positioned outside the display area, and the display area is covered with a liquid crystal alignment layer; a plurality of rapid detection PADs are arranged in the rapid detection binding region, and a plurality of through holes are formed in the rapid detection PADs;
step 2: rubbing the liquid crystal alignment layer on the array substrate by using a roller to form an alignment direction of the liquid crystal alignment layer;
wherein the plurality of via holes are arranged along a single straight line; the moving direction of the roller is not parallel to the arrangement direction of the via holes, so that any point on the surface of the roller can sweep through at most one via hole.
2. The rubbing alignment method of the array substrate of claim 1, wherein the liquid crystal alignment layer has an alignment direction along a lateral, longitudinal or oblique direction.
3. The rubbing alignment method of the array substrate of claim 1, wherein the fast inspection PAD comprises a first electrode layer, an insulating layer and a second electrode layer which are stacked, the plurality of via holes are opened in the insulating layer, and the second electrode layer is electrically connected with the first electrode layer through the plurality of via holes.
4. The rubbing alignment method for the array substrate of claim 3, wherein the first electrode layer is a metal electrode layer, and/or the second electrode layer is an ITO electrode layer.
5. The method of claim 1, wherein the quick test PAD comprises a connection portion and a linear portion, and the plurality of vias are arranged along a straight line on the linear portion.
6. The method of claim 1, wherein the fast PAD is connected to a display circuit in the display area.
7. The rubbing alignment method for the array substrate according to claim 1, wherein a display circuit is disposed in the display region, a plurality of peripheral traces are disposed in the trace region, a plurality of bonding PADs are disposed in the fast inspection bonding region, and the plurality of peripheral traces are connected between the display circuit and the plurality of bonding PADs.
8. The method of claim 7, wherein the fast inspection PAD is connected to the plurality of peripheral areas, and is connected to a display circuit in the display area through the plurality of peripheral areas.
9. The rubbing alignment method for the array substrate of claim 1, wherein the moving direction of the roller is at an angle with the arrangement direction of the plurality of vias.
CN201910815037.2A 2019-08-30 2019-08-30 Array substrate and friction alignment method thereof Active CN110596959B (en)

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Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08184833A (en) * 1994-12-30 1996-07-16 Casio Comput Co Ltd Substrate transporting mechanism and orientation treating device formed by using the same
JP2007079211A (en) * 2005-09-15 2007-03-29 Seiko Epson Corp Electro-optic device, electronic equipment, and method for manufacturing electro-optic device
KR20120075145A (en) * 2010-12-28 2012-07-06 엘지디스플레이 주식회사 Liquid crystal display device and method of fabricating thereof
CN103033991A (en) * 2012-12-14 2013-04-10 京东方科技集团股份有限公司 Substrate, forming method of substrate and liquid crystal display
CN105068327A (en) * 2015-09-16 2015-11-18 京东方科技集团股份有限公司 Array substrate and manufacturing method thereof, display panel and display device
CN109407412A (en) * 2018-12-18 2019-03-01 信利半导体有限公司 Friction matching substrate

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010230740A (en) * 2009-03-26 2010-10-14 Hitachi Displays Ltd Liquid crystal display device and method for manufacturing the same

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08184833A (en) * 1994-12-30 1996-07-16 Casio Comput Co Ltd Substrate transporting mechanism and orientation treating device formed by using the same
JP2007079211A (en) * 2005-09-15 2007-03-29 Seiko Epson Corp Electro-optic device, electronic equipment, and method for manufacturing electro-optic device
KR20120075145A (en) * 2010-12-28 2012-07-06 엘지디스플레이 주식회사 Liquid crystal display device and method of fabricating thereof
CN103033991A (en) * 2012-12-14 2013-04-10 京东方科技集团股份有限公司 Substrate, forming method of substrate and liquid crystal display
CN105068327A (en) * 2015-09-16 2015-11-18 京东方科技集团股份有限公司 Array substrate and manufacturing method thereof, display panel and display device
CN109407412A (en) * 2018-12-18 2019-03-01 信利半导体有限公司 Friction matching substrate

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