CN110596682A - Voltage type open-loop temperature-dependent adjusting system based on FPGA chip - Google Patents
Voltage type open-loop temperature-dependent adjusting system based on FPGA chip Download PDFInfo
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- CN110596682A CN110596682A CN201911002283.2A CN201911002283A CN110596682A CN 110596682 A CN110596682 A CN 110596682A CN 201911002283 A CN201911002283 A CN 201911002283A CN 110596682 A CN110596682 A CN 110596682A
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
- G01S7/00—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00
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Abstract
The invention discloses a voltage type open loop temperature-dependent regulating system based on an FPGA chip, which is used for carrying out temperature compensation on an APD of a laser radar, and comprises an FPGA chip processor, a temperature acquisition module and a voltage regulation module, wherein the temperature acquisition module acquires the temperature of the APD and transmits the temperature to the FPGA chip processor; the voltage regulation module generates an output voltage used as an APD bias voltage, is controlled by the FPGA chip processor and regulates the output voltage V according to a voltage regulation signal of the FPGA chip processorAPDSo that the regulated output voltage VAPDThe bias voltage required by the APD under temperature compensation is the same; and the FPGA chip processor generates a voltage adjusting signal according to the received temperature signal. According to the invention, the measurement precision of the laser radar is improved by adjusting along with the temperature, and the sensitivity of the measurement precision of the laser radar to the temperature is reduced. Each module is composed of a low-voltage and digital circuit matched with an integrated chip, the voltage is adjusted stably along with the temperature, the adjusting precision is high, the adjusting voltage ripple is small, and the oscillation in the adjusting process is small.
Description
Technical Field
The invention relates to the technical field of laser radars, in particular to a voltage type open-loop temperature-dependent adjusting system based on an FPGA chip, which is used for carrying out temperature compensation on APDs of the laser radars.
Background
An Avalanche Photodiode (APD) is a p-n junction type light detection diode, and when the APD is applied to a laser receiving circuit of a laser radar, the avalanche multiplication effect of carriers under the breakdown voltage of the APD is utilized to gain and amplify a photoelectric signal so as to improve the detection sensitivity. In practical applications, the change of the environmental temperature greatly affects the characteristics of the APD, and when the temperature rises, the breakdown voltage of the APD also rises, and if the operating voltage (i.e. high voltage) of the APD is not changed, the photoelectric detection performance of the APD is weakened, and the sensitivity is reduced.
At present, the requirement of measurement accuracy of a product (i.e. achieving that an APD works at a constant gain) is generally achieved by controlling the internal temperature of a laser radar, for example, chinese patent with publication number CN201853143U discloses a laser radar temperature control device, which includes a radar, a telescope main barrel, a sensor and a temperature control device, wherein the temperature control device includes a semiconductor refrigerator and a temperature control circuit board, and the temperature control circuit board is electrically connected with the semiconductor refrigerator through a lead terminal. The use of the temperature control device expands the use temperature range of the laser radar, and completely ensures that the temperature control precision is not influenced under the condition that the temperature difference between the inside and the outside reaches 60 ℃. This approach has many drawbacks: the internal temperature of the laser radar is easily interfered by the outside, the temperature regulation has a certain time delay, and the internal temperature regulation needs to consume a large amount of energy (which is even more than several times compared with the main working energy of the laser radar).
In addition, chinese patent publication No. CN109541569A discloses a laser radar PAD temperature compensation system, which collects the temperature of APD in real time through a temperature collection module, measures the real-time voltage of APD through a voltage feedback module, compares the real-time voltage with a prestored theoretical voltage corresponding to the real-time temperature through an FPGA chip processor, and adjusts a PWM signal for controlling the output voltage of a voltage boost module according to the comparison result, thereby implementing the laser radar APD temperature compensation. In the scheme, the output voltage is adjusted in a mode of adjusting the output duty ratio of the MOS tube by outputting the PWM signal through the FPGA chip processor, the adjusting speed is low, the oscillation is large in the adjusting process, and the voltage output ripple is large. In addition, the circuit structure of the boosting module built by discrete components is very unstable.
Disclosure of Invention
The embodiment of the invention provides a voltage type open-loop temperature-dependent regulating system based on an FPGA chip, which is applied to a photoelectric receiving circuit of a laser radar, improves the measurement precision of the laser radar by performing temperature compensation on APD of the laser radar through temperature-dependent regulation, and reduces the sensitivity of the measurement precision of the laser radar to temperature. Each module is composed of a low-voltage and digital circuit matched with an integrated chip, the voltage is adjusted stably along with the temperature, the adjusting precision is high, the adjusting voltage ripple is small, and the oscillation in the adjusting process is small.
In order to solve the technical problem, the invention provides a voltage type open loop temperature-dependent regulating system based on an FPGA chip, which is used for carrying out temperature compensation on an APD of a laser radar and comprises an FPGA chip processor, a temperature acquisition module and a voltage regulating module,
the temperature acquisition module is used for acquiring the temperature of the APD in real time and transmitting the temperature to the FPGA chip processor;
the voltage regulating module generates output voltage used as APD bias voltage, is controlled by the FPGA chip processor, and regulates the output voltage V according to the voltage regulating signal of the FPGA chip processorAPDSo that the regulated output voltage VAPDThe bias voltage required by the APD under temperature compensation is the same;
the FPGA chip processor receives a temperature signal output by the temperature acquisition module and generates the voltage regulation signal according to the temperature signal;
the FPGA chip processor realizes logic operation and data processing based on an internal programmable logic circuit.
In a preferred embodiment of the invention, the FPGA chip processor further comprises a temperature control module, a voltage control module and a data processing module,
the temperature control module is used for controlling the temperature acquisition module to operate, acquiring temperature information uploaded by the temperature acquisition module and transmitting the temperature information to the data processing module;
the data processing module calculates the temperature according to the temperature informationBias voltage required for temperature compensation of APD at the previous temperature, and voltage regulation quantity delta V at the current temperature is calculated according to temperature informationAPD；
The voltage control module is used for controlling the voltage regulation module to operate and regulating the voltage by the voltage regulation quantity delta VAPDAnd transmitting to the voltage regulation module.
In a preferred embodiment of the present invention, the voltage adjusting module further comprises an adjustable resistance circuit and a DC-DC boost circuit, wherein the adjustable resistance circuit is controlled by the FPGA chip processor and outputs an adjustable digital resistance; and the output end of the adjustable resistance circuit is connected with the reference voltage input end of the DC-DC booster circuit.
In a preferred embodiment of the present invention, the adjustable resistor circuit further includes one or more adjustable resistor chips, and output terminals of the multiple adjustable resistor chips are connected in parallel and then connected to a reference voltage input terminal of the DC-DC boost circuit.
In a preferred embodiment of the present invention, the control terminal of the adjustable resistor chip is connected to the FPGA chip processor through an I2C bus or a PMbus bus.
In a preferred embodiment of the present invention, the model of the adjustable resistor chip is AD 5293.
In a preferred embodiment of the present invention, the DC-DC boost circuit further comprises a boost module chip having a reference voltage input terminal (V)REF) And the output end of the adjustable resistance circuit is connected and changes the output voltage according to the resistance change output by the adjustable resistance circuit.
In a preferred embodiment of the invention, the model of the boost module chip is DW-P301-1B 45.
In a preferred embodiment of the present invention, the temperature acquisition module further includes a temperature sensor chip mounted on the APD, and a control terminal of the temperature sensor chip is connected to the FPGA chip processor through an I2C bus or a PMbus bus.
In a preferred embodiment of the present invention, the model of the temperature sensor chip is TMP 117.
The invention has the beneficial effects that:
firstly, the voltage type open loop temperature-dependent regulation system based on the FPGA chip for carrying out temperature compensation on the APD of the laser radar in the embodiment of the invention improves the measurement precision of the laser radar through temperature-dependent regulation and reduces the sensitivity of the measurement precision of the laser radar to temperature: the temperature acquisition module acquires the temperature of the APD in real time and feeds the temperature back to the FPGA chip processor, the FPGA chip processor outputs a voltage regulation signal according to the temperature value, the voltage regulation module generates an output voltage used as an APD bias voltage and regulates the output voltage according to the voltage regulation signal of the FPGA chip processor, so that the regulated output voltage V isAPDThe bias voltage is the same as that of the APD under temperature compensation, so that the bias voltage of the APD is adjusted in real time according to the temperature of the APD, and the APD works at constant gain.
And the FPGA chip processor, the temperature acquisition module and the voltage regulation module are all composed of low-voltage and digital circuits matched with an integrated chip, the energy loss is small (lower than 1.5 percent of the energy consumption of a product), the voltage is regulated stably along with the temperature, the regulation precision is high, the response is fast, the regulation voltage ripple is small, and the oscillation in the regulation process is small.
Drawings
FIG. 1 is a circuit block diagram of a voltage-type open-loop temperature-dependent regulation system based on an FPGA chip according to an embodiment of the present invention;
FIG. 2 is a block diagram of the internal structure of an FPGA chip processor;
FIG. 3 is an internal circuit diagram of a DC-DC boost circuit in an embodiment of the present invention;
FIG. 4 is a linear relationship diagram of the control voltage and the output voltage of the boost module chip in the embodiment of the present invention;
FIG. 5 is a write byte command timing diagram of the TMP 117;
FIG. 6 is a timing diagram of a read byte command of the TMP 117;
FIG. 7 is a timing diagram of a system management bus alert;
fig. 8 is a timing diagram of the TMP117 broadcast call reset command.
Detailed Description
The present invention is further described below in conjunction with the following figures and specific examples so that those skilled in the art may better understand the present invention and practice it, but the examples are not intended to limit the present invention.
Here, the following are to be explained: an Avalanche Photodiode (APD) is a p-n junction-type light-detecting diode that, when applied in a laser receiver circuit of a lidar, utilizes the breakdown voltage V of the APDBRThe avalanche multiplication effect of the down carriers is used for gaining and amplifying the photoelectric signal so as to improve the detection sensitivity. In practical application, the change of the environmental temperature has great influence on the characteristics of the APD, and when the temperature rises, the breakdown voltage V of the APD increasesBRAlso, as the voltage increases, if the operating voltage (or "bias voltage") of the APD is not changed, the photodetection performance of the APD is weakened, and the sensitivity is reduced.
In the technical scheme of the embodiment, a laser receiving circuit of the 60-meter laser radar is designed, and a photodiode (namely APD) with the model of APD500-9 is adopted, so that the temperature is sensitive, and the performance of the laser receiving circuit is closely related to the measurement accuracy.
The parameters of APD500-9 are shown in Table 1 below:
TABLE 1 APD500-9 parameters
Electro-optical characteristics@23℃
As shown in Table 1, breakdown voltage V of APDBRThe bias voltage V increases with increasing temperaturebiasWill increase, for example: breakdown voltage V of APD at 23 deg.CBR200V, and a breakdown voltage V of 1 ℃ when the temperature is increased by 1℃ under the condition of a temperature coefficient of 1.5BRThe increase is 1.5V; conversely, the temperature is reduced by 1 ℃ and the breakdown voltage V is reducedBRThe reduction was 1.5V.
GAIN GAIN and bias voltage V of APD500-9biasBreakdown voltage VBRThe relationship of (a) is as follows:
when GAIN is 100, Vbias＝0.92*VBR(a gain of 100 is used in design);
when GAIN is 50, Vbias＝0.8*VBR；
When GAIN is 30, Vbias＝0.7*VBR。
Based on this, in order to ensure that the APD is stabilized at a fixed gain value (for example, 100) when the temperature changes, the bias voltage of the APD needs to be controlled and adjusted when the laser receiving circuit of the laser radar is designed.
In order to adjust the bias voltage of the APD with temperature, the embodiment discloses a voltage type open loop temperature-dependent adjustment system based on an FPGA chip, which is shown in fig. 1 and comprises an FPGA chip processor, a temperature acquisition module and a voltage adjustment module,
the temperature acquisition module is used for acquiring the temperature of the APD in real time and transmitting the temperature to the FPGA chip processor;
the voltage regulating module generates output voltage used as APD bias voltage, is controlled by the FPGA chip processor, and regulates the output voltage V according to the voltage regulating signal of the FPGA chip processorAPDSo that the regulated output voltage VAPDThe bias voltage required by the APD under temperature compensation is the same; here, the bias voltage required by the APD under temperature compensation is the bias voltage required to ensure its fixed gain.
The FPGA chip processor receives the temperature signal output by the temperature acquisition module and generates the voltage regulation signal according to the temperature signal.
Specifically, the FPGA chip processor implements logic operation and data processing based on an internal programmable logic circuit, as shown in fig. 2, and includes a temperature control module, a voltage control module, and a data processing module,
the temperature control module is used for controlling the temperature acquisition module to operate, acquiring temperature information uploaded by the temperature acquisition module and transmitting the temperature information to the data processing module;
the data processing module calculates bias voltage required for temperature compensation of the APD at the current temperature according to the temperature information, and calculates voltage regulating quantity delta V at the current temperature according to the temperature informationAPD；
The voltage control module is used for controllingThe voltage regulation module operates to regulate the voltage by the voltage regulation amount delta VAPDAnd transmitting to the voltage regulation module.
In the technical solution of this embodiment, the FPGA chip module preferably uses a chip with a model number of 10M25DAF484 CBG.
The temperature acquisition module comprises a temperature sensor chip attached to an APD (avalanche photo diode) and the technical scheme of the embodiment selects the temperature sensor chip with the model of TMP117 of a TI company, and the precision is as follows:
0.1 deg.C (maximum) at 20 deg.C to +50 deg.C, and resolution of 0.0078125;
within the range of 40 ℃ to +70 ℃ plus or minus 0.15 ℃ (maximum)
Within the range of 40 ℃ to +100 ℃ plus or minus 0.2 ℃ (maximum)
Within the range of 55 ℃ to +125 ℃ plus or minus 0.25 ℃ (maximum)
Within the range of 55 ℃ to +150 ℃ is. + -. 0.3 ℃ C (maximum).
The temperature sensor chip is mounted as close to the APD as possible in structure to more accurately detect the temperature of the APD. The temperature sensor chip is connected with the FPGA chip processor by an I2C bus or a PMbus bus, and transmits the detected temperature of the APD to the FPGA chip processor.
In the present embodiment, the APD is preferably a photodiode of type AD500-9, the temperature coefficient of AD500-9 is 1.5, and when the design GAIN is 100, the bias voltage V is determined by the inherent characteristic of AD500-9biasAnd breakdown voltage VBRThe relationship of (a) to (b) is as follows:
Vbias＝0.92*[VBR+(T-23)]1.5 (equation 1);
wherein the temperature range of T is an industrial-grade temperature range, namely-40 ℃ to +85 ℃.
The working environment temperature of the laser radar is-40 ℃ to +85 ℃, the delta T is 125, and the variable quantity delta V of the bias voltage of the APD under different temperatures is calculated and obtained according to the formula 1biasComprises the following steps:
ΔVbiasΔ T1.5 × 0.92 (equation 2).
If the temperature of the APD working environment is-40-85 ℃, the temperature coefficient is 1.5, VBRAt 200V, the APD bias voltage V is calculated according to equation (1)biasThe range of (A) is as follows:
bias voltage VbiasMinimum value VL＝0.92*[200+(-40-23)*1.5]＝97.06V；
Bias voltage VbiasMinimum value VH＝0.92*[200+(85-23)*1.5]＝269.56V。
The invention aims to control the output voltage V generated by a DC-DC boosted circuit to operate a voltage type open-loop temperature-dependent regulation system based on an FPGA chip-APDBias voltage V required for temperature compensation with APDbiasSimilarly, here, the bias voltage required by the APD under temperature compensation is the bias voltage required to ensure its fixed gain.
In the technical solution of this embodiment, the voltage regulation module includes an adjustable resistor circuit and a DC-DC boost circuit, and as shown in fig. 3, the DC-DC boost circuit is a resistor control voltage type circuit, which has a boost module chip, and preferably uses an eastern high voltage DW-P301-1B45 module, whose input voltage is DC9V, output voltage is adjustable from 0V to 300V, and output current is 1 mA. Wherein Vref is an internal 5V reference voltage, W is an adjustable resistor, and V2 is a control voltage, and the module adopts a resistor to control the linear output of the output voltage, as shown in fig. 4.
The output terminal of the adjustable resistance circuit is connected with the reference voltage input terminal of the DC-DC booster circuit, and the adjustable resistance circuit generates an adjustable digital resistance which is used as an adjustable resistance W shown in figure 3.
In one implementation technical solution of this embodiment, the adjustable resistance circuit includes an adjustable resistance chip; in another embodiment, the adjustable resistor circuit includes multiple adjustable resistor chips, for example, two adjustable resistor chips, and the output ends of the multiple adjustable resistor chips are connected in parallel and then connected to the reference voltage input end V of the boost module chipREF。
In the technical scheme of this embodiment, the adjustable resistor chip preferably uses a digital adjustable resistor AD5293 BRUZ-20 of ADI corporation, the resistance value of the adjustable resistor is 20K, the resolution is 1024, the precision of the adjustable resistor is 1%, and the adjustment step is 20000/1023 Ω -19.55 Ω; and the control end of the adjustable resistance chip is connected with the FPGA chip processor through an I2C bus or a PMbus bus.
Under the condition that the adjustable resistance circuit comprises one path of adjustable resistance chip:
the AD5293 BRUZ-20 outputs an adjustable digital resistor 20K which is used as an adjustable resistor W of a high-voltage DW-P301-1B45 module, and the adjusting step of the AD5293 BRUZ-20 is 20000/1023 omega, so that the voltage adjusting resolution of the high-voltage DW-P301-1B45 module is as follows:
the accuracy of the temperature sensor chip TMP117 is +/-0.1 ℃ in the range of 20 ℃ to +50 ℃, and the resolution is 0.0078125.
According to equation 2, when the voltage changes by a minimum step, the corresponding temperature change is:
that is, when the temperature changes by 25 minimum units (close to 0.2 ℃), the primary bias voltage is adjusted (or the output voltage of the DW-P301-1B45 module is adjusted by adjusting the resistance output of the AD5293 BRUZ-20), and the adjustment amplitude is 0.293V.
For example, the following steps are carried out:
breakdown voltage V of APD when laser radar works in 23 ℃ environmentBR200V, gain of 100M, and bias voltage V required at 23 deg.Cbias0.92 × 200 ═ 184V; at this time, the resistance value that ADI AD5293 needs to output is calculated according to the following equation 3:
wherein D is the decimal equivalent of the binary code AD5293 loaded in the 10-bit RDAC register;
RAB＝20K
RWB is the value of the end W and the end B of the adjustable resistor;
RWA is the value of the end W and the end B of the adjustable resistor;
RAB is the total value of the adjustable resistance W.
At 23 deg.C, D184X 1024/300 ≈ 628
If the temperature rises to 40 ℃, the currently required bias voltage is calculated according to equation 1 as:
Vbias＝[200+1.5×(40-23)]×0.92＝207.46V。
the required D values at this time are: d207.46 × 1024/300 ≈ 708.
The resistance value output from AD5293 is calculated according to equation (3).
In the technical scheme of the embodiment of the invention, the development process of the FPGA chip processor comprises the following contents:
(1) typical configuration for I2C;
(2) reference clock setting or validation;
(3) analyzing data;
(4) interpreting a basic state;
(5) implementation of a logic formula.
The contents to be specifically explained are as follows:
1. TMP117 is 2 line interfaces, compatible I2C, clock line SCL, data line SDA, can add an interrupt signal and use as the warning, and the clock supports 1 ~ 400kHz, and the higher is better. The FPGA can count samples with a reference clock, achieving a 400kHz rate for the I2C interface.
2. The TMP117 has an EEPROM built in and the manufacturer writes factory values into it during manufacture. Reconfiguration is not required under normal application. If necessary, the operation is carried out according to an EEPROM programming flow, and after the power-on, parameters such as upper and lower temperature measurement limits, conversion period and the like can be read from the EEPROM and loaded into a register.
3. The temperature value in the TMP117 is stored in a binary complement manner with a precision of 0.0078125 degrees celsius, and table 3 below shows some corresponding parameter values.
According to formula Vbias＝0.92*[VBR+(T-23)]1.5, it can be seen that the value of T has been expanded 27 times, considering the inconvenience of floating point number of FPGA chip processor, so when calculating according to the formula 23 is also expanded 27 times, 1.5 is expanded 2 times, VBRThe magnification is 28 times, and the magnification is 212 times when the magnification is 0.92. Total result VbiasThe magnification is 220 times.
Calculating Δ Vbias＝VbiasAt 165, expand 165 by 220 times, calculateWhen 1.5 is enlarged by 2 times, the value of Delta IDACActually 219 times larger. The corresponding decrease in LTC7106 was again 219 times. The values are stored in 2's complement.
Initialization of table 316 bit temperature data
FIG. 5 shows a write byte command timing diagram of the TMP 117;
FIG. 6 shows a timing diagram of a read byte command of the TMP 117;
FIG. 7 is a timing diagram illustrating a system management bus alert;
fig. 8 is a timing diagram illustrating the TMP117 broadcasting the call reset command.
The above-mentioned embodiments are merely preferred embodiments for fully illustrating the present invention, and the scope of the present invention is not limited thereto. The equivalent substitution or change made by the technical personnel in the technical field on the basis of the invention is all within the protection scope of the invention. The protection scope of the invention is subject to the claims.
Claims (10)
1. The utility model provides a voltage formula open loop is along with temperature governing system based on FPGA chip for carry out temperature compensation to laser radar's APD, its characterized in that: the system comprises an FPGA chip processor, a temperature acquisition module and a voltage regulation module,
the temperature acquisition module is used for acquiring the temperature of the APD in real time and transmitting the temperature to the FPGA chip processor;
the voltage regulating module generates output voltage used as APD bias voltage, is controlled by the FPGA chip processor, and regulates the output voltage V according to the voltage regulating signal of the FPGA chip processorAPDSo that the regulated output voltage VAPDThe bias voltage required by the APD under temperature compensation is the same;
the FPGA chip processor receives a temperature signal output by the temperature acquisition module and generates the voltage regulation signal according to the temperature signal;
the FPGA chip processor realizes logic operation and data processing based on an internal programmable logic circuit.
2. The FPGA chip based voltage open loop temperature dependent regulation system of claim 1 wherein: the FPGA chip processor comprises a temperature control module, a voltage control module and a data processing module,
the temperature control module is used for controlling the temperature acquisition module to operate, acquiring temperature information uploaded by the temperature acquisition module and transmitting the temperature information to the data processing module;
the data processing module calculates bias voltage required for temperature compensation of the APD at the current temperature according to the temperature information, and calculates voltage regulating quantity delta V at the current temperature according to the temperature informationAPD；
The voltage control module is used for controlling the voltage regulation module to operate and regulating the voltage by the voltage regulation quantity delta VAPDAnd transmitting to the voltage regulation module.
3. The FPGA chip based voltage open loop temperature regulated system of claim 1 or 2 wherein: the voltage regulating module comprises an adjustable resistance circuit and a DC-DC booster circuit, and the adjustable resistance circuit is controlled by the FPGA chip processor and outputs an adjustable digital resistance; and the output end of the adjustable resistance circuit is connected with the reference voltage input end of the DC-DC booster circuit.
4. The FPGA chip-based voltage-type open-loop temperature-dependent regulation system of claim 3, wherein: the adjustable resistance circuit comprises one or more adjustable resistance chips, and the output ends of the multiple adjustable resistance chips are connected in parallel and then connected with the reference voltage input end of the DC-DC booster circuit.
5. The FPGA chip-based voltage-type open-loop temperature-dependent regulation system of claim 4, wherein: and the control end of the adjustable resistance chip is connected with the FPGA chip processor through an I2C bus or a PMbus bus.
6. The FPGA chip-based voltage-type open-loop temperature-dependent regulation system of claim 4, wherein: the model of the adjustable resistance chip is AD 5293.
7. The FPGA chip-based voltage-type open-loop temperature-dependent regulation system of claim 3, wherein: the DC-DC booster circuit comprises a boost module chip, a reference voltage input end (V) of whichREF) And the output end of the adjustable resistance circuit is connected and changes the output voltage according to the resistance change output by the adjustable resistance circuit.
8. The FPGA chip based voltage open loop temperature dependent regulation system of claim 7 wherein: the model of the boosting module chip is DW-P301-1B 45.
9. The FPGA chip based voltage open loop temperature regulated system of claim 1 or 2 wherein: the temperature acquisition module comprises a temperature sensor chip attached to an APD (avalanche photo diode) and a control end of the temperature sensor chip is connected with the FPGA (field programmable gate array) chip processor through an I2C bus or a PMbus.
10. The FPGA chip based voltage open loop temperature dependent regulation system of claim 9 wherein: the model of the temperature sensor chip is TMP 117.
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| CN201911002283.2A CN110596682A (en) | 2019-10-21 | 2019-10-21 | Voltage type open-loop temperature-dependent adjusting system based on FPGA chip |
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