CN110596667A

CN110596667A - Array type sensor based counting system, counting method and array type sensor

Info

Publication number: CN110596667A
Application number: CN201910880325.6A
Authority: CN
Inventors: 雷述宇
Original assignee: Ningbo Feixin Electronic Technology Co Ltd
Current assignee: Ningbo Feixin Electronic Technology Co Ltd
Priority date: 2019-09-18
Filing date: 2019-09-18
Publication date: 2019-12-20

Abstract

The disclosure provides a counting system and a counting method based on an array type sensor and the array type sensor, and relates to the technical field of microelectronics. The system comprises: the method comprises the following steps: the output end of the storage array is connected with the first input end of the calculation module, the output end of the calculation module is connected with the input end of the storage array, the calculation module is used for counting based on output signals of a plurality of array units to obtain an accumulated count value corresponding to each array unit, and storing the accumulated count value corresponding to each array unit into the storage array, and the storage array is used for storing the accumulated count value of each array unit. The present disclosure can save an array unit area in an array type sensor.

Description

Array type sensor based counting system, counting method and array type sensor

Technical Field

The present disclosure relates to the field of microelectronic technologies, and in particular, to a counting system and a counting method based on an array sensor, and an array sensor.

Background

With the development of microelectronic technology, array sensors such as image sensors are widely used in various fields. The array sensor includes a plurality of array units, each array unit may receive external signals such as optical signals, acoustic signals, and the like, and output a corresponding output signal, and in the operation process of the array sensor, it is usually necessary to count the output signals of each array unit before performing subsequent other processing.

In the prior art, a counter is provided for each array unit, so that the counting process for each array unit is completed by each counter. However, in the prior art, the corresponding counter is required to be arranged for each array unit, which results in wasted area of the array unit and brings difficulty in manufacturing the array type sensor with smaller volume.

Disclosure of Invention

The present disclosure provides a counting system, a counting method and an array sensor based on an array sensor, so as to save the area of an array unit in the array sensor.

In order to achieve the above purpose, the technical scheme adopted by the disclosure is as follows:

in a first aspect, the present disclosure presents an array-type sensor-based counting system comprising: the output end of the storage array is connected with the first input end of the calculation module, and the output end of the calculation module is connected with the input end of the storage array;

the calculation module is used for counting based on output signals of a plurality of array units to obtain an accumulated count value corresponding to each array unit, and storing the accumulated count value corresponding to each array unit to the storage array;

the storage array is used for storing the accumulated count value of each array unit.

Optionally, the calculating module is configured to count according to a counting rule corresponding to the output signal of each array unit and the output signal of each array unit, so as to obtain an accumulated count value of each array unit.

Optionally, the computing module comprises at least one type of computing unit;

and the calculating unit is used for counting according to the counting rule corresponding to the calculating unit and the output signal of the array unit if the output signal of the array unit is received, so as to obtain the accumulated count value of the array unit.

Optionally, the array type sensor comprises an image sensor, the array unit comprises pixels, the output signal comprises a first electrical signal corresponding to a mixed signal comprising the reference signal and a target signal and/or a second electrical signal corresponding to a reference signal.

Optionally, the calculation module comprises an addition unit and/or a subtraction unit;

the adding unit is used for receiving the first electric signal of the pixel and performing accumulation counting based on the first electric signal; and/or the subtraction unit is configured to receive the second electrical signals of the pixels, perform count-down based on the second electrical signals of each of the pixels, and obtain an accumulated count value of the pixels.

Optionally, the image sensor further includes a voltage comparator connected to each of the pixels, where each of the pixels includes a first capacitor and a second capacitor, and the voltage comparator is configured to compare a voltage generated by the first capacitor based on the mixed signal with a preset voltage to obtain the first electrical signal, and compare a voltage generated by the second capacitor based on the reference signal with the preset voltage to obtain the second electrical signal;

the adding unit is also used for performing accumulation counting based on the first electric signal; and/or the subtraction unit is further configured to perform a count-down process based on the second electrical signal to obtain an accumulated count value of the pixel.

Optionally, the storage array includes a plurality of storage units, and the storage unit is configured to store the accumulated count value of the array unit.

Optionally, the system further includes at least one row selection signal controller, the memory array includes one memory module or a plurality of cascaded memory modules, each memory module includes a plurality of memory cells, and each row selection signal controller is connected to each memory cell in the corresponding memory module;

the at least one row selection signal controller is used for sequentially gating each storage unit in the at least one storage module according to a cascade sequence;

the storage unit is used for updating the currently stored value to the value stored in the previous storage unit cascaded with the storage unit or the value output by the calculation module if the storage unit is gated.

Optionally, if the storage array includes a plurality of cascaded storage modules, each storage module includes at least one first storage unit and at least one second storage unit, each first storage unit corresponds to one array unit and stores an accumulated count value corresponding to the corresponding array unit, and each second storage unit is used for sharing a cache.

Optionally, each of the memory modules includes the same number of the first memory cells and the same number of the second memory cells.

Optionally, the first storage unit and the second storage unit in each of the storage modules have the same cascade order.

Optionally, the system includes one row selection signal controller, where each row selection signal line of the row selection signal controller is connected to the first storage unit or the second storage unit at the same position in each storage module respectively;

the row selection signal controller is configured to sequentially control gating of the first storage unit or the second storage unit at the same position in each storage module according to a preset period through the plurality of row selection signal lines.

Optionally, each of the storage units includes a plurality of latches, and each of the latches is cascaded with any one of the latches in the adjacent storage unit.

Optionally, the computation module includes a plurality of computation sub-modules, and each latch in the last row of the storage array is connected to any latch in the first row of the storage array through the computation sub-module.

Optionally, the system further includes a column selection signal controller, an output end of each of the storage units is connected to the first input end of the computing module, an input end of each of the storage units is connected to an output end of the computing module, a switch is connected in series between each of the storage units and the computing module, and the column selection signal controller is connected to the switches between each of the storage units and the computing module;

the column selection signal controller is used for controlling the opening and closing of the switches between the storage units and the computing module according to a preset sequence;

each storage unit is used for sending the stored accumulated count value to the calculation module and receiving the updated accumulated count value calculated by the calculation module.

Optionally, the system further includes a bus connected to the storage array, and the bus is configured to read and output data in the storage array.

In a second aspect, the present disclosure provides an array-type sensor-based counting method, which is applied to an array-type sensor-based counting system, the system including: the method comprises the following steps that an output end of the storage array is connected with a first input end of a computing module, and an output end of the computing module is connected with an input end of the storage array, and the method comprises the following steps:

the calculation module is used for counting based on output signals of a plurality of array units to obtain an accumulated count value corresponding to each array unit and storing the accumulated count value corresponding to each array unit to the storage array;

the storage array stores the accumulated count value of each array unit.

Optionally, the calculating module counts according to a counting rule corresponding to the output signal of each array unit and the output signal of each array unit to obtain an accumulated count value of each array unit.

Optionally, the computing module comprises at least one type of computing unit; the method further comprises the following steps:

and if the computing unit receives the output signal of the array unit, counting according to the counting rule corresponding to the computing unit and the output signal of the array unit to obtain the accumulated count value of the array unit.

Optionally, the calculation module comprises an addition unit and/or a subtraction unit; the method further comprises the following steps:

the addition unit receives the first electric signal of the pixel and performs accumulation counting based on the first electric signal; and/or the subtraction unit receives the second electrical signals of the pixels, performs count-down based on the second electrical signals of each pixel, and obtains an accumulated count value of the pixels.

Optionally, the image sensor further comprises a voltage comparator connected to each of the pixels, the pixels comprising a first capacitance and a second capacitance, the method further comprising:

the voltage comparator compares the voltage generated by the first capacitor based on the mixed signal with a preset voltage to obtain the first electric signal, and compares the voltage generated by the second capacitor based on the reference signal with the preset voltage to obtain the second electric signal;

the adding unit is used for performing accumulation counting based on the first electric signal; and/or the subtraction unit performs cumulative subtraction counting based on the second electric signal to obtain a cumulative count value of the pixel.

Optionally, the system further includes at least one row selection signal controller, the memory array includes one memory module or a plurality of cascaded memory modules, each memory module includes a plurality of memory cells, and each row selection signal controller is connected to each memory cell in the corresponding memory module; the method further comprises the following steps:

the row selection signal controller is used for sequentially gating the storage units in the storage module according to a cascade sequence;

and if the storage unit is gated, updating the currently stored numerical value to the numerical value stored by the previous storage unit cascaded with the storage unit, or the numerical value output by the calculation module.

Optionally, the system includes one row selection signal controller, where each row selection signal line of the row selection signal controller is connected to the first storage unit or the second storage unit at the same position in each storage module respectively; the method further comprises the following steps:

and the row selection signal controller sequentially controls the gating of the first storage unit or the second storage unit at the same position in each storage module according to a preset period through a plurality of row selection signal lines.

Optionally, the system further includes a column selection signal controller, an output end of each of the storage units is connected to the first input end of the computing module, an input end of each of the storage units is connected to an output end of the computing module, a switch is connected in series between each of the storage units and the computing module, and the column selection signal controller is connected to the switches between each of the storage units and the computing module; the method further comprises the following steps:

the column selection signal controller controls the opening and closing of the switches between the storage units and the computing module according to a preset sequence;

each storage unit sends the stored accumulated count value to the calculation module and receives the updated accumulated count value calculated by the calculation module.

In a third aspect, the present disclosure also proposes an array-type sensor provided with a counting system as defined in any one of the first aspects.

In the embodiment of the disclosure, the counting system based on the array sensor comprises a storage array and a calculation module, wherein an output end of the storage array is connected with a first input end of the calculation module, an output end of the calculation module is connected with an input end of the storage array, and the calculation module is used for counting based on output signals of a plurality of array units to obtain accumulated count values corresponding to the array units and storing the accumulated count values corresponding to the array units to the storage array.

Additional features and advantages of the disclosure will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by the practice of the disclosure. The objectives and other advantages of the disclosure may be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.

Drawings

To more clearly illustrate the technical solutions of the present disclosure, the drawings needed for the embodiments will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present disclosure, and therefore should not be considered as limiting the scope, and those skilled in the art can also obtain other related drawings based on the drawings without inventive efforts.

FIG. 1 illustrates a schematic structural diagram of an array-type sensor-based counting system provided by the present disclosure;

FIG. 2 illustrates a schematic structural view of another array-type sensor-based counting system provided by the present disclosure;

FIG. 3 illustrates a schematic structural view of another array-type sensor-based counting system provided by the present disclosure;

FIG. 4 illustrates a schematic structural view of another array-type sensor-based counting system provided by the present disclosure;

FIG. 5 illustrates a schematic diagram of a latch provided by the present disclosure;

FIG. 6 illustrates a schematic structural view of another array-type sensor-based counting system provided by the present disclosure;

FIG. 7 illustrates a schematic structural view of another array-type sensor-based counting system provided by the present disclosure;

FIG. 8 illustrates a timing diagram of a row select signal provided by the present disclosure;

FIG. 9 is a schematic diagram illustrating a memory module according to the present disclosure;

FIG. 10 shows a schematic structural diagram of another array-type sensor-based counting system provided by the present disclosure;

FIG. 11 illustrates a schematic structural view of another array-type sensor-based counting system provided by the present disclosure;

FIG. 12 illustrates a schematic structural view of another array-type sensor-based counting system provided by the present disclosure;

FIG. 13 illustrates a flow diagram of an array-type sensor-based counting method provided by the present disclosure;

FIG. 14 is a schematic diagram illustrating a memory state of a memory array provided by the present disclosure;

FIG. 15 illustrates a schematic diagram of memory states of another memory array provided by the present disclosure;

FIG. 16 illustrates a schematic diagram of a memory state of another memory array provided by the present disclosure.

Reference numbers: 100-a memory array; 110-a storage unit; 111-a first storage unit; 112-a second storage unit; 120-latch; 121-a switch; 122-an inverter; 130-a storage module; 200-a calculation module; 210-a calculation unit; 220-an addition unit; 230-a subtraction unit; 240-half adder; 250-a half-reducer; 260-a calculation submodule; 300-a voltage comparator; 400-row select signal controller; 500-column select signal controller; 600-bus.

Detailed Description

The technical solution in the present disclosure will be clearly and completely described below with reference to the accompanying drawings in the present disclosure.

It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures.

Before explaining the present disclosure in detail, an application scenario of the present disclosure will be described.

The array sensor may be classified according to sensing principles, and may include, for example, piezoresistive, piezoelectric, photoelectric, capacitive, and electromagnetic array sensors, which may include a plurality of array elements. Among them, the array unit may be the minimum unit for detecting an external signal in the array type sensor. For example, when the array type sensor is an image sensor, the array unit may be a pixel; when the array type sensor is an acoustic sensor, the array unit may be a microphone.

Because when setting up corresponding counter to every array unit in the array type sensor respectively, can lead to array unit area extravagant, bring the difficulty for making array type sensor that the volume is littleer, consequently, this disclosure provides a counting system based on array type sensor, through a common calculation module of a plurality of array units and storage array, effectively saves array unit area to in order to realize array type sensor of littleer volume.

Referring to fig. 1, a schematic diagram of a counting system based on an array sensor is disclosed. The system comprises: the array comprises a storage array 100 and a calculation module 200, wherein an output end of the storage array 100 is connected with a first input end of the calculation module 200, an output end of the calculation module 200 is connected with an input end of the storage array 100, the calculation module 200 is used for counting based on output signals of a plurality of array units to obtain an accumulated count value corresponding to each array unit, and storing the accumulated count value corresponding to each array unit into the storage array 100, and the storage array 100 is used for storing the accumulated count value of each array unit.

The array type sensor can be provided with at least one counting system, each counting system can count aiming at a plurality of array units, and then counters do not need to be respectively arranged aiming at the array units, so that the area of the array units can be saved, and the more the array units aimed at by one counting system, the more the area of the array units is saved.

The memory array 100 may have a data storage function so that an accumulated count value of a plurality of array units may be stored. The calculation module 200 may have data calculation capability so that the cumulative count of each array element may be realized. The storage array 100 and the calculation module 200 are connected end to end, so that the calculation module 200 can acquire the accumulated count value of each array unit from the storage array 100 in a plurality of cycles, perform accumulation on the basis of the accumulated count value according to the output signal of the array unit, and store the updated accumulated count value into the storage array 100 until the final accumulated count value is obtained.

The calculation module 200 may count each array unit in a time-sharing manner.

The length of the accumulated count value may be Nbit (bits), where N is a positive integer, e.g., N may be 10. Of course, N may be other values in practical applications, and the length of the accumulated count value is not specifically limited in this disclosure.

Alternatively, the calculation module 200 may stop the accumulation when the duration of the accumulation count is greater than or equal to a first preset duration, or stop the accumulation when the number of times of the accumulation count reaches a preset number. Then, the storage array 100 may clear the accumulated count value of the array unit, and the calculation module 200 may accumulate the accumulated count value of each array unit again. Of course, in practical applications, the calculating module 200 may determine the timing of stopping accumulation and re-accumulation in other ways, which is not specifically limited by the present disclosure.

It should be noted that the first preset time or the preset times may be obtained by setting in advance.

It should be noted that, when the counting module 200 starts or restarts counting, the accumulated count value in the storage array 100 may be 0.

In the embodiment of the present disclosure, the counting system based on the array sensor includes a storage array 100 and a calculation module 200, an output end of the storage array 100 is connected to a first input end of the calculation module 200, an output end of the calculation module 200 is connected to an input end of the storage array 100, the calculation module 200 is configured to count based on output signals of a plurality of array units to obtain an accumulated count value corresponding to each array unit, and store the accumulated count value corresponding to each array unit in the storage array 100, and the storage array 100 is configured to store the accumulated count value of each array unit, so that the plurality of array units can share one storage array 100 and the calculation module 200 for counting, and the area of the array unit is saved.

Optionally, on the basis of the counting system, the calculating module 200 is configured to count according to a counting rule corresponding to the output signal of each array unit and the output signal of each array unit, so as to obtain an accumulated count value of each array unit.

Since the array unit may output more than one output signal, and it may be necessary to count in different counting manners for different output signals, in order to improve the reliability of counting, the counting may be performed in the counting manner corresponding to the output signal.

The counting rule is used for indicating a corresponding counting mode, and the corresponding counting rule can be set in advance according to the output signals of the array units.

Optionally, the counting rule may include at least one of accumulation and subtraction, and of course, in practical applications, other counting rules may also be included, and the disclosure does not specifically limit the type of the counting rule.

Optionally, please refer to fig. 2, which is a schematic structural diagram illustrating another array-type sensor-based counting system. Based on the aforementioned counting system, the calculating module 200 includes at least one type of calculating unit 210, and the calculating unit 210 is configured to count according to the counting rule corresponding to the calculating unit 210 and the output signal of the array unit if the output signal of the array unit is received, so as to obtain the accumulated count value of the array unit.

In order to further improve the reliability of counting according to the calculation rule corresponding to the output signal, the calculation module 200 may include at least one type of calculation unit 210, wherein each type of calculation unit 210 may correspond to one calculation rule, and then for the output signal input to the calculation unit 210, the calculation unit 210 may count based on the corresponding calculation rule and the output signal, for example, the calculation module 200 may include, but is not limited to, at least one of two types of calculation units 210, that is, an addition unit 220 for performing addition calculation and a subtraction unit 230 for performing subtraction calculation.

Alternatively, on the basis of the counting system as described above, the array type sensor includes an image sensor, the array unit includes pixels, the output signal includes a first electric signal corresponding to a mixed signal including a reference signal and a target signal and/or a second electric signal corresponding to a reference signal.

When the array unit includes pixels, the mixed signal, the reference signal, and the target signal may all be optical signals, where the reference signal may be a background optical signal, and the target signal may be an imaging optical signal for actual imaging; in the field of radar ranging, the reference signal may be a background light signal, and the target signal may be an echo signal used for obtaining distance information, where the echo signal is a light signal or an electromagnetic wave signal emitted by a radar after being reflected by a detected object. Accordingly, the mixed signal may be a mixed light signal including the background light signal and the imaging light signal. The light signal received by the image sensor during the imaging process is a mixed light signal composed of the imaging light signal and the background light signal, and the background light signal interferes with the imaging quality. In order to separate a target signal from a mixed optical signal and avoid interference of a background optical signal on imaging, in the prior art, a counter corresponding to each pixel is used to count respectively based on a first electrical signal to obtain a first count value and a second electrical signal to obtain a second count value, and then a difference value between the first count value and the second count value is obtained as a count result corresponding to the pixel, so that not only is pixel area wasted, but also data processing efficiency is low. In the present disclosure, the calculating module 200 may count for each pixel based on a counting rule corresponding to the first electrical signal and the second electrical signal of the plurality of pixels, the obtained accumulated count value may represent a target signal, a counter does not need to be set for each pixel, a pixel area is saved, and when the output signal includes the first electrical signal and the second electrical signal, it is not necessary to count for obtaining the first count value and the second count value, and then obtain a difference value between the first count value and the second count value, a partial data processing may be implemented in the counting process, a data processing pressure of other subsequent processing units in the imaging process is relieved, and a data processing efficiency is improved.

It should be noted that, in practical applications, based on the difference of the sensing types of the array type sensors or the difference of the array units, the mixed signal, the reference signal and the target signal may also be other types of signals, such as acoustic signals, etc., where the reference signal may be background noise, and the target signal may be a useful sound signal that needs to be obtained actually, and the application scenarios thereof include, but are not limited to, amplification, transmission, recognition, etc. of the sound signal.

Optionally, please refer to fig. 3, which is a schematic structural diagram illustrating another array-type sensor-based counting system. On the basis of the counting system as described above, the calculation module 200 comprises an adding unit 220 and/or a subtracting unit 230, the adding unit 220 being configured to receive the first electrical signal of the pixel and perform an accumulated count based on the first electrical signal; and/or the subtracting unit 230 is configured to receive the second electrical signals of the pixels, and perform an accumulation count based on the second electrical signals of the pixels to obtain an accumulated count value of the pixels.

Wherein the adding unit 220 may comprise an adder or half-adder 240 and the subtracting unit 230 may comprise a subtractor or half-subtractor 250.

It should be noted that, in practical applications, for each array unit, the adding unit 220 may perform the accumulation counting according to the first electrical signal, and then the subtracting unit 230 performs the accumulation counting based on the accumulated count value obtained by the accumulation counting, of course, in practical applications, the accumulation counting may be performed first and then the accumulation counting is performed, and the order of performing the accumulation counting and the accumulation counting is not specifically limited in the present disclosure.

Optionally, please refer to fig. 4, which is a schematic structural diagram illustrating another array-type sensor-based counting system. Continuing with the image sensor as an example, on the basis of the aforementioned counting system, the image sensor further includes a voltage comparator 300 connected to each pixel, where each pixel includes a first capacitor and a second capacitor, the voltage comparator 300 is configured to compare a voltage generated by the first capacitor based on the mixed signal with a preset voltage to obtain a first electrical signal, and compare a voltage generated by the second capacitor based on the reference signal with the preset voltage to obtain a second electrical signal, the adding unit 220 is further configured to perform an accumulation count based on the first electrical signal, and/or the subtracting unit 230 is further configured to perform an accumulation count based on the second electrical signal to obtain an accumulated count value of the pixel.

Wherein, the output terminal of the voltage comparator 300 can be connected with the second input terminal of the computing module 200.

Taking the example of performing accumulation and then performing accumulation and subtraction, when the voltage comparator 300 compares the voltage generated by the first capacitor in the pixel based on the mixed signal with the preset voltage to obtain the first electrical signal, the adding unit 220 may obtain the accumulated count value of the pixel from the storage array 100, perform accumulation and counting on the accumulated count value based on the first electrical signal, and store the updated accumulated count value in the storage array 100; when the voltage comparator 300 compares the voltage generated by the second capacitor in the pixel based on the reference signal with the preset voltage to obtain the second electrical signal, the subtracting unit 230 may obtain the accumulated count value after accumulation from the storage array 100, subtract the obtained accumulated count value based on the second electrical signal, and store the updated accumulated count value in the storage array 100.

It should be noted that the preset voltage may be set in advance.

Of course, in practical applications, a comparator for comparing other kinds of output signals may be included in the image sensor according to the sensing principle of the array type sensor.

Optionally, on the basis of the counting system as described above, the storage array 100 includes a plurality of storage units 110, and the storage units 110 are used for storing the accumulated count values of the array units.

In order to facilitate storing the accumulated count value of each array unit separately, a plurality of memory units 110 may be included in the memory array 100, and the number of the memory units 110 may be greater than or equal to the number of the array units.

The storage unit 110 may include a plurality of latches 120, and each latch 120 may store a 1-bit value, so that N latches 120 may implement Nbit value storage, and N may be a positive integer.

Optionally, please refer to fig. 5, which is a schematic structural diagram of a latch 120 provided in the present disclosure. On the basis of the counting system as described above, the latch 120 comprises a cascade of a switch 121 and an inverter 122, where D denotes the input of the latch 120,representing the output of latch 120. The inverter 122 may store the input D at the gate terminal when the switch 121 is closed, and the inverter 122 does not store the input D when the switch 121 is open. The switch 121 may be implemented by a Metal-Oxide-Semiconductor (MOS) transistor, and the inverter 122 may be implemented by connecting an N-type MOS transistor and a P-type MOS transistor.

Optionally, please refer to fig. 6, which is a schematic structural diagram illustrating another array-type sensor-based counting system. On the basis of the aforementioned counting system, the system further includes at least one row selection signal controller 400, the memory array 100 includes one memory module 130 or a plurality of cascaded memory modules 130, each memory module 130 includes a plurality of memory cells 110, each row selection signal controller 400 is respectively connected to each memory cell 110 in the corresponding memory module 130, at least one row selection signal controller 400 is used for sequentially gating each memory cell 110 in at least one memory module 130 according to the cascade order, and the memory cells 110 are used for updating the currently stored value to the value stored in the previous memory cell 110 cascaded with the memory cell 110 if the memory cell 110 is gated, or the value output by the computing module 200.

Since the storage array 100 stores the accumulated value of a plurality of array units, and the computing module 200 needs to cycle count each pixel in a time-sharing manner, in order to ensure that each pixel can be sequentially cycle-counted in a time-sharing manner, thereby improving the accuracy and efficiency of counting, the plurality of storage units 110 included in the storage array 100 may be arranged in a cascade manner, when the storage array 100 includes one storage module 130, the storage units 110 in the storage module 130 are cascaded, and when the storage array 100 includes a plurality of storage modules 130, the storage units 110 in each storage module 130 are cascaded, and the plurality of storage modules 130 are also cascaded.

The row selection signal controller 400 may include a plurality of row selection signal lines, and each row selection signal line may be connected to at least one of the memory cells 110, so that the row selection signal controller 400 is connected to the memory cells 110 included in at least one of the memory modules 130 corresponding to the plurality of row selection signal lines, and thus the memory cells 110 connected to the row selection signal line may be gated through any one row selection signal line. Then, through at least one row selection signal controller 400, the memory cells 110 in each memory module 130 can be controlled to sequentially communicate according to the cascade order, and accordingly, the accumulated count values of the plurality of array cells stored in the memory array 100 can be sequentially transferred from the first memory cell 110 to the last memory cell 110, and transmitted to the counting module 200 for counting, and then the updated accumulated count value counted by the counting module 200 is received by the first memory cell 110, and the process is repeated until the counting is finished.

It should be noted that, in fig. 6, only the memory cells 110 included in the first memory module 130 are schematically illustrated, and it is understood that, in practical applications, the memory array 100 may include N memory modules 130, and the row selection signal controller 400, and each memory module 130 may include M memory cells 110, where M and N are positive integers, and the number of the memory cells 110 included in each memory module 130 may be different.

Optionally, please refer to fig. 7, which is a schematic structural diagram illustrating another array-type sensor-based counting system. Based on the counting system as described above, each memory cell 110 includes a plurality of latches 120, and each latch 120 is cascaded with any latch 120 in an adjacent memory cell 110.

As can be seen from the foregoing, the storage unit 110 may include N latches 120 to store the accumulated count value with the length Nbit, and therefore, when the storage units 110 in the storage array 100 are cascaded, each latch 120 in each storage unit 110 may be respectively cascaded with one latch 120 in an adjacent storage unit 110, thereby ensuring that the value of each bit in the accumulated count value can be sequentially shifted in the cascaded order.

Alternatively, as shown in FIG. 7, E₁、E₂、…、E_nEach row select signal line in the array may be connected to a respective latch 120 in a corresponding memory cell 110, so that the respective latch 120 in that memory cell 110 may be controlled to gate.

Optionally, referring to fig. 7, based on the counting system as described above, the calculation module 200 includes a plurality of calculation submodules 260, and each latch 120 in the last row of the storage array 100 is connected to any latch 120 in the first row of the storage array 100 through the calculation submodule 260.

Wherein each computation submodule 260 may include computation units 210 of at least one of the foregoing in parallel, for example, as shown in fig. 7, the computation submodule 260 includes a half adder 240 and a half subtractor 250 in parallel. Taking the counting process as accumulation and accumulation, the latch 120 included in the last storage unit 110 in the storage array 100 may input the stored value to the half adder 240, the half adder 240 inputs the accumulation result to the first storage unit in the storage array 100, after the accumulation counting of the array output signal to be accumulated and the accumulated count value stored in each storage unit 110 is completed, the latch 120 included in the last storage unit 110 in the storage array 100 may input the stored value and the array output signal to be accumulated and reduced to the half subtractor 250, and the half subtractor 250 inputs the accumulation result to the first storage unit in the storage array 100 until the accumulation counting of the accumulated count value stored in each storage unit in the storage array 100 is completed, that is, the accumulated count value after accumulation and accumulation is obtained.

Optionally, please refer to fig. 8, which is a timing diagram of a row selection signal according to the disclosure. The row selection signal controller 400 may sequentially control the row selection signal E every second preset duration T/nns in every preset period Tns (nanoseconds)₁、E₂、…、E_nAnd is at a high level, so as to control the corresponding memory cell 110 in the memory module 130 to be gated, and the gating duration is a third preset duration. Where n is the number of memory cells 110 included in the memory module 130.

When a preset period is over, the data stored in each memory cell 110 stored in the memory module 130 is transferred to the next cascade of memory cells 110.

It should be noted that the preset period, the second preset duration and the third preset duration may be obtained by setting in advance.

It should be further noted that the third preset time period may be less than or equal to the second preset time period, so as to ensure that the row selection signals do not overlap in time.

Optionally, the lengths of the first electrical signal and the second electrical signal are both the same as the length of the accumulated count value, i.e. both are Nbit. The first electrical signal or the second electrical signal of Nbit is respectively input to the N computation submodules 260, the adding unit 220 (for example, the half adder 240 shown in fig. 7) in each computation submodule 260 respectively adds the value of each bit of the first electrical signal to the value of the corresponding latch 120 in the last storage unit 110 of the storage array 100, and if the value of the bit in the first electrical signal is 1, the added value is output to the corresponding latch 120 in the first storage unit 110 of the storage array 100. The subtracting unit 230 (e.g., the subtractor 250 shown in fig. 7) in each computing submodule 260 subtracts the value of the corresponding bit in the second electrical signal from the value of the corresponding latch 120 in the last storage unit 110 of the storage array 100, and outputs the subtracted value to the corresponding latch 120 in the first storage unit 110 of the storage array 100 if the value of the bit in the second electrical signal is 1. Of course, if the value of a bit from the first electrical signal and the second electrical signal is 0, the adding unit 220 or the subtracting unit 230 can directly output the value from the corresponding latch 120 in the last memory cell 110 of the memory array 100 to the corresponding latch 120 in the first memory cell 110 of the memory array 100.

It should be noted that, in order to facilitate the description of the connection manner between the latch 120 included in the memory cell 110 and the memory cell, and the row selection signal controller 400 and the calculation module 200, fig. 7 only shows the case where one memory module 130 is included in the memory array 100, and in practical applications, the memory array 100 may include more memory modules 130.

Optionally, please refer to fig. 9, which is a schematic structural diagram of a memory module 130 provided by the present disclosure. On the basis of the aforementioned counting system, if the storage array 100 includes a plurality of cascaded storage modules 130, each storage module 130 includes at least one first storage unit 111 and at least one second storage unit 112, each first storage unit 111 corresponds to one array unit and stores an accumulated count value corresponding to the corresponding array unit, and each second storage unit 112 is used for sharing the cache.

Since when the storage units 110 in the storage array 100 are cascaded, data stored in the storage units 110 may need to be buffered by an additional storage space when being transferred, in order to ensure that a plurality of accumulated count values stored in the storage array 100 can be sequentially and circularly output to the calculation module 200, thereby completing the accumulated count, and further improving the reliability of the data stored in the storage array 100, each storage module 130 may be provided with a first storage unit 111 and a second storage unit 112.

It should be noted that fig. 9 only shows an example that one memory module 130 includes 2 first memory units 111 and 1 second memory unit 112, and the second memory unit 112 is disposed at the extreme end of the memory module 130, but in practical applications, the number of the first memory units 111, the number of the second memory units 112, and the cascade order of the first memory units 111 and the second memory units 112 included in each memory module 130 may be set in advance in other manners.

Taking the example that the storage array 100 only includes one storage module 130 as shown in fig. 9, at a certain time in the process of accumulation counting, the 2 first storage units 111 respectively store the accumulated count values of the corresponding array units, and the second storage unit 112 is empty, the accumulated count value in the second first storage unit 111 may be first transferred to the second storage unit 112, so as to be output to the calculation module 200, the accumulated count value stored in the first storage unit 111 is then transferred to the second first storage unit 111, then, the first storage unit 111 may receive and store the updated accumulated count value of the calculation module 200, and then complete one time of updating the accumulated count value stored in the second first storage unit 111, by repeating the above steps, the accumulated count of the array units corresponding to the 2 first storage units 111 can be realized.

Optionally, please refer to fig. 10, which is a schematic structural diagram illustrating another array-type sensor-based counting system. On the basis of the counting system, each memory module 130 includes the same number of first memory cells 111 and the same number of second memory cells 112, and the first memory cells 111 and the second memory cells 112 in each memory module 130 have the same cascade order, the system includes a row selection signal controller 400, each row selection signal line of the row selection signal controller 400 is respectively connected to the first memory cells 111 or the second memory cells 112 at the same positions in each memory module 130, and the row selection signal controller 400 is configured to sequentially control the gating of the first memory cells 111 or the second memory cells 112 at the same positions in each memory module 130 according to a preset period through a plurality of row selection signal lines.

In order to reduce the number of row selection signal controllers 400 required, thereby further saving the area of the array unit, each memory module 130 may include the same number of first memory cells 111 and the same number of second memory cells 112, and the cascade order of the first memory cells 111 and the second memory cells 112 is the same, so that each memory module 130 may be controlled by one row selection signal controller.

Wherein, the preset period can be obtained by presetting.

It should be noted that, in practical applications, each memory module 130 may also include only the same number of first memory cells 111 and the same number of second memory cells 112, but the cascade order of the first memory cells 111 and the second memory cells 112 in each memory module 130 may be different, and at this time, each memory module 130 may still be controlled by one row selection signal controller 400, except that each row selection signal line may be connected to the first memory cells 111 or the second memory cells 112 at different positions in each memory module 130.

Optionally, please refer to fig. 11, which is a schematic structural diagram illustrating another array-type sensor-based counting system. On the basis of the counting system, the system further comprises a column selection signal controller 500, an output end of each storage unit 110 is connected with a first input end of the computing module 200, an input end of each storage unit 110 is connected with an output end of the computing module 200, a switch is connected between each storage unit 110 and the computing module 200 in series, the column selection signal controller 500 is connected with the switch between each storage unit 110 and the computing module 200, the column selection signal controller 500 is used for controlling the on and off of the switch between each storage unit 110 and the computing module 200 in sequence, and each storage unit 110 is used for transmitting the stored accumulated count value to the computing module 200 and receiving the updated accumulated count value calculated by the computing module 200.

As shown in fig. 11, the same column selection signal line of the column selection signal controller 500 is connected to two switches corresponding to the same storage unit 110, when the two switches are gated, the storage unit 110 is communicated with the calculation module 200, and the storage unit can input the stored accumulated count value to the calculation module 200 and receive the accumulated count value updated by the calculation module 200. The column select signal controller 500 can sequentially control each memory unit 110 to communicate with the computing module 200, thereby ensuring time sharing of each memory unit 110 to the computing module 200.

It should be noted that each memory cell 110 may include a plurality of latches 120, the computing module 200 may include a plurality of computing submodules 260, and each latch 120 may be connected to one computing submodule 260.

Optionally, please refer to fig. 12, which is a schematic structural diagram illustrating another array-type sensor-based counting system. On the basis of the counting system as described above, the system further comprises a bus 600, the bus 600 is connected with the memory array 100, and the bus 600 is used for reading and outputting data in the memory array 100.

To facilitate reading the accumulated count value for each pixel in the memory array 100, the counting system may also include a bus 600. A switch may be disposed between the bus 600 and the memory array 100, and when the counting process is finished, the switch is closed, and the accumulated count value of each pixel in the memory array 100 may be obtained through the bus 600.

The length of the data readable by the bus 600 may be the same as the length of the accumulated count value, i.e., Nbit.

Alternatively, if the memory array 100 includes the first storage unit 111 and the second storage unit 112, the bus 600 may be connected to each first storage unit 111, and correspondingly, the row selection signal controller 400 may be configured to transfer the accumulated count value of each array unit stored in the memory array 100 to the first storage unit 111 corresponding to each array unit.

Fig. 13 is a schematic flow chart illustrating a counting method based on an array sensor according to the present disclosure. The method may be applied to any one of the array-type sensor-based counting systems described above, the system comprising: the memory system comprises a memory array 100 and a calculation module 200, wherein an output end of the memory array 100 is connected with a first input end of the calculation module 200, and an output end of the calculation module 200 is connected with an input end of the memory array 100. It should be noted that the array-type sensor-based counting method according to the present disclosure is not limited by the specific sequence shown in fig. 13 and described below, and it should be understood that, in other embodiments, the sequence of some steps in the array-type sensor-based counting method according to the present disclosure may be interchanged according to actual needs, or some steps may be omitted or deleted. The flow shown in fig. 13 will be explained in detail below.

In step 1301, the calculating module 200 counts based on the output signals of the plurality of array units to obtain an accumulated count value corresponding to each array unit, and stores the accumulated count value corresponding to each array unit in the storage array 100.

In step 1302, the array 100 is stored, and the accumulated count value of each array unit is stored.

Optionally, the calculating module 200 is configured to count according to a counting rule corresponding to the output signal of each array unit and the output signal of each array unit to obtain an accumulated count value of each array unit.

Optionally, the computing module 200 includes at least one type of computing unit 210; the method further comprises the following steps:

the calculating unit 210, upon receiving the output signal of the array unit, performs counting according to the counting rule corresponding to the calculating unit 210 and the output signal of the array unit to obtain an accumulated count value of the array unit.

Alternatively, the array type sensor includes an image sensor, the array unit includes pixels, the output signal includes a first electric signal corresponding to a mixed signal including the reference signal and the target signal and/or a second electric signal corresponding to the reference signal.

Optionally, the calculation module 200 comprises an addition unit 220 and/or a subtraction unit 230; the method further comprises the following steps:

an adding unit 220 receiving the first electric signal of the pixel and performing an accumulation count based on the first electric signal; and/or the subtracting unit 230 receives the second electrical signals of the pixels, and performs cumulative subtraction based on the second electrical signals of the pixels to obtain a cumulative count value of the pixels.

Optionally, the image sensor further comprises a voltage comparator 300 connected to each pixel, the pixel comprising a first capacitance and a second capacitance, the method further comprising:

the voltage comparator 300 compares the voltage generated by the first capacitor based on the mixed signal with a preset voltage to obtain a first electrical signal, compares the voltage generated by the second capacitor based on the reference signal with the preset voltage to obtain a second electrical signal, and the adding unit 220 performs accumulation counting based on the first electrical signal, and/or the subtracting unit 230 performs accumulation counting based on the second electrical signal to obtain an accumulated count value of the pixel.

Optionally, the memory array 100 includes a plurality of memory cells 110, and the memory cells 110 are used for storing the accumulated count values of the array cells.

Optionally, the system further includes at least one row selection signal controller 400, the memory array 100 includes one memory module 130 or a plurality of cascaded memory modules 130, each memory module 130 includes a plurality of memory units 110, and each row selection signal controller 400 is respectively connected to each memory unit 110 in the corresponding memory module 130; the method further comprises the following steps:

at least one row selection signal controller 400, each memory cell 110 in at least one memory module 130 is gated in sequence according to the cascade sequence, the memory cells 110, if the memory cells 110 are gated, the currently stored value is updated to the value stored in the previous memory cell 110 cascaded with the memory cells 110, or the value output by the computation module 200.

Optionally, if the storage array 100 includes a plurality of cascaded storage modules 130, each storage module 130 includes at least one first storage unit 111 and at least one second storage unit 112, each first storage unit 111 corresponds to one array unit and stores an accumulated count value corresponding to the corresponding array unit, and each second storage unit 112 is used for sharing the cache.

Alternatively, each memory module 130 includes the same number of first memory cells 111 and the same number of second memory cells 112.

Optionally, the first storage unit 111 and the second storage unit 112 in each storage module 130 have the same cascade order.

Optionally, the system includes a row selection signal controller 400, and each row selection signal line of the row selection signal controller 400 is respectively connected to the first storage unit 111 or the second storage unit 112 at the same position in each storage module 130; the method further comprises the following steps:

the row selection signal controller 400 is configured to sequentially control the gating of the first storage unit 111 or the second storage unit 112 at the same position in each storage module 130 according to a preset period through a plurality of row selection signal lines.

Optionally, each memory cell 110 includes a plurality of latches 120, and each latch 120 is cascaded with any latch 120 in an adjacent memory cell 110.

Optionally, the calculation module 200 includes a plurality of calculation submodules 260, and each latch 120 in the last row of the storage array 100 is connected to any latch 120 in the first row of the storage array 100 through the calculation submodule 260.

Optionally, the system further includes a column selection signal controller 500, an output end of each storage unit 110 is connected to the first input end of the computing module 200, an input end of each storage unit 110 is connected to an output end of the computing module 200, a switch is connected in series between each storage unit 110 and the computing module 200, and the column selection signal controller 500 is connected to the switch between each storage unit 110 and the computing module 200; the method further comprises the following steps:

the column selection signal controller 500 is configured to control the on/off of the switches between the storage units 110 and the calculation module 200 according to a preset sequence, and each storage unit 110 is configured to send the stored accumulated count value to the calculation module 200 and receive the updated accumulated count value calculated by the calculation module 200.

Optionally, the system further comprises a bus 600, the bus 600 is connected to the memory array 100, and the bus 600 is used for reading and outputting data in the memory array 100.

The implementation manner and the beneficial effects of the relevant steps in the above method embodiments may refer to the relevant description in the foregoing system, and are not described in detail here.

The array-type sensor-based counting method provided by the present disclosure will be described below in conjunction with an array-type sensor-based counting system as shown in fig. 10, taking an image sensor as an example.

Referring to fig. 14-16, schematic diagrams of three memory states of the memory array 100 provided by the present disclosure are shown.

Assuming that the counting system corresponds to 4 pixels, each pixel includes a first capacitor Ci1 and a second capacitor Ci2, where Ci1 is the capacitance for receiving the mixed light signal in the ith pixel, Ci2 is the capacitance for receiving the background light signal in the ith pixel, and i is 1, 2, 3, 4.

The memory array 100 of the counting system includes two memory modules 130, each memory module 130 includes 2 first memory units 111 and 1 second memory unit 112, and the second memory unit 112 is located at the extreme end of the memory module 130. The first memory cells 111 and the 1 second memory cells 112 in the two memory modules 130 are respectively controlled by 3 row selection signals, and each row selection signal controls the first memory cells 111 or the second memory cells 112 at the same position in the two memory modules 130. Assuming that the calculation module 200 in the counting system as shown in fig. 10 comprises an addition unit 220 and a subtraction unit 230, the last second storage unit 112 in the storage array 100 is connected to the first storage unit 111 in the storage array 100 through the addition unit 220 and the subtraction unit 230.

In the counting process, the comparison results of C11, C21, C31 and C41 and the preset voltage are sequentially input to the adding unit 220 for adding, the calculated accumulated count value is fed back to the storage array 100 for storage, then the comparison results of C12, C22, C32 and C42 and the preset voltage are sequentially input to the subtracting unit 230 for subtracting, the subtracting unit 230 subtracts the comparison results of C12, C22, C32 and C42 and the preset voltage from the accumulated count value of each pixel, so that the cycle counting of 8 capacitors is completed, and the accumulated count value of each pixel is obtained, and each accumulated count value represents C11-C12, C21-C22, C31-C32 and C41-C42.

As shown in fig. 14, storage states of the memory array 100 at four times are respectively represented from left to right, Δ C1[0], Δ C2[0], Δ C3[0] and Δ C4[0] respectively represent initial differences of C11[0] and C12[0], C21[0] and C22[0], C31[0] and C32[0], and C41[0] and C42[0], and Δ C1[ i ], Δ C2[ i ], Δ C3[ i ] and Δ C4[ i ] represent a certain accumulated difference in the counting process.

The output result C11[ i ] of the voltage comparator 300]Entering the adding unit 220, a row selection signal E within a preset period₁、E₂、E₃Are high level in sequence, wherein E₁、E₂、E₃Respectively for the first one of the memory modules 130One memory cell 111, the second memory cell 112, and the second first memory cell 111 are gated.

When E is₁At high, Δ C3[ i ] stored in the second memory cell 112 of the first memory module 130]Migrate to the first memory cell 111 in the second memory module 130, Δ C1[ i ] in the second memory cell 112 in the second memory module 130]Through an addition unit with C11[ i ]]Add to obtain Δ C1[ i +1]]And output to the first storage unit 111 in the first storage module 130.

When E is₂When the level is high, Δ C4[ i ] stored in the second first memory cell 111 of the first memory module 130]Migrating to the second memory cell 112 in the first memory module 130, and storing Δ C2[ i ] in the second first memory cell 111 in the second memory module 130]To the second memory unit 112 in the first memory module 130.

When E is₃When the level is high, Δ C1[ i +1] stored in the first storage unit 111 of the first storage module 130]Migrating to the second first storage unit 111 in the first storage module 130, and storing Δ C3[ i ] in the first storage unit 111 in the second storage module 130]And migrate to a second first memory cell 111 in a second memory module 130.

After a preset period, the data in the entire memory array 100 are sequentially changed from Δ C1[ i ], Δ C2[ i ], Δ C3[ i ], Δ C4[ i ] to Δ C2[ i ], Δ C3[ i ], Δ C4[ i ], Δ C1[ i +1] from bottom to top, and are moved forward once as a whole, wherein two memory cells 110 store an intermediate state.

As shown in fig. 15, the storage states of the storage array 100 at seven times are respectively represented from left to right. After four preset periods, Δ C1[ i ], Δ C2[ i ], Δ C3[ i ], and Δ C4[ i ] are sequentially added to the corresponding comparison results and fed back to the storage unit 110 for continuous circulation, the data sequence in the 4 first storage units 111 is changed to Δ C1[ i +1], Δ C2[ i +1], Δ C3[ i +1], and Δ C4[ i +1], after four preset periods, the accumulated count value of the corresponding pixel is still stored in each first storage unit 111, and each accumulated count value is updated once.

As shown in fig. 16, the storage states of the storage array 100 at four times are shown from left to right, respectively. In the fifth to eighth preset periods, the output results C12[ i ], C22[ i ], C32[ i ] and C42[ i ] of the voltage comparator 300 enter the subtraction unit 230, and Δ C1[ i +2] ═ Δ C1[ i ] + (C11[ i ] -C12[ i ]) are obtained. Similarly, Δ C2[ i +2] ═ Δ C2[ i ] + (C21[ i ] -C22[ i ]), Δ C3[ i +2] ═ Δ C3[ i ] + (C31[ i ] -C32[ i ]), Δ C4[ i +2] ═ Δ C4[ i ] + (C41[ i ] -C42[ i ]), and the count is completed and the accumulated count value obtained by the count is stored in the latch and read out through the bus 600.

It should be noted that, if the image sensor is replaced by another sensor, the implementation manner is similar, and the difference lies in the difference of the internal array unit, taking the sound sensor as an example, the pixels in the above embodiments may be replaced by microphones, and details are not described here.

The present disclosure also proposes an array type sensor provided with a counting system of any of the foregoing.

The array-type sensor can have the same beneficial effects as the array-type sensor-based counting system, and the description is omitted here.

These above modules may be one or more integrated circuits configured to implement the above methods, such as: one or more Application Specific Integrated Circuits (ASICs), or one or more microprocessors (DSPs), or one or more Field Programmable Gate Arrays (FPGAs), among others. For another example, when one of the above modules is implemented in the form of a processing element scheduler code, the processing element may be a general-purpose processor, such as a Central Processing Unit (CPU) or other processor capable of calling program code. For another example, these modules may be integrated together and implemented in the form of a system-on-a-chip (SOC).

In the several embodiments provided in the present disclosure, it should be understood that the above-described apparatus embodiments are merely illustrative, and the disclosed apparatus and method may be implemented in other ways. For example, the division of the unit is only a logical function division, and in actual implementation, there may be another division manner, for example, multiple units or components may be combined or may be integrated into another system, or some features may be omitted, or may not be executed, for example, each unit may be integrated into one processing unit, each unit may exist alone physically, or two or more units may be integrated into one unit. The integrated unit can be realized in a form of hardware, or in a form of hardware plus a software functional unit.

It is noted that, in this document, relational terms such as "first" and "second," and the like, may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.

The above description is only a preferred embodiment of the present disclosure and is not intended to limit the present disclosure, and various modifications and changes may be made to the present disclosure by those skilled in the art. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present disclosure should be included in the protection scope of the present disclosure.

Claims

1. An array-type sensor-based counting system, comprising: the output end of the storage array is connected with the first input end of the calculation module, and the output end of the calculation module is connected with the input end of the storage array;

2. The system of claim 1, wherein the calculating module is configured to count according to a counting rule corresponding to the output signal of each array unit and the output signal of each array unit to obtain an accumulated count value of each array unit.

3. The system of claim 2, wherein the computing modules comprise at least one type of computing unit;

4. The system of claim 1, wherein the array-type sensor comprises an image sensor, the array elements comprise pixels, the output signal comprises a first electrical signal corresponding to a mixed signal and/or a second electrical signal corresponding to a reference signal, the mixed signal comprising the reference signal and a target signal.

5. The system of claim 4, wherein the calculation module comprises an addition unit and/or a subtraction unit;

6. The system of claim 5, wherein the image sensor further comprises a voltage comparator connected to each of the pixels, the pixels comprising a first capacitor and a second capacitor, the voltage comparator for comparing a voltage generated by the first capacitor based on the mixed signal with a preset voltage to obtain the first electrical signal, and comparing a voltage generated by the second capacitor based on the reference signal with the preset voltage to obtain the second electrical signal;

7. The system of any of claims 1-6, wherein the storage array comprises a plurality of storage cells for storing a cumulative count value for the array cells.

8. The system of claim 7, further comprising at least one row select signal controller, wherein the memory array comprises one memory module or a plurality of cascaded memory modules, each memory module comprises a plurality of memory cells, and each row select signal controller is connected to each memory cell in the corresponding memory module;

9. The system according to claim 8, wherein if the storage array comprises a plurality of cascaded storage modules, each storage module comprises at least one first storage unit and at least one second storage unit, each first storage unit corresponds to one array unit and stores an accumulated count value corresponding to the corresponding array unit, and each second storage unit is used for sharing a cache.

10. The system of claim 9, wherein each of the memory modules includes a same number of the first memory cells and a same number of the second memory cells.

11. The system of claim 10, wherein the first storage unit and the second storage unit in each of the storage modules are in the same order of cascade.

12. The system of claim 11, including one of said row select signal controllers, each row select signal line of said row select signal controller being connected to a same location of said first memory cell or said second memory cell in each of said memory modules, respectively;

13. The system of claim 8, wherein each of said storage cells includes a plurality of latches, each of said latches being cascaded with any of said latches in adjacent ones of said storage cells.

14. The system of claim 13, wherein said computation module includes a plurality of computation submodules, each of said latches in a last row of said storage array being connected to any of said latches in a first row of said storage array via said computation submodule, respectively.

15. The system of claim 7, further comprising a column selection signal controller, wherein an output terminal of each of the storage units is connected to the first input terminal of the computing module, an input terminal of each of the storage units is connected to an output terminal of the computing module, and a switch is connected in series between each of the storage units and the computing module, and the column selection signal controller is connected to the switch between each of the storage units and the computing module;

16. The system of claim 1, further comprising a bus coupled to the memory array, the bus configured to read and output data in the memory array.

17. A method for array-based sensor counting, the method being applied to an array-based sensor counting system, the system comprising: the method comprises the following steps that an output end of the storage array is connected with a first input end of a computing module, and an output end of the computing module is connected with an input end of the storage array, and the method comprises the following steps:

the storage array stores the accumulated count value of each array unit.

18. An array-type sensor, characterized in that it is provided with a counting system according to any one of claims 1-16.