CN110572960A - Method for testing interlayer alignment degree of PCB inner-layer plate - Google Patents

Method for testing interlayer alignment degree of PCB inner-layer plate Download PDF

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Publication number
CN110572960A
CN110572960A CN201910777207.2A CN201910777207A CN110572960A CN 110572960 A CN110572960 A CN 110572960A CN 201910777207 A CN201910777207 A CN 201910777207A CN 110572960 A CN110572960 A CN 110572960A
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CN
China
Prior art keywords
test pad
layer
inner layer
film
coordinates
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201910777207.2A
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Chinese (zh)
Inventor
胡荫敏
彭卫红
荣孝强
罗练军
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Zhuhai Chong Da Circuit Technology Co Ltd
Shenzhen Suntak Multilayer PCB Co Ltd
Original Assignee
Zhuhai Chong Da Circuit Technology Co Ltd
Shenzhen Suntak Multilayer PCB Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Zhuhai Chong Da Circuit Technology Co Ltd, Shenzhen Suntak Multilayer PCB Co Ltd filed Critical Zhuhai Chong Da Circuit Technology Co Ltd
Priority to CN201910777207.2A priority Critical patent/CN110572960A/en
Publication of CN110572960A publication Critical patent/CN110572960A/en
Pending legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0266—Marks, test patterns or identification means
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
    • H05K3/4638—Aligning and fixing the circuit boards before lamination; Detecting or measuring the misalignment after lamination; Aligning external circuit patterns or via connections relative to internal circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/16—Inspection; Monitoring; Aligning
    • H05K2203/163—Monitoring a manufacturing process

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

The invention relates to the technical field of circuit board production and manufacturing, in particular to a method for testing interlayer alignment of a PCB inner layer board. The invention sets a pair of non-coincident test PAD patterns at the same angle of the top layer and the bottom layer of the inner layer plate, and calculates the design deviation values of the pair of test PAD patterns in the X direction and the Y direction; forming a test PAD corresponding to the pair of test PAD patterns on the bottom layer and the top layer of the inner layer plate after etching; calculating actual measurement deviation values of the test PAD in the X direction and the Y direction, and comparing the actual measurement deviation values with design deviation values in the X direction and the Y direction respectively to accurately calculate the deviation between the circuits of the top layer and the bottom layer of the inner layer plate; meanwhile, the method does not relate to subjective judgment of testers, so that errors caused by the subjective judgment of the testers can be avoided, and the test result has good repeatability and is more objective and reliable.

Description

Method for testing interlayer alignment degree of PCB inner-layer plate
Technical Field
The invention relates to the technical field of circuit board production and manufacturing, in particular to a method for testing interlayer alignment of a PCB (printed circuit board) inner layer board.
Background
In the production of the PCB, in each process step of fabricating the inner layer circuit on the inner layer board, the circuit formed on the inner layer board may be deviated due to an error in pattern transfer, expansion and contraction of the board, and the like, so that the circuits on the front and back sides of the inner layer board have alignment deviation, and therefore, the interlayer alignment degree of the patterns/circuits on the upper and lower sides of the inner layer board needs to be monitored in the production process, so as to ensure the smooth proceeding of the subsequent processes and the quality of the PCB finished product. In the prior art, the principle of a vernier caliper is adopted when the interlayer alignment of an inner layer plate is tested, and the deviation degree is judged visually, for example, the deviation amount with the precision within the range of 5 μm can only be estimated by applying the principle of a testing method disclosed in a method for detecting the deviation degree of a drilling hole in a PCB (printed Circuit Board) in Chinese patent document CN 201510250510.9. The slice measurement based on the vernier caliper principle cannot accurately measure the interlayer offset data of the inner-layer plate, and the grinding and slicing of the thin plate are inaccurate; the principle of the vernier caliper is applied to a film exposure machine, and the precision cannot be guaranteed because the film exposure machine needs to be processed by multiple devices; and different testers carry out the test, can lead to the error too big because of different testers' operation difference.
Disclosure of Invention
The invention provides a simple and easy interlayer alignment measuring method which can accurately acquire offset data and has high measuring precision, aiming at the problems that the existing interlayer alignment measuring method of an inner layer plate has poor measuring precision, cannot acquire accurate measuring data, is complicated in measuring method and the like.
In order to achieve the purpose, the invention adopts the following technical scheme.
A method for testing interlayer alignment of a PCB inner layer board comprises the following steps:
s1, correspondingly transferring the patterns on the top film and the bottom film to the top layer and the bottom layer of the inner layer plate respectively through exposure and development, wherein the patterns at least comprise test PAD patterns which are respectively arranged at one of four corners of the top film and the bottom film; coordinates of test PAD pattern on top film as top design coordinates (X)A，YA) The coordinates of the test PAD pattern on the base film are the base design coordinates (X)B，YB)；
S2, etching and film stripping treatment are carried out according to the patterns of the top layer and the bottom layer of the inner layer plate, and an inner layer circuit and a test PAD corresponding to the test PAD pattern are formed on the top layer and the bottom layer of the inner layer plate;
S3, measuring the coordinates of the test PAD by a Pluritec target drilling machine, wherein the coordinates of the test PAD on the top layer of the inner layer plate are the measured coordinates (X) of the top layera，Ya) The coordinate of the test PAD on the bottom layer of the inner layer board is the measured coordinate (X) of the bottom layerb，Yb)；
S4, calculating deviation value delta X of the top layer design coordinate and the bottom layer design coordinate in the X direction respectivelysAnd deviation value DeltaY in Y directions，ΔXs＝XA-XB，ΔYs＝YA-YB；
respectively calculating the deviation value delta X of the top layer measured coordinate and the bottom layer measured coordinate in the X directiontAnd deviation value DeltaY in Y directiont，ΔXt＝Xa-Xb，ΔYt＝Ya-Yb；
S5, wherein the interlayer alignment degree of the inner layer plate in the X direction is delta Xt-ΔXs(ii) a The interlayer alignment degree of the inner layer plate in the Y direction is delta Yt-ΔYs。
Preferably, in step S1, a test PAD pattern is designed at each of four corners of the top film and the bottom film.
Preferably, the test PAD graph is circular, and the diameter is more than or equal to 0.5 mm.
Preferably, on the same corner of the inner layer plate, the projection of the test PAD of the top layer and the test PAD of the bottom layer in the direction vertical to the plate surface is more than or equal to 3 mm.
Compared with the prior art, the invention has the beneficial effects that:
The invention sets a pair of non-coincident test PAD patterns at the same angle of the top layer and the bottom layer of the inner layer plate, and calculates the design deviation values of the pair of test PAD patterns in the X direction and the Y direction; forming a test PAD corresponding to the pair of test PAD patterns on the bottom layer and the top layer of the inner layer plate after etching; calculating actual measurement deviation values of the test PAD in the X direction and the Y direction, and comparing the actual measurement deviation values with design deviation values in the X direction and the Y direction respectively to accurately calculate the deviation between the circuits of the top layer and the bottom layer of the inner layer plate; meanwhile, the method does not relate to subjective judgment of testers, so that errors caused by the subjective judgment of the testers can be avoided, and the test result has good repeatability and is more objective and reliable.
Detailed Description
in order to more fully understand the technical contents of the present invention, the technical solutions of the present invention will be further described and illustrated with reference to the following specific embodiments.
Examples
The embodiment provides a method for testing interlayer alignment of a PCB inner layer board, which comprises the following steps:
(1) correspondingly transferring the patterns on the top film and the bottom film to the top layer and the bottom layer of the inner layer plate respectively through exposure and development, wherein the patterns comprise test PAD patterns which are arranged at four corners of the top film and the bottom film respectively, and the diameter of each test PAD pattern is 1 mm; the coordinates of the test PAD pattern (center point, the same applies hereinafter) on the top film are top design coordinates (XA, YA), and the coordinates of the test PAD pattern on the bottom film are bottom design coordinates (X)B，YB). For example:
The test PAD patterns are arranged at the lower left corners of the top layer film and the bottom layer film, the corresponding design coordinates of the top layer are (40, 30), and the corresponding design coordinates of the bottom layer are (35, 25); deviation DeltaX between the top design coordinates (40, 30) and the bottom design coordinates (35, 25) in the X directions5, the deviation DeltaY between the top design coordinates (40, 30) and the bottom design coordinates (35, 25) in the Y directionsIs 5.
(2) And etching and film removing treatment are carried out according to the patterns of the top layer and the bottom layer of the inner layer plate, and an inner layer circuit and a test PAD corresponding to the test PAD pattern are formed on the top layer and the bottom layer of the inner layer plate.
(3) Measuring the coordinate of the test PAD by a Pluritec target drilling machine, wherein the coordinate of the test PAD on the top layer of the inner layer plate is the measured coordinate (X) of the top layera，Ya) The coordinate of the test PAD on the bottom layer of the inner layer board is the measured coordinate (X) of the bottom layerb，Yb). For example:
Measuring a pair of test PADs corresponding to the top layer design coordinates (40, 30) and the bottom layer design coordinates (35, 25) by using a Pluritec drilling and targeting machine, wherein the corresponding top layer actual measurement coordinates are (38, 28), the corresponding bottom layer actual measurement coordinates are (33, 23), and the deviation value delta X of the top layer actual measurement coordinates (38, 28) and the bottom layer actual measurement coordinates (33, 23) in the X directiont5, the measured coordinates (38, 28) of the top layer and the measured coordinates (33, 23) of the bottom layer are deviated from each other by an amount DeltaY in the Y directiontIs 5.
(4) The interlayer alignment degree of the inner layer plate in the X direction is delta Xt-ΔXs(ii) a The interlayer alignment degree of the inner layer plate in the Y direction is delta Yt-ΔYs. For example, in the interlayer alignment of the inner layer board exemplified above, the interlayer alignment in the X direction is 0, that is, the interlayer deviation (layer deviation amount) in the X direction is 0; the interlayer alignment in the Y direction is 0, that is, the interlayer offset (layer offset) in the Y direction is 0.
And calculating four groups of interlayer deviations in X and Y directions according to the test PAD patterns arranged at the four corners and the test PAD, and taking a group of values with the maximum interlayer deviation value as the interlayer alignment degree of the inner plate.
The following description is that patterns on films are transferred to the inner plate by exposure equipment of different brands, the specification of each inner plate and the design of a PAD pattern tested on the inner plate are the same, the interlayer alignment of the inner plate is tested according to the method of the embodiment, and the test results are shown in the following table.
The technical contents of the present invention are further illustrated by the examples, so as to facilitate the understanding of the reader, but the embodiments of the present invention are not limited thereto, and any technical extension or re-creation based on the present invention is protected by the present invention.

Claims (4)

1. A method for testing interlayer alignment of a PCB inner layer board is characterized by comprising the following steps:
s1, respectively aligning the patterns on the top film and the bottom film by exposure and developmentThe pattern is transferred to the top layer and the bottom layer of the inner layer plate, and the pattern at least comprises a test PAD pattern which is respectively arranged at one of four corners of a top layer film and a bottom layer film; coordinates of test PAD pattern on top film as top design coordinates (X)A，YA) The coordinates of the test PAD pattern on the base film are the base design coordinates (X)B，YB)；
S2, etching and film stripping treatment are carried out according to the patterns of the top layer and the bottom layer of the inner layer plate, and an inner layer circuit and a test PAD corresponding to the test PAD pattern are formed on the top layer and the bottom layer of the inner layer plate;
s3, measuring the coordinates of the test PAD by a Pluritec target drilling machine, wherein the coordinates of the test PAD on the top layer of the inner layer plate are the measured coordinates (X) of the top layera，Ya) The coordinate of the test PAD on the bottom layer of the inner layer board is the measured coordinate (X) of the bottom layerb，Yb)；
S4, calculating deviation value DeltaX of the top layer design coordinate and the bottom layer design coordinate in the X direction respectivelysAnd deviation value DeltaY in Y directions，△Xs＝XA-XB，△Ys＝YA-YB；
Respectively calculating the deviation value delta X of the top layer measured coordinate and the bottom layer measured coordinate in the X directiontAnd deviation value DeltaY in Y directiont，ΔXt＝Xa-Xb，ΔYt＝Ya-Yb；
S5, wherein the interlayer alignment degree of the inner layer plate in the X direction is delta Xt-ΔXs(ii) a The interlayer alignment degree of the inner layer plate in the Y direction is delta Yt-ΔYs。
2. The method for testing interlayer alignment of inner layer board of PCB of claim 1, wherein in step S1, each of four corners of said top film and said bottom film is designed with a test PAD pattern.
3. The method for testing interlayer alignment of inner layer board of PCB of claim 2, wherein said test PAD pattern is circular with a diameter greater than or equal to 0.5 mm.
4. The method for testing the interlayer alignment of the inner layer board of the PCB as claimed in claim 3, wherein the distance between the test PAD on the top layer and the test PAD on the bottom layer projected in the direction perpendicular to the board surface at the same corner of the inner layer board is greater than or equal to 3 mm.
CN201910777207.2A 2019-08-20 2019-08-20 Method for testing interlayer alignment degree of PCB inner-layer plate Pending CN110572960A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113408238A (en) * 2021-05-25 2021-09-17 奥士康科技股份有限公司 Method for determining optimal alignment value of anti-welding 8-point CCD

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08307065A (en) * 1995-04-28 1996-11-22 Elna Co Ltd Multilayer printed wiring board and inspection method for the board
CN106061139A (en) * 2016-06-17 2016-10-26 奥士康精密电路（惠州）有限公司 Layer-to-layer registration control method for inner layers of HDI (High Density Interconnector) board
CN107666768A (en) * 2017-09-29 2018-02-06 奥士康科技股份有限公司 Aligning degree monitoring method between PCB layer
CN108684145A (en) * 2018-05-07 2018-10-19 潘玥铭 A method of improving PCB Aligning degrees
CN108925066A (en) * 2018-08-28 2018-11-30 深圳市景旺电子股份有限公司 A kind of multi-layer board interlayer bias detecting method and detection system

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08307065A (en) * 1995-04-28 1996-11-22 Elna Co Ltd Multilayer printed wiring board and inspection method for the board
CN106061139A (en) * 2016-06-17 2016-10-26 奥士康精密电路（惠州）有限公司 Layer-to-layer registration control method for inner layers of HDI (High Density Interconnector) board
CN107666768A (en) * 2017-09-29 2018-02-06 奥士康科技股份有限公司 Aligning degree monitoring method between PCB layer
CN108684145A (en) * 2018-05-07 2018-10-19 潘玥铭 A method of improving PCB Aligning degrees
CN108925066A (en) * 2018-08-28 2018-11-30 深圳市景旺电子股份有限公司 A kind of multi-layer board interlayer bias detecting method and detection system

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113408238A (en) * 2021-05-25 2021-09-17 奥士康科技股份有限公司 Method for determining optimal alignment value of anti-welding 8-point CCD

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Application publication date: 20191213