CN110572025A - multi-path adjustable power supply - Google Patents

multi-path adjustable power supply Download PDF

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Publication number
CN110572025A
CN110572025A CN201910808568.9A CN201910808568A CN110572025A CN 110572025 A CN110572025 A CN 110572025A CN 201910808568 A CN201910808568 A CN 201910808568A CN 110572025 A CN110572025 A CN 110572025A
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China
Prior art keywords
capacitor
power supply
circuit
voltage
electrically connected
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CN201910808568.9A
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Chinese (zh)
Inventor
蒋迪
李潇雨
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University of Electronic Science and Technology of China
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University of Electronic Science and Technology of China
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Priority to CN201910808568.9A priority Critical patent/CN110572025A/en
Publication of CN110572025A publication Critical patent/CN110572025A/en
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/0003—Details of control, feedback or regulation circuits
    • H02M1/0012—Control circuits using digital or numerical techniques
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/0083—Converters characterised by their input or output configuration
    • H02M1/009—Converters characterised by their input or output configuration having two or more independently controlled outputs

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

the invention discloses a multi-path adjustable power supply, which is characterized in that a power supply circuit is used for reducing the voltage of 30V of input voltage to 5V and converting the 5V voltage into 1.2V voltage used by an internal logic circuit and a PLL digital circuit, 2.5V voltage used by a PLL analog circuit and 3.3V voltage used by each circuit; the clock circuit is used for providing an accurate clock source for the FPGA chip; the interface circuit is used for programming the content of the FPGA chip and configuring digital control quantity; the configuration circuit is used for converting the digital control quantity of the FPGA chip into analog voltage for output; the key circuit is used for scanning the analog voltage to obtain the currently pressed key value, then assigning values to the DAC register variable in the configuration circuit of each path, and outputting the required voltage value. The multi-path program-controlled adjustable voltage feed to the antenna array can be realized, the problem of overlarge volume of a feed system is effectively solved, and the practicability of the antenna array is improved.

Description

Multi-path adjustable power supply
Technical Field
The invention relates to the technical field of antennas, in particular to a multi-path adjustable power supply.
Background
With the development of modern electronic information technology, the requirements for antenna characteristics such as beam adjustability, miniaturization, high performance, etc. are increasing, wherein the beam adjustability of the antenna is particularly emphasized. The phased array antenna is a common scheme for realizing a scanning antenna, and phase compensation is realized by changing characteristic parameters of an array element such as length, a rotation angle, corresponding parameters of tunable materials and the like, so that the direction of a main beam of the antenna is changed, and a beam scanning function is further realized. However, the traditional mechanical phased array antenna with heavier mass, complex beam adjustment mode and long response time delay is more and more difficult to meet the requirements of the modern electronic information technology on low time delay and high precision of a communication system, so that the related research of the electrically-controlled phased array antenna is deepened day by day. The electrically tunable phased array antenna has the characteristics of convenient and fast beam adjustment, program control and relatively low mass size, and is the advantage selection for realizing the antenna beam adjustment. One of the key points for realizing the electrically-tunable phased array is the independent tunable feed to each array element of the phased array antenna. The increase of the number of the antenna elements can correspondingly improve the gain of the electric control scanning antenna, but the following problems are that the complexity of a feed system is obviously improved, and the volume of the feed system is also obviously increased, which affects the practical value of the antenna array.
Disclosure of Invention
aiming at the defects in the prior art, the invention aims to provide a multi-path adjustable power supply which can realize multi-path program-controlled adjustable voltage feed to an antenna array, effectively solve the problem of overlarge volume of a feed system and improve the practicability of the antenna array.
in order to achieve the purpose, the invention adopts a multi-path adjustable power supply which comprises an FPGA chip, a power supply circuit, a clock circuit, an interface circuit, a configuration circuit and a key circuit,
The power supply circuit, the clock circuit, the interface circuit, the configuration circuit and the key circuit are all electrically connected with the FPGA chip;
The FPGA chip is used for providing 1.2V voltage for the internal logic circuit and the PLL digital circuit, providing 2.5V voltage for the PLL analog circuit and providing 1.2V, 1.5V, 1.8V, 2.5V, 3.0V or 3.3V voltage for each circuit by IO voltage;
The power supply circuit is used for reducing the input voltage of 30V to 5V and converting the 5V voltage into a 1.2V voltage for the internal logic circuit and the PLL digital circuit, a 2.5V voltage for the PLL analog circuit and a 3.3V voltage for each circuit;
The clock circuit is used for providing an accurate clock source for the FPGA chip;
the interface circuit is used for programming and configuring the content of the FPGA chip and configuring digital control quantity;
The configuration circuit is used for converting the digital control quantity of the FPGA chip into analog voltage for output;
The key circuit is used for scanning the analog voltage to obtain the currently pressed key value, then assigning values to the DAC register variable in the configuration circuit of each path, and outputting the required voltage value.
Wherein the power circuit comprises a voltage reduction unit, the voltage reduction unit comprises a 30V power supply end, a capacitor C7, a capacitor C8, a capacitor C9, a voltage reduction type management power chip, an inductor L1, a Schottky diode D1, a 5V power supply end and a capacitor C, one end of the capacitor C7, one end of the capacitor C8 and one end of the capacitor C9 are electrically connected with the 30V power input end and the VIN terminal of the buck management power chip respectively, the other ends of the capacitor C7, the capacitor C8 and the capacitor C9 are grounded, one end of the inductor L1 is electrically connected to the OUT terminal of the buck management power chip and one end of the schottky diode D1, the other end of the inductor L1 is electrically connected with the FB end of the buck management power supply chip, the 5V power supply end and one end of the capacitor C, the other end of the capacitor C, the GND end of the buck management power supply chip and the other end of the Schottky diode D1 are all grounded.
the power circuit further comprises a first conversion unit, the first conversion unit comprises a voltage stabilizing chip, a capacitor C11, a 3.3V power supply end, a capacitor C10, a capacitor C12, a resistor R1 and a light emitting diode D2, a VIN end of the voltage stabilizing chip and one end of the capacitor C11 are both electrically connected with the 5V power supply end, a Vo end of the voltage stabilizing chip is electrically connected with the 3.3V power supply end, the 3.3V power supply end is respectively electrically connected with one end of the capacitor C10, the capacitor C12 and one end of the resistor R1, the other end of the resistor R1 is electrically connected with a positive end of the light emitting diode D2, and the negative end of the light emitting diode D2, a GND end of the voltage stabilizing chip, the capacitor C10, the capacitor C11 and the other end of the capacitor C12 are all grounded.
the power circuit further comprises a second conversion unit, the second conversion unit comprises a capacitor C5, a 2.5V power supply end, a capacitor C4 and a capacitor C6, one end of the capacitor C5 and a VIN end of the voltage stabilizing chip are electrically connected with the 5V power supply end, a Vo end of the voltage stabilizing chip is electrically connected with one end of the capacitor C4 and one end of the 2.5V power supply end, the other end of the 2.5V power supply end is electrically connected with one end of the capacitor C6, and the other ends of the capacitor C6, the capacitor C4, the capacitor C5 and the GND end of the voltage stabilizing chip are all grounded.
The power circuit further comprises a third conversion unit, the third conversion unit comprises a capacitor C14, a capacitor C13, a 1.2V power supply end and a capacitor C15, one end of the capacitor C14 and the VIN end of the voltage stabilizing chip are both electrically connected with the 5V power supply end, the Vo end of the voltage stabilizing chip is electrically connected with one end of the capacitor C13 and the 1.2V power supply end, the other end of the 1.2V power supply end is electrically connected with one end of the capacitor C15, and the capacitor C15, the capacitor C13, the other end of the capacitor 14 and the GND end of the voltage stabilizing chip are all grounded.
The clock circuit comprises a capacitor C3 and an active crystal oscillator clock, one end of the capacitor C3 is respectively connected with the 3.3V power supply end and the FPGA chip electrically, the other end of the capacitor C3 is grounded, the CLK end of the FPGA chip is electrically connected with the VCC end of the active crystal oscillator clock, and the GND end of the active crystal oscillator clock is grounded.
The interface circuit comprises a JTAG interface, the JTAG interface comprises a HEADER pin bank, a resistor R2, a resistor R3 and a resistor R4, a pin 1 of the HEADER pin bank is electrically connected with a TCK end of the FPGA chip and one end of the resistor R4 respectively, the other end of the resistor R4 is grounded, a pin 5 of the HEADER pin bank is electrically connected with a TMS end of the FPGA chip and a resistor R3 respectively, a pin 5 of the HEADER pin bank is electrically connected with a TMS end of the FPGA chip and one end of a resistor R3 respectively, a pin 9 of the HEADER pin bank is electrically connected with a TDI end of the FPGA chip and one end of the resistor R4 respectively, the resistor R4, the other end of the resistor R3 and a pin 4 of the HEADER pin bank are electrically connected with the 2.5V power supply terminal respectively, and a pin 2 and a pin 10 of the HEADER pin are grounded.
The interface circuit further comprises a FLASH memory and a resistor R5, wherein the NCS end of the FLASH memory is electrically connected with the NCSO end of the FPGA chip, the DATA end of the FLASH memory is electrically connected with the DATA end of the FPGA chip through the resistor R5, the VCC end of the FLASH memory is electrically connected with the VCC end of the FPGA chip, the GND end of the FLASH memory is electrically connected with the GND end of the FPGA chip, the DCLK end of the FLASH memory is electrically connected with the DCLK end of the FPGA chip, and the ASDI end of the FLASH memory is electrically connected with the ASDO end of the FPGA chip.
The configuration circuit comprises a high-voltage DAC, a capacitor C42, a capacitor C43, a capacitor C44, a capacitor C45, a light-emitting diode D3 and a resistor R9, wherein a VDD end of the high-voltage DAC is electrically connected with one ends of the 30V power supply end, the capacitor C42 and the capacitor C43, the other ends of the capacitor C42 and the capacitor C43 are grounded, VLOGIC and R _ SEL ends of the high-voltage DAC are electrically connected with one ends of the 3.3V power supply end, the capacitor C44 and the capacitor C45, the other ends of the capacitor C44 and the capacitor C45 are grounded, and an ALARM end of the high-voltage DAC is electrically connected with the light-emitting diode D3, the resistor R9 and the 3.3V power supply end in sequence.
The key circuit adopts a matrix keyboard and is used for firstly scanning rows and then scanning columns to obtain currently pressed key values, assigning values to DAC register variables in each path of configuration circuit and outputting required voltage values.
the invention has the beneficial effects that: through the combined action of the FPGA chip, the power circuit, the clock circuit, the interface circuit, the configuration circuit and the key circuit, the voltage of 0-30V can be adjusted in a stepping mode, and the voltage is independent and program-controlled. Compared with the traditional feed system, the volume of the power supply is obviously reduced, the gain, the scanning precision and the working frequency of the electric control scanning antenna array are improved, and the practicability of the antenna is obviously improved.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
fig. 1 is a schematic diagram of the multiple adjustable power supply of the present invention.
fig. 2 is a schematic diagram of the voltage-reducing unit of the power supply circuit of the present invention.
fig. 3 is a schematic diagram of a first conversion unit of the power supply circuit of the present invention.
Fig. 4 is a schematic diagram of a second conversion unit of the power supply circuit of the present invention.
Fig. 5 is a schematic diagram of a third conversion unit of the power supply circuit of the present invention.
Fig. 6 is a schematic diagram of the clock circuit of the present invention.
FIG. 7 is a schematic diagram of the JTAG interface of the present invention.
Fig. 8 is a schematic diagram of a FLASH memory of the present invention.
Fig. 9 is a functional block diagram of a high voltage DAC of the present invention.
Fig. 10 is a pin configuration of the high voltage DAC of the present invention.
Fig. 11 is a schematic diagram of a high voltage DAC of the present invention.
fig. 12 is a schematic diagram of the key circuit of the present invention.
100-multi-path adjustable power supply, 10-FPGA chip, 20-power circuit, 21-voltage reduction unit, 22-first conversion unit, 23-second conversion unit, 24-third conversion unit, 30-clock circuit, 40-interface circuit, 41-JTAG interface, 42-FLASH memory, 50-configuration circuit and 60-key circuit.
Detailed Description
Reference will now be made in detail to embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to the same or similar elements or elements having the same or similar function throughout. The embodiments described below with reference to the drawings are illustrative and intended to be illustrative of the invention and are not to be construed as limiting the invention.
In the description of the present invention, it is to be understood that the terms "length", "width", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like, indicate orientations or positional relationships based on the orientations or positional relationships illustrated in the drawings, and are used merely for convenience in describing the present invention and for simplicity in description, and do not indicate or imply that the devices or elements referred to must have a particular orientation, be constructed in a particular orientation, and be operated, and thus, are not to be construed as limiting the present invention. Further, in the description of the present invention, "a plurality" means two or more unless specifically defined otherwise.
Referring to fig. 1 to 12, the present invention provides a multi-channel adjustable power supply 100, which includes an FPGA chip 10, a power circuit 20, a clock circuit 30, an interface circuit 40, a configuration circuit 50, and a key circuit 60, wherein the power circuit 20, the clock circuit 30, the interface circuit 40, the configuration circuit 50, and the key circuit 60 are all electrically connected to the FPGA chip 10;
the FPGA chip 10 is configured to provide a voltage of 1.2V to the internal logic circuit and the PLL digital circuit, provide a voltage of 2.5V to the PLL analog circuit, and provide a voltage of 1.2V, 1.5V, 1.8V, 2.5V, 3.0V, or 3.3V to each circuit through the IO voltage;
the power supply circuit 20 is used for reducing the input voltage of 30V to 5V and converting the 5V voltage into a 1.2V voltage for the internal logic circuit and the PLL digital circuit, a 2.5V voltage for the PLL analog circuit and a 3.3V voltage for each circuit;
The clock circuit 30 is configured to provide a precise clock source to the FPGA chip 10;
The interface circuit 40 is used for programming the content of the FPGA chip 10 and configuring digital control quantity;
the configuration circuit 50 is configured to convert the digital control quantity of the FPGA chip 10 into an analog voltage for output;
The key circuit 60 is configured to scan the analog voltage to obtain a currently pressed key value, assign values to DAC register variables in the configuration circuit 50 of each channel, and output a required voltage value.
In the present embodiment, the FPGA chip 10 employs intel EP4CE10F17C8 as a control core. The working voltage of the FPGA chip is 1.15V-3.465V, the BGA256 is adopted for packaging, 164I/O ports are included, the logic resource is 10320, the configuration circuits 50 can convert digital control quantity of the FPGA chip 10 into analog voltage for output, one configuration circuit 50 has 4 voltage outputs, 25 configuration circuits 50 are needed, and 100 circuits of the electric control scanning antenna can be adjusted in power supply, the power supply circuit 20 is the most basic circuit capable of normally working of an EP4CE10F17C8 chip of Intel, the EP4CE10F17C8 needs 1.0V/1.2V voltage to supply an internal logic circuit (VCCINT) and a PLL digital circuit (VCCD _ PLL), 2.5V is needed to supply the PLL analog circuit (VCCA), and IO Voltage (VCCIO) can be accessed to different voltages such as 1.2V, 1.5V, 1.8V, 2.5V, 3.0V and 3.3V to supply different voltages to each chip area. Therefore, in design, the input 30V voltage is first reduced to 5V, and the 5V voltage is converted to 3.3V, 2.5V, and 1.2V to maintain the normal operation of the board, where 3.3V is used to supply the clock circuit 30, the configuration circuit 50, etc. voltage and the special function pin high level, 2.5V is used to supply VCCA voltage, and 1.2V is used to supply VCCINT and VCC _ PLL.
then, the clock circuit 30 controls each time sequence device in the design through a single master clock driven by a dedicated global clock input pin according to the fact that the FPGA chip 10 has the dedicated global clock pin, so as to provide a precise clock source for the FPGA chip 10;
The interface circuit 40 is a process for programming the FPGA contents. The requirement for configuration after each power-up is based on one feature of the SRAM process FPGA. Inside the FPGA, a plurality of programmable multiplexers, logics, interconnection line nodes, RAM initialization content and the like are arranged, and digital data are needed to be configured for control. The configuration RAM in the FPGA serves as a means for storing the configuration data.
The configuration circuit 50 converts the digital control quantity of the FPGA chip 10 into an analog voltage for output, and the output voltage range is programmably controlled through a range selection pin (RSEL). If the RSEL keeps high level, the output range of the DAC register is 0V to 30V, if the RSEL keeps low level, the output range of the DAC register is 0V to 60V, the output swing AGND within the allowable range of the on-chip output amplifier is +0.5V to-0.5V of VDD, then the key circuit 60 is utilized to scan the output analog voltage to obtain the currently pressed key value, then the variable of the DAC register in the configuration circuit 50 of each path is assigned, and the required voltage value is output.
In summary, the following steps: aiming at the requirements of large-scale antenna array feed system on overlarge volume and multi-path adjustable power supply, the voltage of 0-30V can be adjusted in a stepping mode and controlled independently and in a program mode by using 100 paths of power supplies. Compared with the traditional feed system, the volume of the power supply is obviously reduced, the gain, the scanning precision and the working frequency of the electric control scanning antenna array are improved, and the practicability of the antenna is obviously improved.
Further, the power circuit 20 includes a voltage-reducing unit 21, the voltage-reducing unit 21 includes a 30V power supply terminal, a capacitor C7, a capacitor C8, a capacitor C9, a voltage-reducing type management power chip, an inductor L1, a Schottky diode D1, a 5V power supply terminal, and a capacitor C, one end of the capacitor C7, one end of the capacitor C8 and one end of the capacitor C9 are electrically connected with the 30V power input end and the VIN terminal of the buck management power chip respectively, the other ends of the capacitor C7, the capacitor C8 and the capacitor C9 are grounded, one end of the inductor L1 is electrically connected to the OUT terminal of the buck management power chip and one end of the schottky diode D1, the other end of the inductor L1 is electrically connected with the FB end of the buck management power supply chip, the 5V power supply end and one end of the capacitor C, the other end of the capacitor C, the GND end of the buck management power supply chip and the other end of the Schottky diode D1 are all grounded.
In this embodiment, the unit values of the capacitor C7, the capacitor C8 and the capacitor C9 are all 1 μ F, the unit values of the capacitor C are 4.7 μ F and are all decoupling capacitors, the model of the buck management power supply chip is LM2596, the model of the inductor L1 is MSS1210-683MEB, the unit value is 68 μ H, the model of the schottky diode D1 is B560C-13-F, the unit value is 700mv, after the current of the 30V power supply end enters the buck unit 21, the current of the 30V power supply end passes through the capacitor C7, the capacitor C8 and the capacitor C9, the current of the circuit can be subjected to the functions of filtering OUT ripples and decoupling in the current, so as to provide a stable power supply for the power supply circuit 20, then the power supply enters the VIN terminal of the buck management power supply chip, then the power supply is output from the OUT terminal of the buck management power supply chip and respectively flows through the schottky diode D1, The inductor L1 and the capacitor C are grounded, and the power supply drops to the 5V power supply terminal after flowing through the inductor L1,
And then the 5V power supply end is grounded in parallel through a capacitor C1 and a capacitor C2, and the 5V voltage in the 5V power supply end is filtered again to ensure the stability of the circuit power supply.
Further, the power circuit 20 further includes a first converting unit 22, the first converting unit 22 includes a voltage stabilizing chip, a capacitor C11, a 3.3V power end, a capacitor C10, a capacitor C12, a resistor R1, and a light emitting diode D2, a VIN end of the voltage stabilizing chip and one end of the capacitor C11 are both electrically connected to the 5V power end, a Vo end of the voltage stabilizing chip is electrically connected to the 3.3V power end, the 3.3V power end is respectively electrically connected to the capacitor C10, the capacitor C12, and one end of the resistor R1, the other end of the resistor R1 is electrically connected to a positive end of the light emitting diode D2, and the negative end of the light emitting diode D2, the negative end of the voltage stabilizing chip, the capacitor C10, the capacitor C11, and the other end of the capacitor C12 are all grounded.
In this embodiment, the capacitor C11 is 0.1 μ F, the capacitor C10 is 10 μ F, the capacitor C12 is 0.1 μ F, the model of the voltage stabilization chip is AMS117, the voltage is reduced from 30V to 5V by the buck management power supply chip, the voltage of 5V enters the VIN end of the voltage stabilization chip, and after the conversion processing by the voltage stabilization chip, the voltage is output from the Vo end of the voltage stabilization chip and is converted into the power supply end of 3.3V, which is used for supplying the high level of the voltage and the special function pin of the clock circuit 30, the configuration circuit 50, and the like. The capacitor C10, the capacitor C11 and the capacitor C12 play a role of filtering, and the working state of the power supply can be conveniently checked through the on or off of the light-emitting diode D2.
further, the power circuit 20 further includes a second converting unit 23, the second converting unit 23 includes a capacitor C5, a 2.5V power end, a capacitor C4, and a capacitor C6, one end of the capacitor C5 and a VIN end of the voltage stabilizing chip are both electrically connected to the 5V power end, a Vo end of the voltage stabilizing chip is electrically connected to one end of the capacitor C4 and the 2.5V power end, the other end of the 2.5V power end is electrically connected to one end of the capacitor C6, and the capacitor C6, the capacitor C4, the other end of the capacitor C5, and a GND end of the voltage stabilizing chip are all grounded.
The capacitor C5 is 0.1 μ F, the capacitor C4 is 10 μ F, the capacitor C6 is 0.1 μ F, the model of the voltage stabilization chip is AMS117, the voltage is reduced from 30V to 5V by the buck management power supply chip, the 5V voltage enters the VIN end of the voltage stabilization chip, the voltage is output from the Vo end of the voltage stabilization chip after the conversion processing of the voltage stabilization chip, the voltage is converted into the 2.5V power supply end with the voltage of 2.5V, and the VCCA voltage is supplied, wherein the capacitor C5, the capacitor C4 and the capacitor C6 play a role in filtering.
Further, the power circuit 20 further includes a third converting unit 24, the third converting unit 24 includes a capacitor C14, a capacitor C13, a 1.2V power end and a capacitor C15, one end of the capacitor C14 and a VIN end of the voltage stabilizing chip are both electrically connected to the 5V power end, a Vo end of the voltage stabilizing chip is electrically connected to one end of the capacitor C13 and the 1.2V power end, the other end of the 1.2V power end is electrically connected to one end of the capacitor C15, and the capacitor C15, the capacitor C13, the other end of the capacitor 14 and the GND end of the voltage stabilizing chip are all grounded.
In this embodiment, the capacitor C14 is 0.1 μ F, the capacitor C13 is 10 μ F, the capacitor C15 is 0.1 μ F, the voltage regulator chip is model AMS117, the voltage is reduced from 30V to 5V by the buck management power supply chip, a voltage of 5V enters the VIN terminal of the voltage regulator chip, the voltage is converted by the voltage regulator chip, the voltage is output from the Vo terminal of the voltage regulator chip and converted into the 1.2V power supply terminal with a voltage of 1.2V, and thereby the VCCINT and the VCC _ PLL voltage are supplied, wherein the capacitor C13, the capacitor C14 and the capacitor C15 perform a filtering function.
Further, the clock circuit 30 includes a capacitor C3 and an active crystal oscillator clock, one end of the capacitor C3 is electrically connected to the 3.3V power supply terminal and the FPGA chip 10, the other end of the capacitor C3 is grounded, the CLK terminal of the FPGA chip 10 is electrically connected to the VCC terminal of the active crystal oscillator clock, and the GND terminal of the active crystal oscillator clock is grounded.
In this embodiment, the best solution for the clock in the FPGA design is: a single master clock driven by a dedicated global clock input pin controls each sequential device in the design, should try to use the global clock in the design project whenever possible, the FPGA has a dedicated global clock pin that is directly connected to each register in the device. In the device, the global clock can provide the shortest delay and the highest precision. In the design, a global clock port CLK is used, and the active crystal clock is used as an external clock source because the global clock port CLK is a single clock port. The active crystal oscillator clock adopts a crystal oscillator 5070 chip and can generate a crystal oscillator of 50MHz, 3.3V voltage generated by the 3.3V power supply end passes through the FPGA chip 10, a VCC end of the active crystal oscillator clock enters to supply power to the active crystal oscillator clock, and then a 50MHz clock signal is output from an OUT end, so that an accurate clock source is provided for a system, wherein the capacitor C3 is 0.1 muF and can play a role in filtering a circuit,
Further, the interface circuit 40 includes a JTAG interface 41, the JTAG interface 41 includes a HEADER pin, a resistor R2, a resistor R3, and a resistor R4, the pin 1 of the HEADER pin is electrically connected to the TCK terminal of the FPGA chip 10 and one end of the resistor R4, the other end of the resistor R4 is grounded, the pin 5 of the HEADER pin is electrically connected to the TMS terminal of the FPGA chip 10 and the resistor R3, the pin 5 of the HEADER pin is electrically connected to the TMS terminal of the FPGA chip 10 and one end of the resistor R3, the pin 9 of the HEADER pin is electrically connected to the TDI terminal of the FPGA chip 10 and one end of the resistor R4, the resistor R4, the other end of the resistor R3, and the pin 4 of the HEADER pin are electrically connected to the 2.5V power supply terminal, and the pin 2 and the pin 10 of the HEADER pin are grounded. The interface circuit 40 further includes a FLASH memory 42 and a resistor R5, the NCS end of the FLASH memory 42 is electrically connected to the NCSO end of the FPGA chip 10, the DATA end of the FLASH memory 42 is electrically connected to the DATA end of the FPGA chip 10 through the resistor R5, the VCC end of the FLASH memory 42 is electrically connected to the VCC end of the FPGA chip 10, the GND end of the FLASH memory 42 is electrically connected to the GND end of the FPGA chip 10, the DCLK end of the FLASH memory 42 is electrically connected to the DCLK end of the FPGA chip 10, and the ASDI end of the FLASH memory 42 is electrically connected to the ASDO end of the FPGA chip 10.
In this embodiment, the interface circuit 40 is a process for programming the FPGA content. The requirement for configuration after each power-up is based on one feature of the SRAM process FPGA. Within the FPGA there are many programmable multiplexers, logic, interconnect nodes and RAM initialization content, all of which require configuration data to control. The configuration RAM in the FPGA serves as a means for storing the configuration data. Depending on the role of the FPAG in the configuration circuit 50, its configuration data can be loaded (downloaded) to the target device using 3 ways, three of which are: an FPGA Active (Active) mode, an FPGA Passive (Passive) method and a JTAG mode. The JTAG interface 41 is an industry standard interface, the Altera FPGA can basically support JTAG commands to configure the FPGA, and the JTAG configuration mode has higher priority than any other configuration mode, so the board provides the JTAG configuration mode, and in addition, in order to enable the FPGA to still maintain program data after power down, the FPGA needs to be externally connected with a configuration chip, here, the model of the FLASH memory 42 of the Altera company is selected as EPCS16, and the FLASH memory 42 belongs to an enhanced configuration device, the capacity is up to 16Mbit, and supports monolithic configuration of the large-capacity FPGA, which can be programmed in the system by the JTAG interface 41.
further, the configuration circuit 50 includes a high voltage DAC, a capacitor C42, a capacitor C43, a capacitor C44, a capacitor C45, a light emitting diode D3 and a resistor R9, a VDD terminal of the high voltage DAC is electrically connected to one of the 30V power supply terminal, the capacitor C42 and the capacitor C43, the other ends of the capacitor C42 and the capacitor C43 are grounded, a VLOGIC terminal of the high voltage DAC is electrically connected to one of the 3.3V power supply terminal, the capacitor C44 and the capacitor C45, the other ends of the capacitor C44 and the capacitor C45 are grounded, and an ALARM terminal of the high voltage DAC is electrically connected to the light emitting diode D3, the resistor R9 and the 3.3V power supply terminal in sequence.
in this embodiment, the high voltage DAC is model AD5504, and the high voltage DAC is a product of tuning signals available for antennas and filters, manufactured by ADI, adeno semiconductor company. The AD5504 is a four channel, 12 bit, serial input, digital-to-analog converter with on-chip high voltage output amplifier and an integrated precision reference. The DAC output voltage range is programmably controlled through a range select pin (R _ SEL). If R _ SEL keeps high level, DAC output range is 0V to 30V, if R _ SEL keeps low level, DAC output range is 0V to 60V, and AD5504 of +0.5V to VDD-0.5V of output swing AGND in the on-chip output amplifier allowable range has a high-speed serial interface, COM compatible SPI, QSPI, MICROWIRE and DSP interface standard of the interface can process clock speed up to 16.667 MHz. The capacitor C42 is 10 muF, the capacitor C43 is 0.1 muF, the capacitor C44 is 10 muF, the capacitor C45 is 0.1 muF, all of which are decoupling capacitors, a 30V power supply and a 3.3V power supply are filtered through the capacitor C42, the capacitor C43, the capacitor C44 and the capacitor C45, then the AD5504 works normally, and a 0 ohm magnetic bead is adopted to isolate a digital ground from an analog ground, so that the crosstalk between the digital ground and the analog ground is prevented from influencing the accuracy of output. The LED D3 is used as a temperature alarm indicator light, when the temperature of a chip exceeds 110 ℃, an effective level (low level) is output, the LED D3 is conducted to emit light to send an indication signal, the RSEL is connected to a logic high level (3.3V), the output voltage range is set between 0V and 30V, the LODAC is connected to the ground to enable the loading DAC to be effective all the time, and a zero clearing pin CLR is connected to the high level to enable zero clearing to be disabled. And reading and writing the register of the AD5504 through the FPGA chip 10, and controlling the output voltage of the DAC, wherein the register is 16 bits, and the upper three bits are address bits.
further, the key circuit 60 adopts a matrix keyboard, and is configured to perform row scanning first and then column scanning to obtain a currently pressed key value, assign values to DAC register variables in the configuration circuit 50 of each channel, and output a required voltage value.
In this embodiment, the key circuit 60 uses a matrix keyboard, and first performs row scanning and then column scanning to obtain a currently pressed key value, and then controls corresponding operations to assign values to the DAC register variables of each path, and then outputs the values, so that each path can output a required voltage value.
In summary, the following steps: the invention realizes a 100-channel adjustable power supply module applied to an electric control scanning antenna, which is realized by combining the FPGA chip 10 with the high-voltage DAC, and can realize the stepping adjustment of the voltage of 0-30V and the independent program control. The design can realize high-precision voltage regulation and control while ensuring 100 independent programmable feeds. Compared with the traditional feed system, the volume of the power supply is obviously reduced, the miniaturization and the light weight of the electric control scanning antenna can be supported, the gain, the scanning precision and the working frequency of the electric control scanning antenna can be improved, the application range of the electric control scanning antenna is enlarged, the practicability of the electric control scanning antenna is improved, and the development trend of power supply design is met.
While the invention has been described with reference to a preferred embodiment, it will be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.

Claims (10)

1. A multi-path adjustable power supply is characterized in that,
the FPGA chip comprises an FPGA chip, a power circuit, a clock circuit, an interface circuit, a configuration circuit and a key circuit, wherein the power circuit, the clock circuit, the interface circuit, the configuration circuit and the key circuit are all electrically connected with the FPGA chip;
the FPGA chip is used for providing 1.2V voltage for the internal logic circuit and the PLL digital circuit, providing 2.5V voltage for the PLL analog circuit and providing 1.2V, 1.5V, 1.8V, 2.5V, 3.0V or 3.3V voltage for each circuit by IO voltage;
The power supply circuit is used for reducing the input voltage of 30V to 5V and converting the 5V voltage into a 1.2V voltage for the internal logic circuit and the PLL digital circuit, a 2.5V voltage for the PLL analog circuit and a 3.3V voltage for each circuit;
the clock circuit is used for providing an accurate clock source for the FPGA chip;
The interface circuit is used for programming and configuring the content of the FPGA chip and configuring digital control quantity;
The configuration circuit is used for converting the digital control quantity of the FPGA chip into analog voltage for output;
The key circuit is used for scanning the analog voltage to obtain the currently pressed key value, then assigning values to the DAC register variable in the configuration circuit of each path, and outputting the required voltage value.
2. the multiple adjustable power supply of claim 1,
the power supply circuit comprises a voltage reduction unit, wherein the voltage reduction unit comprises a 30V power supply end, a capacitor C7, a capacitor C8, a capacitor C9, a voltage reduction type management power supply chip, an inductor L1, a Schottky diode D1, a 5V power supply end and a capacitor C, one end of the capacitor C7, one end of the capacitor C8 and one end of the capacitor C9 are electrically connected with the 30V power input end and the VIN terminal of the buck management power chip respectively, the other ends of the capacitor C7, the capacitor C8 and the capacitor C9 are grounded, one end of the inductor L1 is electrically connected to the OUT terminal of the buck management power chip and one end of the schottky diode D1, the other end of the inductor L1 is electrically connected with the FB end of the buck management power supply chip, the 5V power supply end and one end of the capacitor C, the other end of the capacitor C, the GND end of the buck management power supply chip and the other end of the Schottky diode D1 are all grounded.
3. The multiple adjustable power supply of claim 2,
the power circuit further comprises a first conversion unit, the first conversion unit comprises a voltage stabilizing chip, a capacitor C11, a 3.3V power supply end, a capacitor C10, a capacitor C12, a resistor R1 and a light emitting diode D2, a VIN end of the voltage stabilizing chip and one end of the capacitor C11 are electrically connected with the 5V power supply end, a Vo end of the voltage stabilizing chip is electrically connected with the 3.3V power supply end, the 3.3V power supply end is electrically connected with one end of the capacitor C10, the capacitor C12 and one end of the resistor R1 respectively, the other end of the resistor R1 is electrically connected with a positive electrode end of the light emitting diode D2, and the negative electrode end of the light emitting diode D2, the GND end of the voltage stabilizing chip, the capacitor C10, the capacitor C11 and the other end of the capacitor C12 are all grounded.
4. The multiple adjustable power supply of claim 3,
The power circuit further comprises a second conversion unit, wherein the second conversion unit comprises a capacitor C5, a 2.5V power supply end, a capacitor C4 and a capacitor C6, one end of the capacitor C5 and a VIN end of the voltage stabilizing chip are both electrically connected with the 5V power supply end, a Vo end of the voltage stabilizing chip is electrically connected with one ends of the capacitor C4 and the 2.5V power supply end, the other end of the 2.5V power supply end is electrically connected with one end of the capacitor C6, and the capacitor C6, the capacitor C4, the other end of the capacitor C5 and the GND end of the voltage stabilizing chip are all grounded.
5. The multiple adjustable power supply of claim 4,
the power circuit further comprises a third conversion unit, wherein the third conversion unit comprises a capacitor C14, a capacitor C13, a 1.2V power supply end and a capacitor C15, one end of the capacitor C14 and the VIN end of the voltage stabilizing chip are both electrically connected with the 5V power supply end, the Vo end of the voltage stabilizing chip is electrically connected with one ends of the capacitor C13 and the 1.2V power supply end, the other end of the 1.2V power supply end is electrically connected with one end of the capacitor C15, and the capacitor C15, the capacitor C13, the other end of the capacitor 14 and the GND end of the voltage stabilizing chip are all grounded.
6. the multiple adjustable power supply of claim 2,
The clock circuit comprises a capacitor C3 and an active crystal oscillator clock, one end of the capacitor C3 is respectively electrically connected with the 3.3V power supply end and the FPGA chip, the other end of the capacitor C3 is grounded, the CLK end of the FPGA chip is electrically connected with the OUT end of the active crystal oscillator clock, and the GND end of the active crystal oscillator clock is grounded.
7. The multiple adjustable power supply of claim 4,
the interface circuit comprises a JTAG interface, the JTAG interface comprises a HEADER pin, a resistor R2, a resistor R3 and a resistor R4, a pin 1 of the HEADER pin is electrically connected with a TCK end of the FPGA chip and one end of the resistor R4 respectively, the other end of the resistor R4 is grounded, a pin 5 of the HEADER pin is electrically connected with a TMS end of the FPGA chip and a resistor R3 respectively, a pin 5 of the HEADER pin is electrically connected with a TMS end of the FPGA chip and one end of a resistor R3 respectively, a pin 9 of the HEADER pin is electrically connected with a TDI end of the FPGA chip and one end of the resistor R4 respectively, the other end of the resistor R4, the other end of the resistor R3 and a pin 4 of the HEADER pin are electrically connected with the 2.5V power supply terminal respectively, and a pin 2 and a pin 10 of the HEADER pin are grounded.
8. The multiple adjustable power supply of claim 7,
The interface circuit further comprises a FLASH memory and a resistor R5, wherein the NCS end of the FLASH memory is electrically connected with the NCSO end of the FPGA chip, the DATA end of the FLASH memory is electrically connected with the DATA end of the FPGA chip through the resistor R5, the VCC end of the FLASH memory is electrically connected with the VCC _ +3.3V end of the FPGA chip, the GND end of the FLASH memory is electrically connected with the GND end of the FPGA chip, the DCLK end of the FLASH memory is electrically connected with the DCLK end of the FPGA chip, and the ASDI end of the FLASH memory is electrically connected with the ASDO end of the FPGA chip.
9. The multiple adjustable power supply of claim 1,
the configuration circuit comprises a high-voltage DAC, a capacitor C42, a capacitor C43, a capacitor C44, a capacitor C45, a light-emitting diode D3 and a resistor R9, wherein a VDD end of the high-voltage DAC is electrically connected with one ends of the 30V power supply end, the capacitor C42 and the capacitor C43, the other ends of the capacitor C42 and the capacitor C43 are grounded, VLOGIC and R _ SEL ends of the high-voltage DAC are electrically connected with one ends of the 3.3V power supply end, the capacitor C44 and the capacitor C45, the other ends of the capacitor C44 and the capacitor C45 are grounded, and an ALARM end of the high-voltage DAC is electrically connected with the light-emitting diode D3, the resistor R9 and the 3.3V power supply end in sequence.
10. The multiple adjustable power supply of claim 1,
The key circuit adopts a matrix keyboard and is used for firstly carrying out row scanning and then carrying out column scanning to obtain the currently pressed key value, assigning values to DAC register variables in the configuration circuit of each path and outputting a required voltage value.
CN201910808568.9A 2019-08-29 2019-08-29 multi-path adjustable power supply Pending CN110572025A (en)

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CN111769538A (en) * 2020-07-15 2020-10-13 北京无线电测量研究所 Phased array antenna subarray power supply circuit and electric appliance with same
CN117477954A (en) * 2023-12-27 2024-01-30 吉林省龙电电气有限公司 Power module with adjustable multipath output voltage

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CN103631176A (en) * 2013-08-30 2014-03-12 天津大学 FPGA-based ultrahigh-speed industrial controller
CN104237674A (en) * 2014-08-18 2014-12-24 安徽罗伯特科技股份有限公司 Portable arc light protecting calibration device
CN204517654U (en) * 2015-02-28 2015-07-29 合肥国轩高科动力能源股份公司 A kind of DC-DC reduction voltage circuit
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Application publication date: 20191213