CN110571260A - Volume-conducting power semiconductor component with homogenization structure and method for operating the same - Google Patents

Volume-conducting power semiconductor component with homogenization structure and method for operating the same Download PDF

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Publication number
CN110571260A
CN110571260A CN201910482503.XA CN201910482503A CN110571260A CN 110571260 A CN110571260 A CN 110571260A CN 201910482503 A CN201910482503 A CN 201910482503A CN 110571260 A CN110571260 A CN 110571260A
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power semiconductor
semiconductor component
main side
component according
central region
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B·罗森斯塔夫
W-M·舒尔茨
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Semiconductor Electronics Co Ltd
Semikron Elektronik GmbH and Co KG
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Semiconductor Electronics Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/74—Thyristor-type devices, e.g. having four-zone regenerative action
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H01L29/8611—Planar PN junction diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H01L29/8613—Mesa PN junction diodes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/14—Modifications for compensating variations of physical values, e.g. of temperature
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H01L2224/401—Disposition
    • H01L2224/40151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/40221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/40225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H01L29/0692—Surface layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region

Abstract

The invention provides a power semiconductor component and a method for operating a circuit arrangement with a power semiconductor component, wherein the power semiconductor component has a first main side and a second main side and a semiconductor body, which has a first semiconductor body main side, wherein the first main side has a first metallization layer and the second main side has a second metallization layer, wherein the first main side has a central region (100) extending radially outward from a center thereof, wherein the semiconductor body (2) or the first metallization layer (40) or even both are implemented in such a way, such that during operation the surface temperature of the central region (100) has at least three local maxima (110) and at least two local minima (120) from the centre, or in such a way that the surface temperature of the central zone (100) is uniform during operation.

Description

Volume-conducting power semiconductor component with homogenization structure and method for operating the same
Technical Field
The invention describes a volume-conducting power semiconductor component having a first and a second main side and having a semiconductor body, and a method for operating a circuit arrangement having such a semiconductor component.
Background
A semiconductor diode is known from the prior art, which is disclosed in an exemplary manner in DE 102017103111 a1, which has no prior publication date with respect to this document, which semiconductor diode is formed with a semiconductor body, with a first main side, which is formed by an inner region on which a first contact layer is arranged and by an edge region, and with a current path from the first contact layer to a second contact layer arranged on a second main region opposite the first main region, wherein the semiconductor diode is formed by means of the configuration of the first contact layer or the first semiconductor body in such a way that: when a current flows through the current path, a local current path is formed, which is the current path with the greatest heating per unit volume and which starts from a further local region of the inner region, which is arranged outside the boundary of the inner local region in the inner region to an outer local region adjoining the inner local region and forming part thereof, the inner local region preferably being a central local region, i.e. a local region arranged around the central axis.
disclosure of Invention
On the basis of the background described above, it is an object of the present invention to provide a volumetrically conducting power semiconductor component in which the current distribution during operation has a uniform form in a large central area. Another object of the invention is to propose a method for operating a circuit arrangement with power semiconductor components.
According to the invention, this object is achieved by a power semiconductor component having the following features:
The volume-conducting power semiconductor component according to the invention has a first main side and a second main side and a semiconductor body with a first semiconductor body main side, wherein the first main side has a first metallization layer and the second main side has a second metallization layer, wherein the first main side has a central region 100 extending radially outward from its center, wherein the semiconductor body 2 or the first metallization layer 40 or even both are implemented in such a way that during operation the surface temperature of the central region 100 has at least three local maxima 110 and at least two local minima 120 from the center, or in such a way that during operation the surface temperature of the central region 100 is uniform.
Here, the term "central region" describes a region of the power semiconductor component which extends radially outward from the center, while this does not already define the geometry or design of the edge region. In principle, the configuration of the geometry of this central region on the basis of the shape of the power semiconductor component itself is advantageous, i.e. a circular or approximately circular central region in the case of a circular power semiconductor component or a substantially rectangular central region in the case of a rectangular power semiconductor component, and the corners of this central region are additionally rounded in an advantageous manner.
Preferably, the central region has an area of at least 25%, preferably at least 30%, and particularly preferably at least 40% of the area of the first main side.
In particular, it is advantageous if, during operation, the surface temperature of the central region has at least three local maxima and at least two local minima from the center, and the first temperature difference of the surface temperature of the central region between a local maximum and an adjacent local minimum has a value of at most 2K, in particular at most 1K.
As an alternative thereto, it is advantageous if the surface temperature of the central region is homogeneous during operation and the second temperature difference of the surface temperature of the central region between the absolute maximum and the absolute minimum 120 has a value of less than 2K, in particular a value of less than 1K.
In the case of a current flow from the first metallization layer to the second metallization layer, the semiconductor body in the central region may also preferably have a modulation, preferably a periodic modulation, of the resistance R adjacent to the first semiconductor body main side. The modulation can be formed here by a concentric arrangement of insulating large-area, in particular fresnel-type volume regions on the main side of the first semiconductor body, the area volume regions being in particular embodied as a semiconductor oxide.
Here, the term "large area" is understood to mean an area on the order of one percent or more of the area of the first main side. In contrast, the term "small area" below is understood to mean an area of the first main side of the order of one thousandth or less. The term "fresnel-type" is understood to resemble a fresnel lens, in particular a binary fresnel lens, which is also referred to as a binary fresnel zone plate.
Alternatively or alternatively, in addition to the above-described configuration, it may be preferred for the modulation to be formed by a density variation of the small-area elements 58 on the main side of the first semiconductor body, wherein the small-area elements are embodied in particular as a semiconductor oxide.
Likewise, alternatively or additionally thereto, it may be preferred for the modulation to be formed by a variation of a first doping concentration of the semiconductor body or by a variation of a second doping concentration of the semiconductor body.
In addition, it may in principle be advantageous if the first metallization layer has a periodic modulation, in particular a fresnel-type modulation, in the central region.
The power semiconductor component is preferably embodied as a power semiconductor resistor, as a power semiconductor diode, as a power semiconductor thyristor or as a power semiconductor transistor.
Furthermore, according to the invention, the above object is achieved by a method for operating a circuit arrangement with the above-described power semiconductor component.
The method according to the invention for operating a component circuit arrangement, wherein the circuit arrangement has a power semiconductor component, a first electrical connector having a first metallization layer, a second electrical connector having a second metallization layer, and wherein a first electrical current flows from the first metallization layer to the second metallization layer, is characterized in that the surface temperature of the central region has at least three local maxima and at least two local minima from the center, or the surface temperature of the central region is a uniform component.
The first current may be a constant current having a current intensity of 80% of the nominal current of the semiconductor component. Preferably, the constant current is a current in a conducting direction of the power semiconductor component.
Of course, features or groups of features which are respectively specified in the singular may be present multiple times in a power semiconductor component according to the invention if this is not explicitly excluded or excluded per se or if this does not contradict the inventive concept.
It should be understood that the various configurations of the present invention, whether they are specified with power semiconductor components or with methods for operating circuit arrangements having such power semiconductor components, may be implemented individually or in any combination to achieve improvements. In particular, the features specified and explained both above and below can be used not only in the specified combinations but also in other combinations or alone without departing from the scope of the invention.
Drawings
Further explanations, advantageous details and features of the invention result from the following description of exemplary embodiments of the invention, which are schematically illustrated in fig. 1 to 9 or the following description of corresponding parts thereof.
Fig. 1 and 2 show a cross-sectional view and a plan view of a first configuration of a power semiconductor component according to the invention.
Fig. 3 to 6 show diagrams of the electrical resistances adjacent to the first semiconductor body main side of various configurations of the power semiconductor component according to the invention.
Fig. 7 shows a circuit arrangement with a power semiconductor component according to the invention.
Fig. 8 and 9 show diagrams of the surface temperature of a power semiconductor component according to the invention, and in fig. 8 a diagram of the surface temperature of a power semiconductor component according to the prior art is additionally shown.
Detailed Description
Fig. 1 and 2 show a first configuration of a power semiconductor component 1 according to the invention, wherein fig. 1 is shown in a sectional view and fig. 2 is shown in a plan view. 3 the 3 cross 3- 3 sectional 3 view 3 is 3 based 3 on 3 a 3 cross 3- 3 section 3 along 3 line 3 a 3- 3 a 3. 3 A power semiconductor component 1 is shown, in this case a power diode with a semiconductor body 2, the semiconductor body 2 having a first doping, in this case an n-type doping. A well 3 with a second doping, in this case a p-type doping, is formed in the semiconductor body 2 symmetrically about its center, more precisely about its central axis. Thus, a pn junction is formed between the first doping and the second doping. Furthermore, the semiconductor body 2 has a first semiconductor body main side 20 and a second semiconductor body main side 21 arranged opposite the first semiconductor body main side 20. A first metallization layer 40 is arranged on a portion of the first semiconductor body main side 20 in the region of the well 3. A second metallization layer 30 is arranged on a portion of the second semiconductor body main side 22. Fig. 2 shows a plan view of the first semiconductor body main side 20 without the first metallization layer.
The respective first main side 10 and second main side 12 of the power diode 1 are defined with undulating accessible surfaces, i.e. with respective metallization layers 40, 30 on the associated semiconductor body main side 20, 22.
The semiconductor diode 1, in this case a silicon semiconductor diode, is developed according to the invention by a large-area electrically insulating volume region 5 arranged in the region of the well 3. These volume regions are formed by means of the surface regions of the first semiconductor body main side 20, 22 which are exposed to the oxidizing atmosphere and, as a result, the p-doped silicon is converted from these surface regions into silicon oxide which extends from the semiconductor body main side 20 into the semiconductor body 2, more precisely into the well 3, and forms the volume region 5 there. However, the volume region 5 made of silicon oxide does not extend as far as or even beyond the pn-junction.
In plan view, the power diode 1 is shown with a square base. The electrically insulating silicon oxide volume regions 50,52,54,56 have a structure adapted thereto, which structure has a fresnel-type embodiment in plan view. In this case, the structure has a central first silicon oxide volume region 50 with a square radial extent and a rounded corner region. In the radial direction, the first silicon oxide volume regions are adjoined by a first "square" ring with rounded corners that does not have silicon oxide volume regions.
The first square ring with rounded corners and no silicon oxide volume area is bordered in the radial direction by the first square ring with silicon oxide volume area 52.
Next, it continues in an alternating manner through the second quad ring without a silicon oxide volume region, the second quad ring with a silicon oxide volume region 54, the third quad ring without a silicon oxide volume region, and the third quad ring with a silicon oxide volume region 56.
Due to the structure, what happens when a current is applied in the conducting direction of the pn junction (the current is naturally applied through the first metallization layer 40 and the second metallization layer 30) is that the surface temperature of the central region 100 adjoining the third ring with the silicon volume region 56 at a small radial distance has four local maxima 110 and four local minima 120 from the center, see also fig. 8. Thus, the central region 100 extends slightly beyond the aforementioned structure.
Fig. 3 to 6 show diagrams of the periodic modulation of the resistance R adjacent to the first semiconductor body main side 20 in various configurations of the power semiconductor component according to the invention. The adjacent region can be located in particular in the pn junction region of the power diode, as is shown in principle in fig. 1, or it can be located between the silicon oxide volume region and the pn junction.
Fig. 3 shows on the left side the value of the resistance R in the silicon volume region actually at the end of the penetration depth of the latter and on the right side the associated structure of the silicon oxide volume region in plan view, in each case of the power diodes according to fig. 1 and 2.
The schematic curve of the resistance R is only approximately shown and ultimately corresponds to the structure of the silicon oxide volume regions 50,52,54, 56. The resistance R of a square power semiconductor component is plotted starting from the center and reaching the edge R of the power semiconductor component0 3 again 3 similar 3 to 3 the 3 direction 3 a 3- 3 a 3 according 3 to 3 fig. 32 3. 3 This curve of the resistance R is achieved by the structure of the silicon oxide volume regions 50,52,54,56, as in both fig. 1 and fig. 2And on the right side of figure 3. The illustration shows only a part of the large-area fresnel-type structure on the right, likewise starting from the center and reaching up to the edge r of the power semiconductor component0。
Fig. 4 shows on the left the value of the resistance R in the above-mentioned region near the pn junction at a small distance from the end of the penetration depth of the small-area silicon oxide volume element, and on the right and in plan view the associated structure of such a small-area silicon oxide volume element 58, which is correspondingly a power diode, in a manner similar to fig. 3, only a part of the surface on the right.
In this case, the roughness structure of those areas that produce the effect according to the invention follows a fresnel-type configuration; in this case, however, each "ring" does not have any large silicon oxide volume area, but rather the single ring is formed from a small area silicon oxide volume element 58. These small-area silicon oxide volume elements 58 have different dimensions in terms of surface extent and, without loss of generality, in this case have a circular embodiment. In principle, this involves a density variation of these small-area silicon oxide volume elements 58, which small-area silicon oxide volume elements 58 obtain a large-area effect by their interaction. Preferably, all of the small area silicon oxide volume elements 58 have the same penetration depth and interact to form a curve of resistance R as shown on the left side.
Fig. 5 shows the value of the resistance R in the above-mentioned region, in fact at the end of the penetration depth of the large-area silicon volume region, substantially in a manner similar to fig. 3. However, the fresnel-type structure starts with a central region where no silicon volume regions are arranged; instead, the first silicon volume region is arranged as a ring around the central region. In particular, for power thyristors with a central gate, such a structure is advantageous without loss of generality.
Fig. 6 shows the value of the resistance R in the above-mentioned region in the vicinity of the pn junction at a small distance from the end of the penetration depth of the small-area silicon oxide volume element, in principle in a manner similar to that of the power thyristor according to fig. 4. Here, the central region of the gate of the power thyristor is likewise free of silicon oxide volume elements.
Fig. 7 shows a circuit arrangement with a power semiconductor component according to the invention, in this case a semiconductor diode 1, which has a substrate 6 and a connection device 7. The substrate 6 has an insulating layer 60 or alternatively a body of insulating material, on which conductor tracks 62 are arranged in each case. Here, this is a substrate conventional in the art, by way of example a so-called Direct Copper Bonding (DCB) substrate, as is conventional for power semiconductor modules which, for example, also have a metal layer 64 on the second side of the insulating layer. In a manner conventional in the art, the second contact layer 30 of the semiconductor diode 1 is electrically conductively connected to the conductor track 62 in a force-fitting or material-bonding manner, for example by soldering. The first contact layer 40 of the semiconductor diode 1 is electrically conductively connected to the circuit arrangement, to be precise to the further conductor track 62 of the substrate 60, by means of the connecting device 7. The connecting means 7 also has an embodiment conventional in the art, in this case a metal clip; however, it may also be implemented as a conductive film or a wire bond connection.
Fig. 8 and 9 show graphs of the surface temperature of a power semiconductor component according to the invention, and in addition a graph of the surface temperature of a power semiconductor component according to the prior art is shown in fig. 8.
Fig. 8 shows the temperature profile of various power semiconductor diodes during their application, from the respective center to the edge of the respective semiconductor diode during the application of the power semiconductor diode in the circuit arrangement, and in the case of a constant current in the conducting direction with a current intensity of 80% of the nominal current. Curve a is the temperature profile of the semiconductor diode according to the accepted prior art. Such power semiconductor diodes heat most strongly in their center because heat dissipation from this area to the substrate or heat sink is least efficient. In this case, a maximum temperature of more than 173 ℃ is generated in the center of the power semiconductor diode and thus a maximum heating area per unit volume is generated. Temperature is monotonous in the radial directionReduced to the edge r0。
In one configuration according to curve B of a power semiconductor diode according to the prior art described in DE 102017103111 a1, the region with the highest temperature during operation is displaced in the direction of the edge of the semiconductor diode.
Curve C shows the temperature profiles of the power semiconductor diodes according to fig. 1 to 3. Starting from the center, the temperature profile has four local maxima 110 and four local minima 120, wherein a first temperature difference 130 of the surface temperature of the central region 100 between a local maximum 110 and an adjacent local minimum 120 has a value of at most 2K, in particular a value of at most 1K. Starting from a power semiconductor diode having a square shape, the central region constitutes approximately 30% of the area of the main side of the first semiconductor body.
Fig. 9 shows a temperature profile from the center to the edge for the power semiconductor diode according to fig. 4, the current intensity of which is 80% of the nominal current when the power semiconductor diode is applied in the circuit arrangement and has a constant current in the conduction direction. The temperature profile of the surface temperature of the central region 100 is homogeneous and therefore has a second temperature difference 132 of the surface temperature of the central region 100 between the absolute maximum 112 and the absolute minimum 122, which is less than 2K, in particular less than 1K. The central region again constitutes approximately 30% of the area of the main side of the first semiconductor body, starting from the power semiconductor diode having a square shape.

Claims (22)

1. A volume-conducting power semiconductor component (1) having a first main side (10), a second main side (12) and a semiconductor body (2), the semiconductor body (2) having a first semiconductor body main side (20), wherein the first main side (10) has a first metallization layer (40), the second main side (12) has a second metallization layer (30), wherein the first main side (10) has a central region (100) extending radially outward from its center, wherein the semiconductor body (2) or the first metallization layer (40) is embodied such that the surface temperature of the central region (100) has at least three local maxima (110) and at least two local minima (120) from the center during operation or is embodied such that the surface temperature of the central region (100) is uniform during operation.
2. Power semiconductor component according to claim 1, characterized in that the central region (100) has an area of at least 25% of the area of the first main side.
3. Power semiconductor component according to claim 1, characterized in that the central region (100) has an area of at least 30% of the area of the first main side.
4. Power semiconductor component according to claim 1, characterized in that the central region (100) has an area of at least 40% of the area of the first main side.
5. Power semiconductor component according to any one of claims 1-4, characterized in that the surface temperature of the central region (100) during operation has at least three local maxima (110) and at least two local minima (120) from the center, and that the first temperature difference (130) of the surface temperature of the central region (100) between a local maximum (110) and an adjacent local minimum (120) has a value of at most 2K.
6. The power semiconductor component according to claim 5, characterized in that the first temperature difference (130) has a value of at most 1K.
7. Power semiconductor component according to any of claims 1-4, characterized in that the surface temperature of the central area (100) is uniform during operation and that the second temperature difference (132) between the absolute maximum (112) and the absolute minimum (122) of the surface temperature of the central area (100) has a value of less than 2K.
8. The power semiconductor component according to claim 7, characterized in that the second temperature difference (132) has a value smaller than 1K.
9. Power semiconductor component according to any one of claims 1 to 4, characterized in that the semiconductor body in the central region (100) has a modulation of the resistance (R) adjacent to the first semiconductor body main side (20) in the case of a current flow from the first metallization layer (40) to the second metallization layer (30).
10. Power semiconductor component according to claim 9, characterized in that the semiconductor body in the central region (100) has a periodic modulation of the resistance (R) adjacent to the first semiconductor body main side (20) in the case of a current flow from the first metallization layer (40) to the second metallization layer (30).
11. Power semiconductor component according to claim 9, characterized in that the modulation is formed by a concentric arrangement of insulating large area volume regions on the first semiconductor body main side (20).
12. Power semiconductor component according to claim 11, characterized in that the modulation is done by a concentric arrangement of fresnel-type volume regions (50, 52,54, 56) on the first semiconductor body main side (20).
13. Power semiconductor component according to claim 11, characterized in that the insulating large-area volume region is embodied as a semiconductor oxide.
14. Power semiconductor component according to claim 9, characterized in that the modulation is formed by a density variation of the small-area elements (58) on the first semiconductor body main side (20).
15. Power semiconductor component according to claim 14, characterized in that the small-area element (58) is embodied as a semiconductor oxide.
16. Power semiconductor component according to claim 9, characterized in that the modulation is formed by a variation of a first doping concentration of the semiconductor body (2) or by a variation of a second doping concentration of the portion (3) of the semiconductor body (2).
17. The power semiconductor component according to any one of claims 1 to 4, characterized in that the first metallization layer has a periodic modulation in the central region.
18. Power semiconductor component according to claim 17, characterized in that the first metallization layer has a fresnel type modulation in the central area.
19. Power semiconductor component according to one of claims 1 to 4, characterized in that the power semiconductor component is embodied as a power semiconductor resistor, a power semiconductor diode, a power semiconductor thyristor or a power semiconductor transistor.
20. Method for operating a circuit arrangement with a power semiconductor component according to any one of the preceding claims, a first electrical connector with a first metallization layer, a second electrical connector with a second metallization layer, and wherein a first current flows from the first metallization layer to the second metallization layer, wherein the surface temperature of the central region has at least three local maxima and at least two local minima from the center, or the surface temperature of the central region is uniform.
21. The method according to claim 20, characterized in that the first current is a constant current having a current intensity of 80% of the nominal current of the semiconductor component.
22. A method as claimed in claim 21, characterized in that the constant current is a current in the conducting direction of the power semiconductor component.
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