CN110571186A - Method for manufacturing metal nanowire, semiconductor device and method for manufacturing semiconductor device - Google Patents
Method for manufacturing metal nanowire, semiconductor device and method for manufacturing semiconductor device Download PDFInfo
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- CN110571186A CN110571186A CN201810570146.8A CN201810570146A CN110571186A CN 110571186 A CN110571186 A CN 110571186A CN 201810570146 A CN201810570146 A CN 201810570146A CN 110571186 A CN110571186 A CN 110571186A
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B82—NANOTECHNOLOGY
- B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- B82Y40/00—Manufacture or treatment of nanostructures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5386—Geometry or layout of the interconnection structure
Abstract
The invention provides a manufacturing method of a metal nanowire, a semiconductor device and a manufacturing method thereof.
Description
Technical Field
the present invention relates to the field of integrated circuit manufacturing technologies, and in particular, to a method for manufacturing a metal nanowire, a semiconductor device, and a method for manufacturing the semiconductor device.
Background
With the rapid development of nanotechnology and the increasing demand for miniaturization of device size and function integration, it is a future development trend to fabricate nano devices with more complex structures and smaller components. The interconnection technology of the nanometer materials is a bridge from the nanometer materials to the nanometer devices, and is one of the necessary bases for promoting the large-scale application of the nanometer materials. A nanostructure is a structure with at least one dimension (1D) on the nanometer scale (1 to 100 nm). Among the 1D nanostructures, metal nanowires are attracting more and more attention and can be used as interconnection structures in electronic, optical and nano-sensing devices, but the manufacturing method of metal nanowires used as interconnection structures also has the defects of poor nanowire morphology, uneven thickness and the like, which seriously affects the electrical performance and yield of finally formed semiconductor devices.
Disclosure of Invention
The invention aims to provide a manufacturing method of a metal nanowire, a semiconductor device and a manufacturing method thereof, which can form the metal nanowire with better side wall appearance and higher thickness uniformity, thereby improving the performance of the device and improving the yield of the product.
In order to achieve the above object, the present invention provides a method for manufacturing a metal nanowire, comprising the steps of:
Forming a patterned core layer on a semiconductor substrate;
Forming a metal layer covering the patterned core layer and the surface of the semiconductor substrate;
Forming a side wall on the side wall of the patterned core layer, wherein the side wall covers the metal layer on the side wall of the patterned core layer;
And removing the metal layer on the top surface of the patterned core layer and the surface of the semiconductor substrate outside the side wall to form the metal nanowire.
optionally, the material of the patterned core layer includes at least one of silicon oxide, silicon oxynitride, silicon nitride, and a low-K dielectric.
Optionally, the metal layer is made of at least one of ruthenium (Ru), molybdenum (Mo), tungsten (W), cobalt (Co), rhenium (Re), iron (Fe), osmium (Os), rhodium (Rh), iridium (Ir), nickel (Ni), palladium (Pd), platinum (Pt), titanium (Ti), zirconium (Zr), hafnium (Hf), vanadium (V), niobium (Nb), tantalum (Ta), chromium (Cr), and technetium (Tc).
Optionally, the step of forming a sidewall on the sidewall of the metal layer includes:
Depositing a side wall material layer on the surface of the metal layer;
and removing the side wall material layer above the top surface of the patterned core layer and part of the side wall material layer above the surface of the semiconductor substrate outside the patterned core layer to form a side wall covering the side wall of the metal layer.
optionally, the sidewall material layer above the top surface of the patterned core layer is removed by a chemical mechanical planarization process, and then a part of the sidewall material layer above the surface of the semiconductor substrate outside the patterned core layer is removed by a first wet etching process to form a sidewall covering the sidewall of the metal layer; or, the side wall material layer is etched to the surface of the metal layer through a first wet etching process, and then the top surface of the rest side wall material layer is flattened to the top surface of the patterned core layer through a chemical mechanical planarization process.
Optionally, the deposition thickness of the side wall material layer is 2nm to 20 nm.
Optionally, the step of removing the metal layer on the top surface of the patterned core layer and on the surface of the semiconductor substrate outside the sidewall to form the metal nanowire includes:
thinning the metal layer by adopting a dry etching process;
and removing the residual metal layer on the top surface of the patterned core layer and the surface of the semiconductor substrate outside the side wall by adopting a second wet etching process to form the metal nanowire.
Optionally, the dry etching process is an ion beam etching process.
Optionally, the metal layer is over-etched by the second wet etching process, so that the top surface of the formed metal nanowire is lower than the top surface of the core layer.
optionally, the etchant of the second wet etching process includes a sodium hypochlorite solution.
Optionally, after the metal nanowire is formed, the top surface of the sidewall is planarized to the top surface of the patterned core layer.
The invention also provides a manufacturing method of the semiconductor device, which comprises the following steps:
Providing a semiconductor substrate;
and forming the metal nanowire on the surface of the semiconductor substrate by adopting the manufacturing method of the metal nanowire.
Optionally, the method for manufacturing a semiconductor device further includes:
covering a passivation layer on the surface of the semiconductor substrate, wherein the passivation layer also covers the side wall, the patterned core layer and the top surface of the metal nanowire;
etching the passivation layer to form a groove exposing the side wall, the patterned core layer and the top surface of the metal nanowire in the passivation layer;
and removing the side wall, and forming a conducting layer in the groove, wherein the conducting layer covers the top surfaces of the metal nanowires and the patterned core layer.
Optionally, before etching the passivation layer, the passivation layer is further subjected to top surface planarization.
optionally, the material of the conductive layer includes at least one of titanium, tantalum, aluminum, copper, nickel, cobalt, and tungsten.
Optionally, a top surface of the conductive layer is lower than a top surface of the passivation layer, or the conductive layer at least fills the trench.
The present invention also provides a semiconductor device comprising:
a semiconductor substrate;
A patterned core layer on a portion of a surface of the semiconductor substrate;
The metal nanowire is positioned on the semiconductor substrate and attached to the side wall of the patterned core layer, and the outer side wall of the metal nanowire is L-shaped.
optionally, the top surface of the metal nanowire is lower than the top surface of the patterned core layer.
Optionally, the material of the patterned core layer includes at least one of silicon oxide, silicon oxynitride, silicon nitride, and a low-K dielectric.
Optionally, the material of the metal nanowire includes at least one of ruthenium, molybdenum, tungsten, cobalt, rhenium, iron, osmium, rhodium, iridium, nickel, palladium, platinum, titanium, zirconium, hafnium, vanadium, niobium, tantalum, chromium, and technetium.
optionally, the semiconductor device further includes a passivation layer on the surface of the semiconductor substrate outside the metal nanowire, and a top surface of the passivation layer is higher than a top surface of the patterned core layer, and a gap is formed between the passivation layer and the metal nanowire.
Optionally, the width of the gap from the passivation layer to the metal nanowire is 2nm to 20 nm.
optionally, the semiconductor device further includes a conductive layer covering the top surface of the core layer and the top surface of the metal nanowire, and filling the gap.
compared with the prior art, the technical scheme of the invention has the following beneficial effects:
1. According to the manufacturing method of the metal nanowire, after the patterned core layer and the semiconductor substrate surface are covered with the metal layer, the side wall is formed on the side wall of the metal layer, then under the protection of the side wall, the metal layer on the top surface of the patterned core layer and the semiconductor substrate surface outside the side wall is removed, the metal layer clamped between the patterned core layer and the side wall is not subjected to extra etching and is reserved, and the L-shaped metal nanowire is formed.
2. According to the manufacturing method of the semiconductor device, the metal nanowire is manufactured by adopting the manufacturing method of the metal nanowire, so that the metal nanowire with better side wall appearance and higher thickness uniformity can be obtained, the performance of the device is improved, and the yield of products is improved.
3. According to the semiconductor device, the metal nanowire covers the side wall of the patterned core layer, the metal nanowire is L-shaped, the side wall is good in appearance, and the thickness uniformity is high, so that the performance of the semiconductor device is guaranteed.
Drawings
fig. 1A to 1E are schematic cross-sectional views of a device structure in a method of manufacturing a semiconductor device having a metal nanowire;
FIG. 2A is a flow chart of a method of fabricating metal nanowires in accordance with an embodiment of the present invention;
FIG. 2B is a flow chart of a method of fabricating a semiconductor device in accordance with an embodiment of the present invention;
Fig. 3A to 3K are schematic cross-sectional views of device structures in a method of manufacturing a semiconductor device according to an embodiment of the present invention.
Detailed Description
referring to fig. 1A to 1E, a method for fabricating a semiconductor device having a metal nanowire includes the following steps:
First, referring to fig. 1A, a bottom anti-reflection layer (for example, SiCN)101 and a core layer are sequentially covered on a semiconductor substrate 100, and the core layer is patterned by processes of photoresist coating, exposure, development, and the like to form a patterned core layer 102;
Then, with continued reference to fig. 1A, a deposition process of Ru or other material is employed to cover the metal layer 103 on the surfaces of the patterned core layer 102 and the etch stop layer 101, and the deposition thickness of the metal layer 103 in each region is substantially the same;
Next, referring to fig. 1B, the metal layer is etched by using an anisotropic metal etching process until the top surface of the patterned core layer 102 and the top surface of the etching stop layer 101 are exposed, at this time, only the sidewall of the patterned core layer 102 is covered with the metal layer, and the remaining metal layer is the metal nanowire 103 a;
Then, referring to fig. 1C, a passivation layer 104 made of silicon nitride or the like is deposited on the surfaces of the etching stop layer 101, the patterned core layer 102 and the metal nanowire 103a, and a top surface of the passivation layer 104 is planarized, where the passivation layer 104 has a certain thickness on the top surface of the patterned core layer 102;
Next, referring to fig. 1D, the passivation layer 104 is etched to the surface of the etch stop layer 101 to form a trench 104a, where the trench 104a can expose the top surface of the patterned core layer 102, the top surface of the metal nanowire 103a, and the sidewall thereof away from the core layer 102;
Then, referring to fig. 1E, a conductive material such as Al is filled into the trench 104a by a process such as evaporation or sputtering to form a conductive contact pad 105, thereby completing the manufacture of the semiconductor device.
In the manufacturing method of the semiconductor device, the critical dimension of the metal nanowire mainly depends on the deposition thickness of materials such as Ru and the height of the patterned core layer 102, when the passivation layer 104 is etched to form the trench 104a, since the opening of the trench 104a is relatively large, in the process of etching the passivation layer 104 on the outer side of the metal nanowire 103a (i.e. the side of the metal nanowire 103a away from the core layer 102) to the surface of the etch stop layer 101, the exposed sidewall of the metal nanowire 103a is etched to a certain extent, so that the sidewall profile is damaged and uneven in thickness, which may cause some region of the metal nanowire 103a to disappear in severe cases, for example, the top surface of the metal nanowire 103a becomes short and is far lower than a required height, for example, when the sidewall of the core layer 102 is an inclined sidewall, the bottom of the metal nanowire 103a is etched to be away from the surface of the etch stop layer 101, the cross section of the metal nanowire 103 may be shortened from a linear shape covering the sidewall of the core layer 102 to an elliptical shape or even a point, which may cause poor contact between the metal nanowire 103a and the subsequently formed conductive contact pad 105, and thus may affect the performance and yield of the finally formed semiconductor device.
based on the method, the invention provides a manufacturing method of the metal nanowire, a semiconductor device and a manufacturing method of the semiconductor device
the present invention will be described in more detail with reference to the accompanying drawings, which are included to illustrate embodiments of the present invention.
Referring to fig. 2, the present invention provides a method for manufacturing a metal nanowire, comprising the following steps:
S1, forming a patterned core layer on a semiconductor substrate, wherein the core layer exposes a part of the surface of the semiconductor substrate;
s2, forming a metal layer, wherein the metal layer covers the core layer and the surface of the semiconductor substrate;
s3, forming a side wall on the side wall of the patterned core layer, wherein the side wall covers the metal layer on the side wall of the patterned core layer;
And S4, removing the metal layers on the top surface of the core layer and the surface of the semiconductor substrate outside the side wall to form the metal nanowire.
Referring to fig. 3A and 3B, in step S1, the semiconductor substrate used to provide a platform for subsequent processing may include any semiconductor material, including but not limited to: si, SiC, SiGe, SiGeC, Ge alloys, GeAs, InAs, InP, and other III-V or II-VI compound semiconductors. The semiconductor substrate may also comprise an organic semiconductor or a layered semiconductor such as Si/SiGe, silicon-on-insulator (SOI), or SiGe-on-insulator (sgoi). An isolation structure and a device structure (not labeled in the figure) can be further formed in the semiconductor substrate, the isolation structure can be a local isolation structure comprising a device isolation structure used for device isolation and a local area isolation structure used for local area isolation in the device, and the isolation structure can be a shallow trench isolation structure; the device structure can comprise active devices such as MOS transistors and the like or passive devices such as resistors, capacitors and the like. The semiconductor substrate in this embodiment includes a semiconductor base 300 and an etch stop layer 301. In step S1, first, an etching stop layer 301 and a core material layer 302a are sequentially covered on a semiconductor substrate 300, where the etching stop layer 301 may be formed of at least one of carbon-containing silicon nitride (SiCN, or NDC), silicon nitride, silicon oxynitride, silicon oxide, an Organic Dielectric (ODL) or spin-on-carbon (SOC), and may be formed by a thermal oxidation process, a thermal nitridation process, a Chemical Vapor Deposition (CVD) process, a coating process, or the like, the core material layer 302a is different from the etching stop layer 301, and the core material layer may be formed of at least one of silicon oxide, silicon oxynitride, silicon nitride, and a low-K dielectric (dielectric constant K is less than 4) and may be formed by a chemical vapor deposition, a physical vapor deposition, or a coating process; next, an anti-reflective layer (not shown, which may be a silicon-containing anti-reflective material Si-ARC) and a photoresist layer 303 may be sequentially formed on the surface of the core material layer 302a, and the photoresist layer 303 may be patterned by a photolithography process such as exposure and development; the anti-reflective layer and the core material layer 302a are then sequentially etched using the patterned photoresist layer 303 as a mask, the etching stopping on the surface of the etch stop layer 301 to transfer the pattern in the photoresist layer 303 into the core material layer 302a, thereby forming the patterned core layer 302, where the patterned core layer 302 exposes a portion of the surface of the etch stop layer 301. Thereafter, the patterned photoresist layer 303 may be removed through an ashing process, and the anti-reflection layer may be removed through an etching process or the like to expose the top surface of the patterned core layer 302.
Referring to fig. 3C, in step S2, a metal layer 304 may be deposited on the patterned core layer 302 and the surface of the etch stop layer 301 by a Physical Vapor Deposition (PVD), Chemical Vapor Deposition (CVD), or Atomic Layer Deposition (ALD), and the deposited metal layer 304 may cover the sidewalls and the top surface of the core layer 302 and the surface of the etch stop layer 301 outside the patterned core layer 302. The material of the metal layer 304 may be selected from a non-copper metal or alloy having a melting point greater than that of copper (e.g., greater than 1085 ℃). For example, in some embodiments, the metal layer 304 may include at least one of ruthenium (Ru), molybdenum (Mo), tungsten (W), cobalt (Co), rhenium (Re), iron (Fe), osmium (Os), rhodium (Rh), iridium (Ir), nickel (Ni), palladium (Pd), titanium (Ti), zirconium (Zr), hafnium (Hf), vanadium (V), niobium (Nb), tantalum (Ta), chromium (Cr), and technetium (Tc). The metal layer 304 may also include low atomic percent (e.g., typically less than about 5 atomic percent) non-metallic impurities, such as carbon (C), hydrogen (H), oxygen (O), or nitrogen (N).
Referring to fig. 3C and 3D, in step S3, a sidewall material layer 305 is first deposited on the surface of the metal layer 304 by using a Physical Vapor Deposition (PVD), a Chemical Vapor Deposition (CVD), or an Atomic Layer Deposition (ALD), and the like, wherein the material of the sidewall material layer is selected to have a higher etching selectivity with the etching stop layer 301, the metal layer 304, and the subsequently formed passivation layer (306 in fig. 3H) to facilitate subsequent removal, and the deposition thickness of the sidewall material layer 305 may be determined according to the size of the device to be manufactured, for example, 2nm to 20 nm; then, performing chemical mechanical planarization on the deposited sidewall material layer 305 until the top surface of the patterned core layer 302 is exposed; next, the spacer material layer 305 above the surface of the etch stop layer 301 outside the patterned core layer 302 is removed by etching through a first wet etching process to form a spacer 305a covering the sidewall of the metal layer 304. Or, after depositing the sidewall material layer 305 on the surface of the metal layer 304, etching the sidewall material layer 305 by a first wet etching process, stopping etching on the surface of the metal layer 304, and then planarizing the top surface of the remaining sidewall material layer to the top surface of the metal layer 303 above the patterned core layer 302 by a chemical mechanical planarization process to form a sidewall 305a covering the sidewall of the metal layer 304.
Referring to fig. 3E and 3F, in step S4, the metal layer 303 may be partially etched by a dry etching process such as an Ion Beam Etching (IBE) process, and the metal layer 303 with most of the thickness on the top surface (i.e., the top surface) of the patterned core layer 302 and on the surface of the etching stop layer 301 outside the sidewall 305a is removed by etching, so as to achieve a great reduction of the metal layer 303, where the remaining metal layer 304a includes a portion used as a metal nanowire and an excess portion located on the top surface of the patterned core layer 302 and on the surface of the etching stop layer 301 outside the sidewall 305 a; and then, removing the redundant metal layer on the top surface of the patterned core layer 302 and on the surface of the etching stop layer 301 outside the side wall 305a by adopting a second wet etching process. In the ion beam etching process and the second wet etching process, the metal layer sandwiched between the sidewall 305a and the patterned core layer 302 is not subjected to additional etching, so that the metal nanowire 304b with an outer sidewall in an "L" shape is formed, and critical dimensions such as top height, bottom line width, and overall line width of the metal nanowire 304b can meet the device manufacturing requirements. The second wet etching process may perform a certain over-etching on the metal layer, so that the top surface of the formed metal nanowire 304b is lower than the top surface of the patterned core layer 302, and a part of the metal nanowire 304b at the bottom of the sidewall 305a is also etched away, so that a part of the bottom of the sidewall 305a is suspended. Wherein the etchant of the second wet etching process comprises Sodium hypochlorite solution (Sodium hypochlorite).
referring to fig. 3G, in order to provide a relatively flat process surface for the subsequent processes, in step S4, after the metal nanowires 304b are formed, a chemical mechanical planarization process may be used to planarize the top surfaces of the side walls 305a to the top surface of the patterned core layer 302, i.e., to make the top surfaces of the side walls 35a flush with the top surface of the patterned core layer 302. In addition, the sidewall spacers 305a may be subsequently removed by an etching process as required to completely expose the outer sidewalls of the metal nanowires 304 b.
according to the manufacturing method of the metal nanowire, the appearance of the outer side wall of the metal nanowire 304b can be limited and protected by the formed side wall 305a, so that the metal nanowire is L-shaped, continuous and high in thickness uniformity; the metal nanowire can be used as a conductive structure such as an interconnection line or a contact plug, and is beneficial to reducing the size of a chip, improving the density of an integrated circuit device, reducing the resistivity, improving the characteristics of an electric appliance, and improving the reliability and the yield of products.
referring to fig. 2B, the present invention further provides a method for manufacturing a semiconductor device, in which the method for manufacturing a metal nanowire shown in fig. 2A is used to form a metal nanowire on a surface of a semiconductor substrate, and the method for manufacturing a semiconductor device specifically includes the following steps:
s0, providing a semiconductor substrate;
S1, forming a patterned core layer on a semiconductor substrate, wherein the core layer exposes a part of the surface of the semiconductor substrate;
s2, forming a metal layer, wherein the metal layer covers the core layer and the surface of the semiconductor substrate;
s3, forming a side wall on the side wall of the patterned core layer, wherein the side wall covers the metal layer on the side wall of the patterned core layer;
S4, removing the metal layers on the top surface of the core layer and the surface of the semiconductor substrate outside the side wall to form a metal nanowire;
s5, covering a passivation layer on the surface of the semiconductor substrate, wherein the passivation layer also covers the side wall, the core layer and the top surface of the metal nanowire;
S6, etching the passivation layer to form a groove exposing the side wall, the core layer and the top surface of the metal nanowire in the passivation layer;
and S7, removing the side wall, and forming a conducting layer in the groove, wherein the conducting layer covers the top surfaces of the metal nanowires and the core layer.
referring to fig. 3A, the semiconductor substrate provided in step S0 provides a processing platform for the subsequent steps S1-S7, and the semiconductor substrate provided in step S0 may comprise any semiconductor material, including but not limited to: si, SiC, SiGe, SiGeC, Ge alloys, GeAs, InAs, InP, and other III-V or II-VI compound semiconductors. The semiconductor substrate may also comprise an organic semiconductor or a layered semiconductor such as Si/SiGe, silicon-on-insulator (SOI), or SiGe-on-insulator (sgoi). An isolation structure and a device structure (not marked in the figure) can be further formed in the semiconductor substrate, the isolation structure can be a local isolation structure comprising a device isolation structure used for device isolation and a local area isolation structure used for local area isolation in a device, and the isolation structure can be a shallow trench isolation structure; the device structure can comprise active devices such as MOS transistors and the like or passive devices such as resistors, capacitors and the like. The semiconductor substrate in this embodiment includes a semiconductor base 300 and an etch stop layer 301.
Referring to fig. 3A to 3F, steps S1 to S4 in the method for manufacturing a semiconductor device of the present embodiment correspond to steps S1 to S4 in the method for manufacturing a metal nanowire, respectively, and are not described in detail herein, wherein, referring to fig. 3A and 3B, a patterned core layer 302 is formed on the surface of an etch stop layer 301 in step S1, and the patterned core layer 301 exposes a portion of the surface of the etch stop layer 301; referring to fig. 3C, in step S2, a metal layer 304 is formed to cover the sidewalls and the top surface of the patterned core layer 302 and the exposed surface of the etch stop layer 301; referring to fig. 3C and 3D, in step S3, a sidewall spacer 305a is formed on the sidewall of the metal layer 304; referring to fig. 3E and 3G, in step S4, the metal layer on the top surface of the patterned core layer 302 and on the surface of the etching stop layer 301 outside the sidewall 305a is removed, so as to form the metal nanowire 304b with the outer sidewall still in the shape of "L" between the sidewall 305a and the patterned core layer 302, and make the top surface of the sidewall 305a flush with the top surface of the patterned core layer 302.
referring to fig. 3H, in step S5, a Passivation layer (Passivation)306 may be first covered on the surfaces of the etching stop layer 301, the sidewall 305a, the metal nanowire 304b and the patterned core layer 302 by physical vapor deposition, chemical vapor deposition, atomic deposition or coating, and the like, where the deposition thickness of the Passivation layer (Passivation)306 on the etching stop layer 301 outside the sidewall 305a is greater than the deposition thickness of the core layer 302 on the etching stop layer 301, and the material of the Passivation layer 306 is different from the sidewall 305a and the etching stop layer 301, so that the sidewall 305a and the Passivation layer 306 have a higher etching selection ratio in the subsequent process of removing the sidewall 305a by etching, so as to facilitate the removal of the sidewall 305 a. The passivation layer 306 may be made of at least one of silicon oxide, silicon oxynitride, silicon nitride, low-K dielectric (including organic dielectric and inorganic dielectric), and spin-on carbon. In addition, the deposited passivation layer 306 may be subjected to chemical mechanical planarization, which may provide a relatively flat process surface, and may rapidly thin the passivation layer 306, so as to reduce the etching time in the subsequent step S6.
Referring to fig. 3I, in step S6, the passivation layer 306 may be etched by a dry etching process to open the patterned core layer 302 to a region of the sidewall 305a, so as to form a trench 306a exposing the sidewall 305a, the patterned core layer 302, and the top surface of the metal nanowire 304 b.
Referring to fig. 3J and 3K, in step S7, the sidewall 305a may be removed by at least one of a wet etching process and a dry etching process, and then the trench 306a is filled with the conductive layer 307 by vacuum evaporation, sputtering, or the like until the conductive layer 307 fills or overflows the trench 306a, where the conductive layer 307 is made of at least one of titanium, tantalum, aluminum, copper, nickel, cobalt, and tungsten, and at this time, the conductive layer 307 covers not only the metal nanowire 304b and the core layer 302 in the trench 306a, but also the top surface of the passivation layer 306. The conductive layer 307 may then be top planarized as desired so that the top surface of the conductive layer 307 is flush with the top surface of the passivation layer 306. In other embodiments of the present invention, the top surface of the conductive layer 307 may also be lower than the top surface of the passivation layer 306, and can cover the surface of the metal nanowire 304b and the core layer 302 exposed by the trench 306 a.
in view of the above, the method for manufacturing a semiconductor device according to the present invention can obtain a metal nanowire having a better sidewall morphology and a higher thickness uniformity because the metal nanowire is manufactured by using the method for manufacturing a metal nanowire according to the present invention, thereby improving the performance of the finally manufactured device and increasing the yield of the product.
Referring to fig. 3K, the present invention further provides a semiconductor device, including: a semiconductor substrate mainly formed by stacking a semiconductor base 300 and an etching stop layer 301; a patterned core layer 302 located on the etch stop layer 301 and exposing a portion of the surface of the etch stop layer 301; and the metal nanowire 304b is positioned on the etching stop layer 301 and attached to the side wall of the patterned core layer 302, and the outer side wall of the metal nanowire 304b is in an 'L' shape. In addition, the semiconductor device may further include a passivation layer 306 and a conductive layer 307, wherein the passivation layer 306 is located on the surface of the etch stop layer 301 outside the metal nanowire 304b, the top surface of the passivation layer 306 is higher than the top surface of the patterned core layer 302, and a gap may be formed between the passivation layer 306 and the metal nanowire 304b, and the width of the gap from the passivation layer 306 to the metal nanowire 304b may be 2nm to 20 nm; the conductive layer 307 covers the top surface of the patterned core layer 302 and the top surface of the metal nanowire 304b and fills the gap between the passivation layer 306 and the metal nanowire 304b, in this embodiment, the top surface of the metal nanowire 304b is lower than the top surface of the patterned core layer 302, the passivation layer 306 has a trench exposing the top surface of the patterned core layer 302 and the top surface and a portion of the outer sidewall of the metal nanowire 304b and forming the gap with the portion of the outer sidewall of the metal nanowire 304b, the conductive layer 307 fills the trench, and the top surface of the conductive layer 307 is flush with the top surface of the passivation layer 306.
it should be noted that the materials of the patterned core layer 302, the metal nanowires 304b, the passivation layer 306, and the conductive layer 307 can be adaptively selected according to the device manufacturing requirements, wherein the material of the patterned core layer 302 includes at least one of silicon oxide, silicon oxynitride, silicon nitride, and low-K dielectric; the material of the metal nanowire 304b may include at least one of ruthenium, molybdenum, tungsten, cobalt, rhenium, iron, osmium, rhodium, iridium, nickel, palladium, platinum, titanium, zirconium, hafnium, vanadium, niobium, tantalum, chromium, and technetium; the passivation layer 306 may be made of at least one of silicon oxide, silicon oxynitride, silicon nitride, spin-on carbon SOC, and low-K dielectric; the conductive layer 307 is made of at least one of titanium, tantalum, aluminum, copper, nickel, cobalt, and tungsten.
According to the semiconductor device, the metal nanowire covers the side wall of the patterned core layer, the outer side wall of the metal nanowire is L-shaped, and the semiconductor device has good side wall appearance and high thickness uniformity, so that the performance of the semiconductor device is guaranteed.
It will be apparent to those skilled in the art that various changes and modifications may be made in the invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.
Claims (23)
1. A method of fabricating a metal nanowire, comprising the steps of:
forming a patterned core layer on a semiconductor substrate, wherein the patterned core layer exposes a part of the surface of the semiconductor substrate;
forming a metal layer covering the patterned core layer and the surface of the semiconductor substrate;
forming a side wall on the side wall of the patterned core layer, wherein the side wall covers the metal layer on the side wall of the patterned core layer;
and removing the metal layer on the top surface of the patterned core layer and the surface of the semiconductor substrate outside the side wall to form the metal nanowire.
2. The method of claim 1, wherein the material of the patterned core layer comprises at least one of silicon oxide, silicon oxynitride, silicon nitride, and a low-K dielectric.
3. The method of manufacturing a metal nanowire according to claim 1, wherein a material of the metal layer includes at least one of ruthenium, molybdenum, tungsten, cobalt, rhenium, iron, osmium, rhodium, iridium, nickel, palladium, platinum, titanium, zirconium, hafnium, vanadium, niobium, tantalum, chromium, and technetium.
4. The method of claim 1, wherein the step of forming a sidewall on the sidewall of the metal layer comprises:
Depositing a side wall material layer on the surface of the metal layer;
And removing the side wall material layer above the top surface of the patterned core layer and part of the side wall material layer above the surface of the semiconductor substrate outside the patterned core layer to form a side wall covering the side wall of the metal layer.
5. the method according to claim 4, wherein the sidewall material layer on the top surface of the patterned core layer is removed by a chemical mechanical planarization process, and then the portion of the sidewall material layer on the top surface of the semiconductor substrate outside the patterned core layer is removed by a first wet etching process to form a sidewall covering the sidewall of the metal layer; or, the side wall material layer is etched to the surface of the metal layer through a first wet etching process, and then the top surface of the rest side wall material layer is flattened to the top surface of the patterned core layer through a chemical mechanical planarization process.
6. the method according to claim 4, wherein the sidewall material layer is deposited to a thickness of 2nm to 20 nm.
7. The method of claim 1, wherein the step of removing the metal layer on the top surface of the patterned core layer and on the surface of the semiconductor substrate outside the sidewall to form the metal nanowire comprises:
Thinning the metal layer by adopting a dry etching process;
And removing the residual metal layer on the top surface of the patterned core layer and the surface of the semiconductor substrate outside the side wall by adopting a second wet etching process to form the metal nanowire.
8. The method of manufacturing metal nanowires of claim 7, wherein the dry etching process is an ion beam etching process.
9. The method of manufacturing metal nanowires of claim 7, wherein the second wet etching process over-etches the metal layer such that top surfaces of the formed metal nanowires are lower than top surfaces of the core layer.
10. The method of manufacturing metal nanowires of claim 7 or 9, wherein the etchant of the second wet etching process comprises a sodium hypochlorite solution.
11. the method of claim 1, wherein after forming the metal nanowires, planarizing a top surface of the sidewall spacers to a top surface of the core layer.
12. A method of manufacturing a semiconductor device, comprising the steps of:
Providing a semiconductor substrate;
the method for manufacturing a metal nanowire according to any one of claims 1 to 11, wherein the metal nanowire is formed on a surface of the semiconductor substrate.
13. The method for manufacturing a semiconductor device according to claim 12, further comprising:
covering a passivation layer on the surface of the semiconductor substrate, wherein the passivation layer also covers the side wall, the patterned core layer and the top surface of the metal nanowire;
etching the passivation layer to form a groove exposing the side wall, the patterned core layer and the top surface of the metal nanowire in the passivation layer;
And removing the side wall, and forming a conducting layer in the groove, wherein the conducting layer covers the top surfaces of the metal nanowires and the core layer.
14. The method for manufacturing a semiconductor device according to claim 13, wherein the passivation layer is also subjected to top surface planarization before the passivation layer is etched.
15. the method for manufacturing a semiconductor device according to claim 13, wherein a material of the conductive layer includes at least one of titanium, tantalum, aluminum, copper, nickel, cobalt, and tungsten.
16. The method for manufacturing a semiconductor device according to claim 13, wherein a top surface of the conductive layer is lower than a top surface of the passivation layer, or wherein the conductive layer at least fills the trench.
17. a semiconductor device, comprising:
a semiconductor substrate;
the patterned core layer is positioned on the semiconductor substrate and exposes part of the surface of the semiconductor substrate;
and the metal nanowire is positioned on the semiconductor substrate and attached to the side wall of the patterned core layer, and is L-shaped.
18. The semiconductor device of claim 17, wherein a top surface of the metal nanowire is lower than a top surface of the patterned core layer.
19. The semiconductor device of claim 17, wherein a material of the patterned core layer comprises at least one of silicon oxide, silicon oxynitride, silicon nitride, and a low-K dielectric.
20. the semiconductor device according to claim 17, wherein a material of the metal nanowire comprises at least one of ruthenium, molybdenum, tungsten, cobalt, rhenium, iron, osmium, rhodium, iridium, nickel, palladium, platinum, titanium, zirconium, hafnium, vanadium, niobium, tantalum, chromium, and technetium.
21. The semiconductor device according to claim 17, further comprising: and the passivation layer is positioned on the surface of the semiconductor substrate outside the metal nanowire, the top surface of the passivation layer is higher than that of the patterned core layer, and a gap is formed between the passivation layer and the metal nanowire.
22. the semiconductor device according to claim 21, wherein a width of the slit from the passivation layer to the metal nanowire is 2nm to 20 nm.
23. the semiconductor device of claim 21, further comprising a conductive layer covering a top surface of the patterned core layer and a top surface of the metal nanowire and filling the gap.
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