TWI833547B - Manufacturing method of semiconductor device - Google Patents

Abstract

The disclosure provides a method for manufacturing a semiconductor device. The method includes following steps: sequentially forming a barrier layer and a first anti-reflection layer on the substrate with the array area and the peripheral area. The first anti-reflection layer in the peripheral area is etched, and an underlayer is formed on the first anti-reflection layer in the peripheral area. A second anti-reflection layer is formed on the underlayer in the peripheral area. An ashable hard mask layer is formed on the first anti-reflection layer in the array area and the underlayer layer in the peripheral area. A third anti-reflection layer is formed on the ashable hard mask layer. A bottom antireflection layer and a photoresist layer are sequentially formed on the third antireflection layer. The method can improve the etch selectivity of the dielectric film stack, so as to reduce the problems of short circuit or disconnection of metal lines and landing pads.

Description

Semiconductor device manufacturing method

The present disclosure relates to a manufacturing method of a semiconductor device.

The semiconductor integrated circuit (IC) industry has experienced rapid development and has been committed to increasing device density, improving performance and reducing costs. However, problems involving manufacturing and design are currently being faced. For example, as the size of devices shrinks, over-etching may occur during the etching process, which may cause problems such as undesirable leakage current, undesirable conduction between electronic components, and finally Reducing the reliability of the device.

In view of this, one purpose of the present disclosure is to propose a semiconductor device manufacturing method that can solve the above problems, especially a method that makes the subsequent etching process more efficient by improving the etch selectivity of dielectric film stacks. Accurate method.

One embodiment of the present invention provides a method for manufacturing a semiconductor device including the following steps. A barrier layer and a first anti-reflective layer are sequentially formed on the substrate having the array area and the peripheral area. The first anti-reflective layer in the peripheral area is etched, and a lining layer is formed on the first anti-reflective layer in the peripheral area. A second anti-reflective layer is formed on the lining layer in the peripheral area. An ashesable hard mask layer is formed on the first anti-reflective layer in the array area and the lining layer in the peripheral area. A third anti-reflective layer is formed on the ashingable hard mask layer. A bottom anti-reflective layer and a photoresist layer are sequentially formed on the third anti-reflective layer.

In some embodiments, the method further includes: forming a device layer on the substrate before forming the barrier layer on the substrate.

In some embodiments, the method further includes: performing a protective treatment on the first anti-reflective layer in the array area before etching the first anti-reflective layer in the peripheral area.

In some embodiments, the barrier layer and the ashedable hard mask layer include carbon-based materials.

In some embodiments, the first anti-reflective layer and the second anti-reflective layer include silicon-rich silicon oxynitride material.

In some embodiments, the third anti-reflective layer includes oxygen-rich silicon oxynitride material.

In some embodiments, a plasma enhanced chemical vapor deposition method is used to form the barrier layer, the first anti-reflective layer, the second anti-reflective layer, the third anti-reflective layer and the ashing hard mask layer.

In some embodiments, the first anti-reflective layer has a thickness greater than a thickness of the second anti-reflective layer.

In some embodiments, after the photoresist layer is formed, the photoresist layer is patterned, and the third anti-reflective layer and the bottom anti-reflective layer are etched using the patterned photoresist layer as a mask.

In some embodiments, the etched third anti-reflective layer and the bottom anti-reflective layer are used as masks, and the etching can ashes the hard mask layer.

In order to make the description of the present disclosure more detailed and complete, aspects and specific implementations of the present disclosure are described below by way of examples. Although a series of operations or steps are used to illustrate the method of the present disclosure below, the order shown in these operations or steps should not be construed as a limitation of the disclosure. For example, certain operations or steps may be performed in a different order and/or concurrently with other steps. Furthermore, not all illustrated operations, steps, and/or features must be performed to implement embodiments of the invention, and each operation or step described herein may include several sub-steps or actions.

For ease of description, spatially relative terms (such as "under", "below", "below", "above", "above", etc.) may be used in this article to describe what is shown in the figure The relationship between one element or characteristic and another element or characteristic. It will be understood that the spatially relative terms encompass different orientations of use or operation of the device in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" or "above" the other elements or features. Thus, for example, the term "below" may include both upper and lower orientations. The device may be otherwise oriented using the spatially relative descriptors corresponding to that orientation.

The present disclosure provides a method of manufacturing a semiconductor device. 1-7 are schematic cross-sectional views of a manufacturing stage of a semiconductor structure according to some embodiments of the invention. Referring to FIG. 1 , the substrate 110 of the semiconductor device 100 has an array area A1 and a peripheral area A2. First, the element layer 120 is formed on the substrate 110 in the array area A1 and the peripheral area A2. The component layer 120 may include a plurality of integrated circuit components, which may include active components, such as transistors, switching components, etc., and/or passive components, such as resistors, capacitors, inductors, converters, etc., and The element layer 120 may have different element distribution and/or surface topography in the array area A1 and the peripheral area A2.

For example, the element layer 120 in the array area A1 may include core circuit elements, while the element layer 120 in the peripheral area A2 may have peripheral circuit elements. The elements in the array area A1 and the elements in the peripheral area A2 may be made of metal. lines connected together. To facilitate understanding, the component layer 120 is simplified in the drawings herein.

In some embodiments, the substrate 110 includes elemental semiconductors, including silicon or germanium in crystalline, polycrystalline and/or amorphous structures; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, arsenide Indium and/or indium antimonide; alloy semiconductors including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP and/or GaInAsP; any other suitable material; and/or combinations thereof.

As shown in FIG. 1 , barrier layers 130 are respectively formed on the element layer 120 of the array area A1 and the element layer 120 of the peripheral area A2 by, for example, plasma-enhanced chemical vapor deposition (PECVD). . In some embodiments, the barrier layer 130 includes a carbon-based material, where the thickness of the barrier layer 130 may be approximately 60±1.5 nanometer (nm).

As shown in FIG. 1 , next, first anti-reflection layers 140 are respectively formed on the barrier layer 130 of the array area A1 and the barrier layer 130 of the peripheral area A2 by, for example, plasma enhanced chemical vapor deposition (PECVD). In some embodiments, the first anti-reflective layer 140 includes silicon-rich silicon oxynitride (SiO _ₓ N _y ) material, wherein the first anti-reflective layer 140 has a refractive index greater than approximately 1.7. In some implementations, the thickness of the first anti-reflective layer 140 may be approximately 50±2 nm. Since the material of the first anti-reflective layer 140 is different from the material of the barrier layer 130 , the etching selectivity ratio can be improved.

As shown in FIG. 1 , the first anti-reflective layer 140 in the peripheral area A2 is etched to form a plurality of trenches 142 in the peripheral area A2. In some embodiments, the trench 142 may be formed by, for example, dry etching, wet etching, or other etching methods. In the case of dry etching, a reactive ion etching (RIE) process may be used. The illustration of trench 142 is presented simplified herein.

Although not shown in the drawings, in some embodiments, before etching the first anti-reflective layer 140 in the peripheral area A2, the elements in the array area A1 may be protected first. For example, a mask layer (not shown) can be deposited on the first anti-reflective layer 140 in the array area A1 first, so that the elements in the array area A1 are protected from being affected by or damaged by subsequent processing in the peripheral area A2 .

As shown in FIG. 2 , an underlayer 150 is formed on the first anti-reflection layer 140 in the peripheral area A2. The lining layer 150 can be made of various suitable materials. If a material different from the first anti-reflective layer 140 is chosen, the etching selectivity ratio can be further improved. In some embodiments, a planarization process may be performed on the liner layer 150 before proceeding with subsequent steps. The planarization process includes chemical mechanical planarization (CMP), and other suitable processes can also be selected. The illustrations of liner 150 are presented simplified herein.

As shown in FIG. 3 , a second anti-reflective layer 160 is formed on the liner 150 of the peripheral area A2 by, for example, plasma enhanced chemical vapor deposition (PECVD). In some embodiments, the second anti-reflective layer 160 includes silicon-rich silicon oxynitride (SiOₓN _y ) material, wherein the refractive index of the second anti-reflective layer 160 is approximately greater than 1.7. The thickness of the second anti-reflective layer 160 may be approximately 15±2 nm. In some embodiments, the thickness of the second anti-reflective layer 160 is less than the thickness of the first anti-reflective layer 140 . Both the first anti-reflective layer 140 and the second anti-reflective layer 160 include silicon-rich silicon oxynitride. The proportions of silicon in the first anti-reflective layer 140 and the second anti-reflective layer 160 may be exactly the same or different.

Although not shown in the drawings, in some embodiments, after forming the second anti-reflective layer 160 in the peripheral area A2, the mask layer protecting the array area A1 may be removed using, for example, a planarization process to expose the array area. The first anti-reflective layer 140 of A1. In some embodiments, the planarization process includes chemical mechanical planarization (CMP), but other suitable processes may also be selected.

As shown in FIG. 4 , an asheable hardened layer is formed on the first anti-reflective layer 140 of the array area A1 and the second anti-reflective layer 160 of the peripheral area A2 by, for example, plasma enhanced chemical vapor deposition (PECVD). Mask layer 170. In some embodiments, the ashing hard mask layer 170 includes a carbon-based material, wherein the thickness of the ashing hard mask layer 170 may be approximately 60 ± 2.5 nm. In some embodiments, the material of the ashing hard mask layer 170 is different from the materials of the first anti-reflective layer 140 of the array area A1 and the second anti-reflective layer 160 of the peripheral area A2, which can improve the etching selectivity. In some embodiments, the barrier layer 130 and the ashedable hard mask layer 170 both include carbon-based materials, and the barrier layer 130 and the ashedable hard mask layer 170 may be formed of the same material. In some embodiments, the barrier layer 130 and the ashable hard mask layer 170 may have the same thickness or may have different thicknesses.

As shown in FIG. 5 , the asheable hard mask layer 170 in the array area A1 and the asheable hard mask layer 170 in the peripheral area A2 are respectively formed by, for example, plasma enhanced chemical vapor deposition (PECVD). Third anti-reflective layer 180. In some embodiments, the third anti-reflective layer 180 includes oxygen-rich silicon oxynitride (SiOₓN _y ) material, wherein the refractive index of the third anti-reflective layer 180 is approximately less than 1.7. In some implementations, the thickness of the third anti-reflective layer 180 may be approximately 26 ± 1 nm. In some embodiments, the thickness of the third anti-reflective layer 180 is greater than the thickness of the second anti-reflective layer 160 , and the thickness of the third anti-reflective layer 180 is less than the thickness of the first anti-reflective layer 140 . In other words, in some embodiments, the thickness of the first anti-reflective layer 140 is greater than the thickness of the second anti-reflective layer 160 and also greater than the thickness of the third anti-reflective layer 180 . In some embodiments, the third anti-reflective layer 180 has a higher oxygen content than the first anti-reflective layer 140 and the second anti-reflective layer 160 .

As shown in FIG. 6 , a bottom anti-reflective coating (BARC) 190 is formed on the third anti-reflective layer 180 of the array area A1 and the third anti-reflective layer 180 of the peripheral area A2 respectively. In some implementations, the thickness of bottom anti-reflective layer 190 may be approximately 30 nm. Bottom anti-reflective layer 190 may be formed of silicon oxynitride or other suitable materials.

As shown in FIG. 6 , photoresist layers 200 are respectively formed on the bottom anti-reflective layer 190 of the array area A1 and the bottom anti-reflective layer 190 of the peripheral area A2. In some embodiments, the thickness of photoresist layer 200 may be approximately 120 nm. In some embodiments, the photoresist layer 200 can be a single layer or a multi-layer structure. In some embodiments, a conventional photoresist can be used as the material of the photoresist layer 200 , and the photoresist layer 200 can also be a polymer material.

As shown in FIG. 7 , a subsequent etching process is performed on the array area A1 and the peripheral area A2 in FIG. 6 , and a plurality of trenches 210 are formed. In some embodiments, the trench 210 exposes some portions of the substrate 110, and metal lines or landing pads are formed in the trench 210 in subsequent processes. The metal lines or landing pads can be connected to the lines on the substrate 110 ( if any) connected. The metal lines or landing pads may be formed of, for example, tungsten (W), copper (Cu) aluminum (Al), titanium (Ti), tantalum (Ta), combinations thereof, and/or other suitable conductive materials. In some other embodiments, the step of etching the trench 210 may end at the device layer 120 , and metal lines or landing pads may be formed in the trench 210 in subsequent processes. Metal wires or landing pads may be connected to components in component layer 120 . In some embodiments, the trench 210 may be formed by, for example, dry etching, wet etching, or other etching methods, wherein dry etching may use, for example, a reactive ion etching (RIE) process.

In some embodiments, the etching process described above can be performed in stages. After the photoresist layer 200 is formed, the photoresist layer 200 is first patterned, and the patterning can be performed using a conventional method. Next, the patterned photoresist layer 200 can be used as a mask, and the bottom anti-reflective layer 190 and the third anti-reflective layer 180 of the array area A1 and the peripheral area A2 are etched using a first etching process. Next, the asheable hard mask layer 170 of the array area A1 and the peripheral area A2 can be etched using a second etching process that is different from the first etching process. Next, a third etching process different from the second etching process can be used to etch the first anti-reflective layer 140 of the array area A1 and the second anti-reflective layer 160 of the peripheral area A2. Then, the lining layer 150 of the peripheral region A2 can be etched using a fourth etching process that is different from the third etching process. Next, the first anti-reflective layer 140 of the peripheral area A2 can be etched using a fifth etching process that is different from the fourth etching process. Next, a sixth etching process different from the fifth etching process is used to etch the barrier layer 130 of the array area A1 and the peripheral area A2. The above is only an exemplary description, and each etching process can be increased or decreased according to needs.

With the semiconductor device manufacturing method provided by the present disclosure, by forming multiple layers of dielectric films of different materials and different thicknesses, the etch selectivity of dielectric film stacks can be improved for subsequent etching processes. A more precise groove 210 is formed. In this way, problems such as undesirable leakage current and undesirable conduction between electronic components can be reduced, thereby improving component reliability. For example, it can reduce short circuits or disconnections of metal lines and landing pads in subsequent processes. The semiconductor device manufacturing method provided by the present disclosure can effectively improve device reliability and increase yield.

Although the present disclosure has been described in considerable detail with reference to certain embodiments, other embodiments are possible. Accordingly, the spirit and scope of the appended claims should not be limited to the description of the embodiments contained herein.

It will be apparent to those skilled in the art that various modifications and changes can be made in the structure of the present disclosure without departing from the scope or spirit of the disclosure. In view of the foregoing, it is intended that the present disclosure cover the modifications and variations of this invention falling within the scope of the appended claims.

100:Semiconductor components 110:Substrate 120: component layer 130: Barrier layer 140: First anti-reflective layer 142:Trench 150: Lining 160: Second anti-reflective layer 170: Hard mask layer can be grayed out 180:Third anti-reflective layer 190: Bottom anti-reflective layer 200: Photoresist layer 210:Trench A1: Array area A2: Surrounding area

When reading the accompanying drawings, various aspects of the present disclosure can be fully understood from the following detailed description, and reference can be made to the accompanying drawings and the various embodiments described below. The same numbers in the drawings represent the same or similar of components. In addition, in order to simplify the illustration, some commonly used structures and components will be illustrated in a simple schematic manner. 1-7 are schematic cross-sectional views of a manufacturing stage of a semiconductor structure according to some embodiments of the invention.

Domestic storage information (please note in order of storage institution, date and number) without Overseas storage information (please note in order of storage country, institution, date, and number) without

100:Semiconductor components

110:Substrate

120: component layer

130: Barrier layer

140: First anti-reflective layer

150: Lining

160: Second anti-reflective layer

170: Hard mask layer can be grayed out

180:Third anti-reflective layer

190: Bottom anti-reflective layer

200: Photoresist layer

A1: Array area

A2: Surrounding area

Claims (10)

A method for manufacturing semiconductor components, including: A barrier layer and a first anti-reflective layer are sequentially formed on a substrate having an array area and a peripheral area; Etching the first anti-reflective layer in the peripheral area; and forming a lining layer on the first anti-reflective layer in the peripheral area; forming a second anti-reflective layer on the liner in the peripheral area; Form an ashesable hard mask layer on the first anti-reflective layer in the array area and the liner layer in the peripheral area; forming a third anti-reflective layer on the ashingable hard mask layer; and A bottom anti-reflective layer and a photoresist layer are sequentially formed on the third anti-reflective layer. The method of claim 1, further comprising: forming a component layer on the substrate before forming the barrier layer on the substrate. The method of claim 1, further comprising: performing a protective treatment on the first anti-reflective layer in the array area before etching the first anti-reflective layer in the peripheral area. The method of claim 1, wherein the barrier layer and the ashing hard mask layer comprise a carbon-based material. The method of claim 1, wherein the first anti-reflective layer and the second anti-reflective layer include a silicon-rich silicon oxynitride material. The method of claim 1, wherein the third anti-reflective layer includes an oxygen-rich silicon oxynitride material. The method of claim 1, wherein the barrier layer, the first anti-reflective layer, the second anti-reflective layer, the third anti-reflective layer and the ashing hard layer are formed by plasma enhanced chemical vapor deposition. Mask layer. The method of claim 1, wherein the first anti-reflective layer has a thickness greater than a thickness of the second anti-reflective layer. The method of claim 1, wherein after forming the photoresist layer, the photoresist layer is patterned, and the third anti-reflective layer and the bottom anti-reflective layer are etched using the patterned photoresist layer as a mask. layer. The method of claim 9 further includes etching the ashingable hard mask layer using the etched third anti-reflective layer and the bottom anti-reflective layer as masks.

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