CN110570815A - Clock control device and driving method thereof - Google Patents
Clock control device and driving method thereof Download PDFInfo
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- CN110570815A CN110570815A CN201910752665.0A CN201910752665A CN110570815A CN 110570815 A CN110570815 A CN 110570815A CN 201910752665 A CN201910752665 A CN 201910752665A CN 110570815 A CN110570815 A CN 110570815A
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- 238000000034 method Methods 0.000 title claims abstract description 31
- 239000010409 thin film Substances 0.000 claims abstract description 11
- 230000003321 amplification Effects 0.000 claims 4
- 238000003199 nucleic acid amplification method Methods 0.000 claims 4
- 238000004519 manufacturing process Methods 0.000 abstract description 4
- 238000012986 modification Methods 0.000 description 4
- 230000004048 modification Effects 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 229920001621 AMOLED Polymers 0.000 description 2
- 230000004075 alteration Effects 0.000 description 2
- 238000004458 analytical method Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
Classifications
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
- G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
Abstract
A clock pulse control device for providing display clock pulse signals for controlling the display screen of a display device in an output mode comprises a clock pulse control circuit and a clock pulse voltage lifting circuit connected with the clock pulse control circuit. The clock control circuit is configured to output a plurality of initial clock signals. The clock voltage raising circuit receives a plurality of initial clock signals and correspondingly generates a plurality of display clock signals according to the initial clock signals. Wherein the high and low voltage ranges of the display clock signal are within the switch voltage range of the thin film transistor of the display device. The clock pulse control device and the driving method thereof have high interface reusability, further simplify the external circuit of the display and reduce the production cost of the display device.
Description
[ technical field ] A method for producing a semiconductor device
The present disclosure relates to the field of display technologies, and in particular, to a clock control apparatus and a driving method thereof.
[ background of the invention ]
In order to meet the operation requirement of the conventional Active-matrix organic light-emitting diode (AMOLED), a Gate On Array (GOA) panel driving circuit device having a plurality of clocks is often used. However, the voltage amplitude of the clock signal outputted by the clock Controller (TCON) is too low, and the thin film transistor of the display cannot be directly switched according to the output signal of the clock Controller, thereby limiting the multiplexing of the output interface of the clock Controller and the flexibility of the circuit design.
Therefore, it is desirable to provide a clock control apparatus and a driving method thereof to solve the problems of the prior art.
[ summary of the invention ]
To solve the above problems, the present disclosure provides a clock control device and a driving method thereof, which can improve the reusability of the clock control device, further simplify the external circuit of the display and reduce the production cost of the display.
To achieve the above object, the present disclosure provides a clock control apparatus configured to output a display clock signal for controlling a display screen of a display apparatus, the clock control apparatus comprising: the clock pulse voltage raising circuit receives the plurality of initial clock pulse signals and correspondingly generates a plurality of display clock pulse signals according to the initial clock pulse signals, wherein the high-low voltage range of the display clock pulse signals is within the voltage switching range of the thin film transistor of the display device.
In one embodiment of the disclosure, the clock control device further includes a multiplexing interface device, and the multiplexing interface device is connected to the clock voltage boost circuit.
In an embodiment of the disclosure, the clock voltage boosting circuit further includes a plurality of initial clock signal amplifying units, and the number of the initial clock signal amplifying units is the same as the number of the initial clock signals.
in an embodiment of the disclosure, the clock voltage boost circuit further includes at least one clock boost interface, and the at least one clock boost interface is connected to at least one of the initial clock signal amplifying units.
In an embodiment of the disclosure, the clock voltage boost circuit further includes at least one clock boost interface, and the at least one clock boost interface is connected to the plurality of initial clock signal amplifying units.
In order to achieve the above object, the present disclosure further provides a method for driving a clock control device, where the method for driving a clock control device includes providing a plurality of initial clock signals, transmitting all the initial clock signals to a clock voltage boosting circuit, and generating a display clock signal according to the received initial clock signals by the clock voltage boosting circuit, where a high-low voltage range of the display clock signal is within a switching voltage range of a thin film transistor of the display device.
In one embodiment of the disclosure, the clock control device driving method further includes transmitting the display clock signal to a multiplexing interface device after the clock voltage boosting circuit generates the display clock signal according to the received initial clock signal.
In an embodiment of the disclosure, in a process of generating a display clock signal according to the received initial clock signal, the clock voltage boosting circuit further includes a unit for transmitting the initial clock signal to an initial clock signal amplifying unit.
In an embodiment of the disclosure, in a process of generating a display clock signal according to the received initial clock signal, the clock voltage boost circuit further includes transmitting a signal processed by the initial clock signal amplifying unit to at least one clock boost interface.
In an embodiment of the present disclosure, in a process of generating a display clock signal according to the received initial clock signal, the clock voltage boost circuit further includes a clock boost interface for transmitting a plurality of signals processed by the initial clock signal amplifying unit.
The clock pulse control device comprises a clock pulse control circuit which is configured to be used for outputting a plurality of initial clock pulse signals, and a clock pulse voltage lifting circuit which is connected with the clock pulse control circuit and is used for receiving the plurality of initial clock pulse signals and correspondingly generating a plurality of display clock pulse signals according to the initial clock pulse signals, wherein the high-low voltage range of the display clock pulse signals is within the voltage switching range of a thin film transistor of the display device.
In order to make the aforementioned and other aspects of the present disclosure more comprehensible, preferred embodiments accompanied with figures are described in detail below:
[ description of the drawings ]
FIG. 1 is a block diagram of a clock control apparatus according to an embodiment of the disclosure;
FIG. 2 is a block diagram of a clock control apparatus according to an embodiment of the disclosure;
FIG. 3 is a flowchart illustrating a clock control method according to an embodiment of the disclosure.
[ detailed description ] embodiments
The following description of the embodiments refers to the accompanying drawings, which are included to illustrate specific embodiments in which the disclosure may be practiced. Directional phrases used in this disclosure, such as [ upper ], [ lower ], [ front ], [ back ], [ left ], [ right ], [ inner ], [ outer ], [ side ], etc., refer only to the directions of the attached drawings. Accordingly, the directional terms used are used for the purpose of illustration and understanding of the present disclosure, and are not used to limit the present disclosure.
In the drawings, elements having similar structures are denoted by the same reference numerals.
Fig. 1 is a block diagram illustrating a clock control apparatus according to an embodiment of the disclosure. As shown, the clock control apparatus 10 includes a clock control circuit 100 and a clock voltage boosting circuit 200. The clock control circuit 100 is configured to output a plurality of initial clock signals. The clock voltage boost circuit 200 is connected to the clock control circuit 100, and the clock voltage boost circuit 200 receives a plurality of initial clock signals and generates a plurality of display clock signals according to the initial clock signals. Wherein the high and low voltage ranges of the display clock signal are within the voltage switching range of the thin film transistor of the display device.
The high-low voltage range refers to a voltage difference between the highest voltage and the lowest voltage output by the display clock signal, and the voltage switching range refers to a voltage difference between the highest voltage and the lowest voltage for driving the transistor switch.
referring to fig. 1, to facilitate description of the embodiments of the present disclosure, the plurality of initial clock signals in fig. 1 include a first initial clock signal Ck1_ in, a second initial clock signal Ck2_ in, a third initial clock signal Ck3_ in, a fourth initial clock signal Ck4_ in, a fifth initial clock signal Ck5_ in, a sixth initial clock signal Ck6_ in, a seventh initial clock signal Ck7_ in, an eighth initial clock signal Ck8_ in, a ninth initial clock signal Ck9_ in, a tenth initial clock signal Ck10_ in, an eleventh initial clock signal Ck11_ in, and a twelfth initial clock signal Ck12_ in.
For convenience of describing the embodiment of the present disclosure, the plurality of display clock signals include a first display clock signal Ck1_ out, a second display clock signal Ck2_ out, a third display clock signal Ck3_ out, a fourth display clock signal Ck4_ out, a fifth display clock signal Ck5_ out, a sixth display clock signal Ck6_ out, a seventh display clock signal Ck7_ out, an eighth display clock signal Ck8_ out, a ninth display clock signal Ck9_ out, a tenth display clock signal Ck10_ out, an eleventh display clock signal Ck11_ out, and a twelfth display clock signal Ck12_ out.
Referring to fig. 1, the clock voltage boost circuit 200 further includes a plurality of initial clock signal amplifying units. In an embodiment of the disclosure, the number of the initial clock signal amplifying units is the same as the number of the initial clock signals.
Each initial clock signal is amplified by a corresponding initial clock signal amplifying unit to generate a corresponding display clock signal. The clock voltage boosting circuit 200 includes a first initial clock signal amplifying unit a1, a second initial clock signal amplifying unit a2, a third initial clock signal amplifying unit A3, a fourth initial clock signal amplifying unit a4, a fifth initial clock signal amplifying unit a5, a sixth initial clock signal amplifying unit A6, a seventh initial clock signal amplifying unit a7, an eighth initial clock signal amplifying unit A8, a ninth initial clock signal amplifying unit a9, a tenth initial clock signal amplifying unit a10, an eleventh initial clock signal amplifying unit a11, and a twelfth initial clock signal amplifying unit a 12.
The first initial clock signal amplifying unit a1 is configured to receive the first initial clock signal Ck1_ in and output the first display clock signal Ck1_ out, the second initial clock signal amplifying unit a2 is configured to receive the second initial clock signal Ck2_ in and output the second display clock signal Ck2_ out, the third initial clock signal amplifying unit A3 is configured to receive the third initial clock signal Ck3_ in and output the third display clock signal Ck3_ out, the fourth initial clock signal amplifying unit a4 is configured to receive the fourth initial clock signal Ck4_ in and output the fourth display clock signal Ck4_ out, the fifth initial clock signal amplifying unit A5 is configured to receive the fifth initial clock signal Ck5_ in and output the fifth display clock signal Ck5_ out, the sixth initial clock signal amplifying unit A6 is configured to receive the sixth initial clock signal Ck1_ in and output the sixth display clock signal Ck6 9_ out, and output the sixth display clock signal Ck6 9_ out, The seventh initial clock signal amplifying unit a7 is configured to receive the seventh initial clock signal Ck7_ in and output the seventh display clock signal Ck7_ out, the eighth initial clock signal amplifying unit A8 is configured to receive the eighth initial clock signal Ck8_ in and output the eighth display clock signal Ck8_ out, the ninth initial clock signal amplifying unit a9 is configured to receive the ninth initial clock signal Ck9_ in and output the ninth display clock signal Ck9_ out, the tenth initial clock signal amplifying unit a10 is configured to receive the tenth initial clock signal Ck10_ in and output the tenth display clock signal Ck10_ out, the eleventh initial clock signal amplifying unit a11 is configured to receive the eleventh initial clock signal Ck11_ in and output the eleventh display clock signal Ck11_ out, and the twelfth initial clock signal amplifying unit a12 is configured to receive the twelfth initial clock signal Ck12_ in and output the twelfth display clock signal Ck12_ out.
In an embodiment of the present disclosure, each initial clock signal amplifying unit in the clock voltage boosting circuit 200 is configured to output display clock signals having different high and low voltage ranges for the column pixels of at least one row or the row pixels of at least one column in the connected display device. For example, the first display clock signal Ck1_ out corresponds to a first column of sub-pixels of the connected display device, the seventh display clock signal Ck7_ out corresponds to a seventh column of sub-pixels of the connected display device, and the first display clock signal Ck1_ out and the seventh display clock signal Ck7_ out have different output high and low voltage ranges. In other words, in the circuit architecture of the clock control device 10 of the present disclosure, the initial clock signal amplifying unit disposed in the clock voltage boost circuit 200 can be adjusted and replaced to adjust the high-low voltage range and frequency of each display clock signal output by the clock voltage boost circuit, so as to achieve the effect of adjusting the light emitting brightness or the flicker frequency of the light emitting units in the connected display device or at least one row.
In an embodiment of the present disclosure, the range of the display device pixels corresponding to the display clock signal includes a plurality of rows of pixels or a plurality of rows of pixels.
In an embodiment of the present disclosure, the number of the initial clock signal amplifying units is less than the number of the initial clock signals output by the clock control circuit 100. Wherein each initial clock signal amplifying unit is configured to receive more than one initial clock signal.
in one embodiment of the present disclosure, the initial clock signal amplifying unit is constituted by an amplifying circuit including an operational amplifier.
Referring to fig. 2, the difference between the embodiment shown in fig. 1 and the clock control device 10 is that the clock control device further includes a multiplexing interface device P1, and the multiplexing interface device P1 is connected to the clock voltage raising circuit 200.
in one embodiment of the present disclosure, the multiplexing interface device P1 and the clock voltage rising circuit 200 output the display clock signal synchronously. By connecting the multiplexing interface device to a plurality of display devices, the clock control device 10 can directly control the flicker frequency or the light emitting brightness of at least one row of pixels or at least one column of pixels in each display device.
In one embodiment of the present disclosure, the multiplexing interface device P1 is configured to receive a first adjustment signal and output a display adjustment signal according to the first adjustment signal and the received plurality of display clock signals. By the arrangement of the multiplexing interface device P1, the clock control device 10 can output the display adjustment signal according to the first adjustment signal without changing the initial clock signal amplifying unit inside the clock voltage boost circuit 200, thereby improving the applicability of the clock control device 10.
In one embodiment of the present disclosure, the clock voltage boost circuit 200 further comprises at least one clock boost interface, and the clock boost interface is connected to an initial clock signal amplifying unit. For example, the clock voltage boost circuit 200 includes a second clock boost interface connected to the second initial clock signal amplifying unit a 2. Through the configuration of the second clock lifting interface, the user can analyze the first display clock signal Ck1_ out conveniently. Through the setting of the clock pulse lifting interface, a user can conveniently analyze the display clock pulse signal output by the initial clock pulse signal amplifying unit.
in one embodiment of the present disclosure, the clock voltage boost circuit 200 further comprises a plurality of clock boost interfaces. Each clock pulse lifting interface is connected with one initial clock pulse signal amplifying unit, so that a user can analyze the display clock pulse signals output by each initial clock pulse signal amplifying unit conveniently.
in one embodiment of the present disclosure, the clock voltage boost circuit 200 further includes at least one clock boost interface, and the clock boost interface is connected to the plurality of initial clock signal amplifying units. For example, the clock voltage boost circuit 200 includes a first clock boost interface connected to the first initial clock signal amplifying unit a1, the second initial clock signal amplifying unit a2, and the third initial clock signal amplifying unit A3. Through the configuration of the first clock lifting interface, the user can directly receive the first display clock signal Ck1_ out for analysis. Through the setting of the clock pulse lifting interface, a user can conveniently analyze a plurality of display clock pulse signals output by at least one initial clock pulse signal amplifying unit.
Referring to fig. 3, fig. 3 is a flow chart illustrating a clock control method according to an embodiment of the disclosure. To achieve the above object, the present disclosure further provides a driving method of a clock control apparatus, including:
The process S1 provides a plurality of initial clock signals.
the process S2 is to transmit all the initial clock signals to the clock voltage raising circuit.
The process S3 includes the clock voltage raising circuit generating a display clock signal according to the received initial clock signal.
The high and low voltage ranges of the display clock signal are within the switch voltage range of the thin film transistor of the display device.
Through the above process, the user directly controls the clock control device to output the display clock signal with the high-low voltage range within the switch voltage range of the thin film transistor of the display device.
In one embodiment of the present disclosure, after the process S3, the display clock signal is transmitted to the multiplexing interface device. The multiplexing interface device transmits the display clock signal, so that the flicker frequency or the light-emitting brightness of the light-emitting units of at least one row or at least one column in the plurality of display devices connected with the multiplexing interface device can be conveniently controlled.
In one embodiment of the present disclosure, the process S3 further includes transmitting the initial clock signal to an initial clock signal amplifying unit. Wherein, the number of the initial clock signal amplifying units is the same as the number of the initial clock signals. Each initial clock signal is amplified by a corresponding initial clock signal amplifying unit to generate a corresponding display clock signal.
In one embodiment of the present disclosure, the process S3 further includes transmitting the signal processed by the initial clock signal amplifying unit to at least one clock lifting interface. By transmitting the signal processed by the initial clock signal amplifying unit to at least one clock lifting interface, a user can conveniently analyze the display clock signal output by the initial clock signal amplifying unit.
In one embodiment of the present disclosure, the process S3 further includes transmitting the signals processed by the initial clock signal amplifying unit to a clock lifting interface. By transmitting the signals processed by the initial clock signal amplifying unit to a clock lifting interface, a user can conveniently analyze a plurality of display clock signals output by at least one initial clock signal amplifying unit.
In summary, the clock control apparatus provided by the embodiments of the present disclosure includes a clock control circuit and a clock voltage boosting circuit connected to the clock control circuit. The clock control circuit is configured to output a plurality of initial clock signals. The clock voltage raising circuit receives a plurality of initial clock signals and correspondingly generates a plurality of display clock signals according to the initial clock signals. Wherein the high and low voltage ranges of the display clock signal are within the switch voltage range of the thin film transistor of the display device. The clock pulse control device and the driving method thereof have high interface reusability, further simplify the external circuit of the display and reduce the production cost of the display device.
Although the disclosure has been shown and described with respect to one or more implementations, equivalent alterations and modifications will occur to others skilled in the art based upon a reading and understanding of this specification and the annexed drawings. The present disclosure includes all such modifications and alterations, and is limited only by the scope of the appended claims. In particular regard to the various functions performed by the above described components, the terms used to describe such components are intended to correspond, unless otherwise indicated, to any component which performs the specified function of the described component (e.g., that is functionally equivalent), even though not structurally equivalent to the disclosed structure which performs the function in the herein illustrated exemplary implementations of the specification. In addition, while a particular feature of the specification may have been disclosed with respect to only one of several implementations, such feature may be combined with one or more other features of the other implementations as may be desired and advantageous for any given or particular application. Furthermore, to the extent that the terms "includes," has, "" contains, "or variants thereof are used in either the detailed description or the claims, such terms are intended to be inclusive in a manner similar to the term" comprising.
The foregoing is merely a preferred embodiment of the present disclosure, and it should be noted that modifications and refinements may be made by those skilled in the art without departing from the principle of the present disclosure, and these modifications and refinements should also be construed as the protection scope of the present disclosure.
Claims (10)
1. A clock control apparatus configured to output a display clock signal for controlling a display screen of a display apparatus, comprising:
A clock control circuit configured to output a plurality of initial clock signals; and
The clock pulse voltage lifting circuit is connected with the clock pulse control circuit, receives the plurality of initial clock pulse signals and correspondingly generates a plurality of display clock pulse signals according to the initial clock pulse signals;
wherein, the high-low voltage range of the display clock signal is within the voltage switch range of the thin film transistor of the display device.
2. The clock control device of claim 1, further comprising a multiplexing interface device coupled to the clock voltage boost circuit.
3. The clock control device of claim 1, wherein the clock voltage boost circuit is further provided with a plurality of initial clock signal amplification units configured to amplify the initial clock signals, the number of initial clock signal amplification units being the same as the number of initial clock signals.
4. The clock control device of claim 3, wherein the clock voltage boost circuit further comprises at least one clock boost interface, and the at least one clock boost interface is connected to at least one of the initial clock signal amplification units.
5. the clock control device of claim 3, wherein the clock voltage boost circuit further comprises at least one clock boost interface, the at least one clock boost interface being connected to the plurality of initial clock signal amplification units.
6. A driving method of a clock control device is suitable for outputting a display clock signal for controlling a display screen of a display device, and comprises the following steps:
Providing a plurality of initial clock signals;
Transmitting all the initial clock signals to a clock voltage raising circuit; and
The clock pulse voltage lifting circuit generates a display clock pulse signal according to the received initial clock pulse signal;
Wherein, the high-low voltage range of the display clock signal is within the switch voltage range of the thin film transistor of the display device.
7. The clock control device driving method according to claim 6, further comprising transmitting the display clock signal to a multiplexing interface device after the clock voltage boosting circuit generates the display clock signal according to the received initial clock signal.
8. The clock control device driving method according to claim 6, wherein the clock voltage boosting circuit further comprises transmitting the initial clock signal to an initial clock signal amplifying unit in a process of generating a display clock signal according to the received initial clock signal.
9. The clock control device driving method according to claim 8, wherein in the process of generating the display clock signal according to the received initial clock signal, the clock voltage boosting circuit further comprises transmitting the signal processed by the initial clock signal amplifying unit to at least one clock boosting interface.
10. The clock control device driving method according to claim 8, wherein the clock voltage boosting circuit generates the display clock signal according to the received initial clock signal, further comprising transmitting a plurality of signals processed by the initial clock signal amplifying unit to a clock boosting interface.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910752665.0A CN110570815A (en) | 2019-08-15 | 2019-08-15 | Clock control device and driving method thereof |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910752665.0A CN110570815A (en) | 2019-08-15 | 2019-08-15 | Clock control device and driving method thereof |
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| CN110570815A true CN110570815A (en) | 2019-12-13 |
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| CN201910752665.0A Pending CN110570815A (en) | 2019-08-15 | 2019-08-15 | Clock control device and driving method thereof |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN111128088A (en) * | 2020-01-17 | 2020-05-08 | Tcl华星光电技术有限公司 | Driving circuit and display panel applying same |
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| CN101546545A (en) * | 2008-11-28 | 2009-09-30 | 友达光电股份有限公司 | Clock signal generating signal and clock signal generating circuit |
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| TW201409449A (en) * | 2012-07-31 | 2014-03-01 | Sharp Kk | Display device and driving method therefor |
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Address after: 9-2 Tangming Avenue, Guangming New District, Shenzhen City, Guangdong Province Applicant after: TCL China Star Optoelectronics Technology Co.,Ltd. Address before: 9-2 Tangming Avenue, Guangming New District, Shenzhen City, Guangdong Province Applicant before: Shenzhen China Star Optoelectronics Technology Co.,Ltd. |
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Application publication date: 20191213 |
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| RJ01 | Rejection of invention patent application after publication |