CN110569066B - Control method for common code segment of multi-core system, intelligent terminal and storage medium - Google Patents

Control method for common code segment of multi-core system, intelligent terminal and storage medium Download PDF

Info

Publication number
CN110569066B
CN110569066B CN201910683995.9A CN201910683995A CN110569066B CN 110569066 B CN110569066 B CN 110569066B CN 201910683995 A CN201910683995 A CN 201910683995A CN 110569066 B CN110569066 B CN 110569066B
Authority
CN
China
Prior art keywords
core
master
slave
slave core
cpu
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201910683995.9A
Other languages
Chinese (zh)
Other versions
CN110569066A (en
Inventor
李小军
吴闽华
孟庆晓
杨超
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shenzhen Genew Technologies Co Ltd
Original Assignee
Shenzhen Genew Technologies Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shenzhen Genew Technologies Co Ltd filed Critical Shenzhen Genew Technologies Co Ltd
Priority to CN201910683995.9A priority Critical patent/CN110569066B/en
Publication of CN110569066A publication Critical patent/CN110569066A/en
Application granted granted Critical
Publication of CN110569066B publication Critical patent/CN110569066B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/3004—Arrangements for executing specific machine instructions to perform operations on memory
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Multi Processors (AREA)

Abstract

The invention provides a control method of a common code segment of a multi-core system, an intelligent terminal and a storage medium, wherein the method comprises the following steps: when the CPU runs, judging whether the running CPU is a master core or a slave core; if the running CPU is a main core, reading a main core instruction from a pre-established main-slave core code section and executing a control operation corresponding to the main core instruction; and if the running CPU is a slave core, reading a slave core instruction from the master-slave core code section and executing the control operation corresponding to the slave core instruction. The invention establishes the master-slave core code section for storing the master core instruction and the slave core instruction in advance, when the CPU runs, the corresponding control operation in the master-slave core code section is executed by judging whether the master core runs or the slave core runs, the master core and the slave core share one set of codes, the code upgrading and the maintenance are simple, the storage space of an AMP system is saved, and meanwhile, the code running space is saved.

Description

Control method for common code segment of multi-core system, intelligent terminal and storage medium
Technical Field
The present invention relates to the field of embedded systems, and in particular, to a method for controlling a common code segment of a multi-core system, an intelligent terminal, and a storage medium.
Background
In the field of embedded systems, applications for multiple cores are classified into symmetric multiprocessing (Symmetrical Multi-Processing, SMP) and Asymmetric Multiprocessing (AMP), which are adapted to various applications. Although they vary widely, multiple cores within a processor are all started to execute their respective instructions and work.
All cores of the existing SMP system are scheduled and managed by an operating system, each process is switched among a plurality of cores in operation, system performance loss is caused, and the performance of an N-core CPU cannot be equal to the performance of 1 single-core CPU. Whereas each CPU in an AMP system is responsible for handling a single complementary coherent service, the overall N-core CPU performance may approach that of a single-core CPU. But each CPU of the AMP system needs a separate code running space (RAM), and when the system is upgraded and maintained, the code of each CPU code segment needs to be upgraded and maintained, so that the operation is complex, and the large code running space (RAM) is occupied.
Accordingly, there is a need for further improvements in the art.
Disclosure of Invention
In view of the above-mentioned shortcomings in the prior art, the present invention aims to provide a control method, an intelligent terminal and a storage medium for a code segment shared by a multi-core system, which overcome the defects that each CPU of an AMP system in the prior art needs a separate code running space (RAM), and the code upgrading and maintenance are cumbersome and occupy a larger code running space (RAM).
The first embodiment of the invention discloses a control method of a common code segment of a multi-core system, which comprises the following steps:
the control method of the common code segment of the multi-core system is characterized by comprising the following steps:
when the CPU runs, judging whether the running CPU is a master core or a slave core;
if the running CPU is a main core, reading a main core instruction from a pre-established main-slave core code section and executing a control operation corresponding to the main core instruction; the master core code segment and the slave core code segment are respectively used for storing a master core instruction and a slave core instruction;
and if the running CPU is a slave core, reading a slave core instruction from the master-slave core code section and executing the control operation corresponding to the slave core instruction.
The method for controlling the common code segment of the multi-core system, wherein when the CPU runs, the step of judging whether the running CPU is a master core or a slave core further comprises the following steps:
registers for judging whether the running CPU is a master core or a slave core are set in advance.
The method for controlling the common code segment of the multi-core system, wherein when the CPU runs, the step of judging whether the running CPU is a master core or a slave core comprises the following steps:
when the CPU runs, judging whether the running CPU is a master core or a slave core according to the value of the register;
when the value of the register is 0, judging that the running CPU is a main core;
when the value of the register is N, judging that the running CPU is a slave core; wherein N is a number not equal to 0.
The control method of the multi-core system shared code section, wherein the main core comprises the following steps: the first memory management unit, the slave core includes: a second memory management unit;
after the CPU is operated, the step of judging whether the operated CPU is a master core or a slave core further comprises the following steps:
starting a first memory management unit, and mapping the physical address of the master and slave core code segments into a master and slave core code segment virtual address which is the same as the physical address of the master and slave core code segments;
and starting a second memory management unit, and mapping the physical address of the master-slave core code segment into a master-slave core code segment virtual address which is the same as the physical address of the master-slave core code segment.
The method for controlling the common code segment of the multi-core system, wherein if the running CPU is a main core, the steps of reading a main core instruction from the pre-established main-slave core code segment and executing the control operation corresponding to the main core instruction comprise the following steps:
if the running CPU is a main core, determining a physical address of a main core code segment corresponding to a virtual address of a main core code segment accessed by the main core through a first memory management unit;
and reading a main core instruction from the main core code segment and the slave core code segment corresponding to the physical address of the main core code segment and executing the control operation corresponding to the main core instruction.
The method for controlling the common code segment of the multi-core system, wherein if the running CPU is a slave core, the steps of reading a slave core instruction from the master-slave core code segment and executing a control operation corresponding to the slave core instruction include:
if the running CPU is a slave core, determining a master-slave core code segment physical address corresponding to a master-slave core code segment virtual address accessed by the slave core through a second memory management unit;
and reading a slave core instruction from the master and slave core code segments corresponding to the physical addresses of the master and slave core code segments and executing the control operation corresponding to the slave core instruction.
The control method of the multi-core system shared code section, wherein the main core comprises the following steps: a first data storage unit, the slave core comprising: a second data storage unit;
after the CPU is operated, the step of judging whether the operated CPU is a master core or a slave core further comprises the following steps:
starting a first memory management unit, and mapping the physical address of the first data storage unit into a first data storage unit virtual address which is the same as the physical address of the first data storage unit;
and starting a second memory management unit, and mapping the physical address of the second data storage unit into a second data storage unit virtual address which is the same as the first data storage unit virtual address.
The control method of the multi-core system shared code section, wherein after the CPU operates, the step of judging whether the operating CPU is a master core or a slave core further comprises:
the master-slave core code segment is set to read-only.
An intelligent terminal, wherein, include: a processor, a storage medium communicatively coupled to the processor, the storage medium adapted to store a plurality of instructions; the processor is adapted to invoke instructions in the storage medium to perform steps implementing the control method of the common code segment of a multi-core system as described in any of the above.
A storage medium, wherein a control program of a control method of a multi-core system common code section is stored on the storage medium, and the control program of the control method of the multi-core system common code section realizes the steps of the control method of any one of the multi-core system common code sections when executed by a processor.
The invention has the beneficial effects that the invention provides a control method, an intelligent terminal and a storage medium of a common code segment of a multi-core system, when a CPU runs, the running CPU is judged to be a master core or a slave core; if the running CPU is a main core, reading a main core instruction from a pre-established main-slave core code section and executing a control operation corresponding to the main core instruction; and if the running CPU is a slave core, reading a slave core instruction from the master-slave core code section and executing the control operation corresponding to the slave core instruction. The method, the computer equipment and the storage medium of the invention execute the corresponding control operation in the master-slave core code section by pre-establishing the master-slave core code section for storing the master core instruction and the slave core instruction and judging whether the master core is operated or the slave core is operated when the CPU is operated, the master core and the slave core share one set of codes, the code upgrading and the maintenance are simple, the storage space (ROM) of an AMP system is saved, and the code operation space (RAM) is saved.
Drawings
FIG. 1 is a flow chart of a preferred embodiment of a method for controlling a common code segment of a multi-core system according to the present invention;
fig. 2 is a functional schematic diagram of the intelligent terminal of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more clear and clear, the present invention will be further described in detail below with reference to the accompanying drawings and examples. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the invention.
The control method of the multi-core system shared code segment provided by the invention can be applied to a terminal. The terminal may be, but is not limited to, various personal computers, notebook computers, cell phones, tablet computers, car computers, and portable wearable devices. The terminal of the invention adopts a multi-core processor. The processor of the terminal may be at least one of a central processing unit (Central Processing Unit, CPU), a graphics processor (Graphics Processing Unit, GPU), a video processing unit (Video Processing Unit, VPU), and the like.
In order to solve the problems that each CPU of the existing AMP system needs a separate code running space (RAM), the code upgrading and maintenance are complicated, and the large code running space (RAM) is occupied. The invention provides a control method for a common code segment of a multi-core system.
Referring to fig. 1, fig. 1 is a flowchart of a control method for a common code segment of a multi-core system according to a preferred embodiment of the present invention.
In a first embodiment, the control method of the common code segment of the multi-core system has four steps:
s100, when the CPU runs, judging whether the running CPU is a master core or a slave core.
In the existing AMP system, each CPU is responsible for processing single complementary coherent service, each CPU needs independent code running space (RAM), and when the system is upgraded and maintained, the code of each CPU code segment needs to be upgraded and maintained, so that the operation is complex, and the larger code running space (RAM) is occupied. Therefore, in this embodiment, a master-slave core code section for storing a master core instruction and a slave core instruction is pre-established, and when the master core and the slave core run, both the master core and the slave core can read corresponding instructions from the same master-slave core code section and execute control operations corresponding to the instructions. In this embodiment, since the master and slave core instructions are stored in the same code segment, only one code needs to be upgraded and maintained in the same code segment during system upgrade and maintenance, and the operation is simple. And because the master and slave core codes use the same set and are stored in the master and slave core code segments, the memory space (ROM) and the code running space (RAM) of the AMP system are saved.
In the embodiment, the main core instruction and the slave core instruction are stored in the same code segment, but in the actual use process, the main core instruction and the slave core instruction have differences due to the difference of functions of the main core and the slave core, so that the instruction which can only run on one core needs to distinguish which core is currently running. Therefore, in this embodiment, when it is monitored that the CPU is running, it is further required to determine whether the CPU currently running is a master core CPU or a slave core CPU, and according to the determined type of the CPU currently running, read a corresponding instruction from the master-slave core code segment and execute a corresponding operation, so that instruction reading and control operations of multiple CPUs can be implemented in one code segment by using one set of code.
In this embodiment, when the CPU runs, the step of determining whether the running CPU is a master core or a slave core specifically includes:
s101, when the CPU runs, judging whether the running CPU is a master core or a slave core according to the value of the register;
s102, when the value of the register is 0, judging that the running CPU is a main core;
s103, when the value of the register is N, judging that the running CPU is a slave core; wherein N is a number not equal to 0.
In this embodiment, before determining whether the running CPU is the master core or the slave core, a register for determining whether the running CPU is the master core or the slave core is further preset.
Specifically, when the value of the WHOAMI register is 0, the running CPU is judged to be the master core, and when the value of the WHOAMI register is N, the running CPU is judged to be the slave core, wherein N is a value not equal to 0. Taking a dual-core CPU as an example, it may be set that the running CPU is judged to be a master core when the value of the WHOAMI register is 0, and the running CPU is judged to be a slave core when the value of the WHOAMI register is 1. And so on, when the CPU is three cores, it may be set that the running CPU is judged to be the master core when the value of the WHOAMI register is 0, the running CPU is judged to be the first slave core when the value of the WHOAMI register is 1, and the running CPU is judged to be the second slave core when the value of the WHOAMI register is 2. Of course, the present invention is equally applicable to AMP systems of more cores than 2 cores and 3 cores, and will not be described in detail herein.
Further, in this embodiment, the determination of the current running CPU as the master core or the slave core through the WHOAMI register may be implemented by the following manner:
if(0＝＝WHOAMI)
{
a main core processing flow;
}
else
{
a slave core processing flow;
}。
in this embodiment, after the CPU is running, the step of determining whether the running CPU is a master core or a slave core further includes:
s1, starting a first memory management unit, and mapping the physical address of the master-slave core code segment into a master-slave core code segment virtual address which is the same as the physical address of the master-slave core code segment; mapping the physical address of the first data storage unit into a first data storage unit virtual address identical to the first data storage unit physical address;
s2, starting a second memory management unit, and mapping the physical address of the master-slave core code segment into a master-slave core code segment virtual address which is the same as the physical address of the master-slave core code segment; the physical address of the second data storage unit is mapped to a second data storage unit virtual address that is the same as the first data storage unit virtual address.
In particular, those skilled in the art understand that, in the present AMP system, in addition to a code segment for storing instructions, a data storage unit for storing CPU data and variables is further provided, and in this embodiment, in order to implement a code segment shared by a master core and a slave core, and implement independent division of the data storage units of the master core and the slave core without interference, the code segments of the master core and the slave core are set to be the same code segment of the master core and the code segment of the slave core, and the data storage units of the master core and the data storage units of the slave core are separately set. Taking the AMP system of 2 cores as an example, the master core includes a first data storage unit and the slave core includes a second data storage unit. The master core may access the master-slave core code segment and the first data storage unit, and the slave core may access the master-slave core code segment and the second data storage unit. For example, for a dual-core AMP system with a 1GB double-speed synchronous dynamic random memory, a master-slave core code segment is set to be in a space of 0-64M, a first data storage unit is set to be in a space of 64-512M, a second data storage unit is set to be in a space of 512-960M, namely, a master core can access the master-slave core code segment of 0-64M and the first data storage unit of 64-512M, and a slave core can access the master-slave core code segment of 0-64M and the second data storage unit of 512-960M.
As can be seen from the above steps, the master and slave cores share the code segment, and the master and slave cores data storage units are independent from each other. Thus resulting in a discontinuity in the memory space that can be accessed by the master or slave. For example, in the foregoing steps, it is mentioned that for a dual core AMP system with a 1GB dual speed synchronous dynamic random access memory size, the master core can access 0-512M of memory space, while the slave core can access 0-64M of memory space and 512-960M of memory space, it is apparent that the memory space accessible by the slave core is discontinuous.
In practice, it will be appreciated by those skilled in the art that information is stored in units of bytes in memory, and that each byte unit is assigned a unique memory address, referred to as a physical address, in order to properly store or retrieve information. The master-slave core code segment for storing instructions and storing data and the first data storage unit and the second data storage unit in this embodiment each correspond to a respective physical address, which is represented using a binary number, for example: 0x0000-0000 to 0x0400-0000. In this embodiment, because the physical addresses that the master core or the slave core can access are discontinuous, the physical addresses of the master core code segment, the physical addresses of the first storage unit and the physical addresses of the second storage unit are further mapped into corresponding virtual addresses, so as to solve the problem that the physical addresses that the master core or the slave core can access are discontinuous.
Specifically, the master core and the slave core of the present embodiment are respectively provided with a Memory Management Unit (MMU), and the Memory Management Unit (MMU) may be used to manage the virtual memory, the control line of the physical memory, and also be responsible for mapping the virtual address to the physical address, and providing memory access authorization of the hardware mechanism, multi-task and multi-process operation, and so on. In this embodiment, a 2-core AMP system is illustrated, where a primary core is provided with a first memory management unit, and a secondary core is provided with a second memory management unit. When the physical addresses which can be accessed by the master core are continuous and the physical addresses which can be accessed by the slave core are discontinuous, the master core starts a first memory management unit, maps the physical addresses of the master core code segments and the slave core code segments to master core code segment virtual addresses which are the same as the physical addresses of the master core code segments and the slave core code segments, and maps the physical addresses of the first data storage units to first data storage unit virtual addresses which are the same as the physical addresses of the first data storage units; the slave core starts a second memory management unit, maps the physical address of the master-slave core code segment to the same master-slave core code segment virtual address as the master-slave core code segment physical address, and maps the physical address of the second data storage unit to the same second data storage unit virtual address as the first data storage unit virtual address. For example, still taking a dual-core AMP system with a 1GB dual-speed synchronous dynamic random access memory as an example, a master core may access a 0-512M memory space, and a slave core may access a 0-64M memory space and a 512-960M memory space, since 0-64M is a master-slave core code segment that can be accessed by the master-slave core at the same time, in this embodiment, the physical address of 0-512M that can be accessed by the master core is directly mapped to the virtual address of 0-512M, the physical address of 0-64M that can be accessed by the slave core is directly mapped to the virtual address of 0-64M, and the physical address of 512-960M that can be accessed by the slave core is mapped to the virtual address of 64-512M, so that the physical address that can be accessed by the slave core is discontinuous, but the virtual addresses that can be accessed by the slave core are continuous. And so on, when the physical addresses of the master core are discontinuous and the physical addresses of the slave cores are continuous, the method can be used for mapping the physical addresses of the master core and the slave core to virtual addresses with continuous ranges, and the description is omitted. Table 1 below is a comparison table of master-slave core physical addresses and virtual addresses:
TABLE 1
As can be seen from table 1, although the physical addresses accessible to the slave core are discontinuous, the virtual address space accessible to the slave core is configured by the Memory Management Unit (MMU) to be identical to the virtual address space accessible to the master core, so that the virtual address view accessible to the master and slave cores is identical.
Further, in the embodiment, the master and slave core code segments are set to be read only and not rewritable, so that the safety of code operation is ensured. Specifically, in this embodiment, the mapping between the master-slave core code setting and the physical address and the virtual address is performed by a plurality of registers MAS0, MAS1, MAS2, MAS3, MAS7 in the AMP system:
continuing back to FIG. 1, the control method of the common code segment of the multi-core system further includes the steps of:
s200, if the running CPU is a main core, reading a main core instruction from a pre-established main-slave core code section and executing a control operation corresponding to the main core instruction;
s300, if the running CPU is a slave core, reading a slave core instruction from the master-slave core code segment and executing control operation corresponding to the slave core instruction.
In the embodiment, after judging whether the currently running CPU is the master core or the slave core according to the value of the processor identification register, further reading the instruction corresponding to the currently running CPU in the master-slave core code segment and executing the control operation corresponding to the instruction. For example, if the currently running CPU is judged to be the main core by the value of the processor identification register, reading a main core instruction from the main core code section and executing a control operation corresponding to the main core instruction; and otherwise, reading the slave core instruction from the master-slave core code segment and executing the control operation corresponding to the slave core instruction.
In this embodiment, if the running CPU is a master core, the steps of reading a master core instruction from a pre-established master-slave core code segment and executing a control operation corresponding to the master core instruction specifically include:
s201, if the running CPU is a main core, determining a physical address of a main core code segment corresponding to a virtual address of a main core code segment accessed by the main core through a first memory management unit;
s202, reading a main core instruction from a main core code segment corresponding to the physical address of the main core code segment and executing control operation corresponding to the main core instruction.
In the implementation, if the running CPU is a main core, the main core starts a first memory management unit, a virtual address of a main core code segment sent by the main core is intercepted by the first memory management unit, the first memory management unit translates the virtual address into a corresponding main core code segment physical address and sends the corresponding main core code segment physical address to an external address pin of the main core chip, so that a main core instruction in the main core code segment is read and a control operation corresponding to the main core instruction is executed. Of course, the virtual address sent by the main core in this embodiment may also be a virtual address of the first data storage unit, where the virtual address of the first data storage unit is intercepted by the first memory management unit, and the first memory management unit translates the virtual address into a corresponding physical address of the first data storage unit and sends the physical address of the first data storage unit to an external address pin of the main core chip, so as to store data or variables and the like.
In this embodiment, if the running CPU is a master core, the steps of reading a master core instruction from the master-slave core code segment and executing a control operation corresponding to the master core instruction specifically include:
s301, if the running CPU is a slave core, determining a master-slave core code segment physical address corresponding to a master-slave core code segment virtual address accessed by the slave core through a second memory management unit;
s302, reading a slave core instruction from a master core code segment corresponding to the master core code segment physical address and executing control operation corresponding to the slave core instruction.
In the implementation, if the running CPU is a slave core, the slave core starts a second memory management unit, a virtual address of a master-slave core code segment sent by the slave core is intercepted by the second memory management unit, the second memory management unit translates the virtual address into a corresponding master-slave core code segment physical address and sends the corresponding master-slave core code segment physical address to an external address pin of the slave core chip, and therefore a master core instruction in the master-slave core code segment is read and control operation corresponding to the slave core instruction is executed. Of course, in this embodiment, the virtual address of the second data storage unit may also be sent by the master core, where the virtual address of the second data storage unit is intercepted by the second memory management unit, and the second memory management unit translates the virtual address into a corresponding physical address of the second data storage unit and sends the physical address of the second data storage unit to an external address pin of the slave core chip, so as to store data or variables and so on.
Based on the above embodiment, the present invention further provides an intelligent terminal, and a functional block diagram thereof may be shown in fig. 2. The intelligent terminal comprises a processor, a memory, a network interface, a display screen and a temperature sensor which are connected through a system bus. The processor of the intelligent terminal is used for providing computing and control capabilities. The memory of the intelligent terminal comprises a nonvolatile storage medium and an internal memory. The non-volatile storage medium stores an operating system and a computer program. The internal memory provides an environment for the operation of the operating system and computer programs in the non-volatile storage media. The network interface of the intelligent terminal is used for communicating with an external terminal through network connection. The computer program, when executed by a processor, implements a method of controlling a common code segment of a multi-core system. The display screen of the intelligent terminal can be a liquid crystal display screen or an electronic ink display screen, and a temperature sensor of the intelligent terminal is arranged in the intelligent terminal in advance and used for detecting the current running temperature of internal equipment.
It will be appreciated by those skilled in the art that the schematic block diagram shown in fig. 2 is merely a block diagram of a portion of the structure associated with the present inventive arrangements and is not limiting of the intelligent terminal to which the system described in the present inventive arrangements is applied, and that a particular intelligent terminal may include more or fewer components than shown, or may combine certain components, or may have a different arrangement of components.
In one embodiment, there is provided an intelligent terminal including a memory and a processor, the memory storing a computer program, the processor executing the computer program to perform at least the following steps:
when the CPU runs, judging whether the running CPU is a master core or a slave core;
if the running CPU is a main core, reading a main core instruction from a pre-established main-slave core code section and executing a control operation corresponding to the main core instruction;
and if the running CPU is a slave core, reading a slave core instruction from the master-slave core code section and executing the control operation corresponding to the slave core instruction.
In one embodiment, the processor, when executing the computer program, may further implement: registers for judging whether the running CPU is a master core or a slave core are set in advance.
In one embodiment, the processor, when executing the computer program, may further implement: when the CPU runs, judging whether the running CPU is a master core or a slave core according to the value of the register; when the value of the register is 0, judging that the running CPU is a main core; when the value of the register is N, judging that the running CPU is a slave core; wherein N is a number not equal to 0.
In one embodiment, the processor, when executing the computer program, may further implement: starting a first memory management unit, and mapping the physical address of the master and slave core code segments into a master and slave core code segment virtual address which is the same as the physical address of the master and slave core code segments; and starting a second memory management unit, and mapping the physical address of the master-slave core code segment into a master-slave core code segment virtual address which is the same as the physical address of the master-slave core code segment.
In one embodiment, the processor, when executing the computer program, may further implement: if the running CPU is a main core, determining a physical address of a main core code segment corresponding to a virtual address of a main core code segment accessed by the main core through a first memory management unit; and reading a main core instruction from the main core code segment and the slave core code segment corresponding to the physical address of the main core code segment and executing the control operation corresponding to the main core instruction.
In one embodiment, the processor, when executing the computer program, may further implement: if the running CPU is a slave core, determining a master-slave core code segment physical address corresponding to a master-slave core code segment virtual address accessed by the slave core through a second memory management unit; and reading a slave core instruction from the master and slave core code segments corresponding to the physical addresses of the master and slave core code segments and executing the control operation corresponding to the slave core instruction.
In one embodiment, the processor, when executing the computer program, may further implement: starting a first memory management unit, and mapping the physical address of the first data storage unit into a first data storage unit virtual address which is the same as the physical address of the first data storage unit; and starting a second memory management unit, and mapping the physical address of the second data storage unit into a second data storage unit virtual address which is the same as the first data storage unit virtual address.
In one embodiment, the processor, when executing the computer program, may further implement: the master-slave core code segment is set to read-only.
Those skilled in the art will appreciate that implementing all or part of the above described methods may be accomplished by way of a computer program stored on a non-transitory computer readable storage medium, which when executed, may comprise the steps of the embodiments of the methods described above. Any reference to memory, storage, database, or other medium used in embodiments provided herein may include non-volatile and/or volatile memory. The nonvolatile memory can include Read Only Memory (ROM), programmable ROM (PROM), electrically Programmable ROM (EPROM), electrically Erasable Programmable ROM (EEPROM), or flash memory. Volatile memory can include Random Access Memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in a variety of forms such as Static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double Data Rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous Link DRAM (SLDRAM), memory bus direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM), among others.
In summary, the present invention provides a control method, an intelligent terminal and a storage medium for a common code segment of a multi-core system, where the method includes: when the CPU runs, judging whether the running CPU is a master core or a slave core; if the running CPU is a main core, reading a main core instruction from a pre-established main-slave core code section and executing a control operation corresponding to the main core instruction; and if the running CPU is a slave core, reading a slave core instruction from the master-slave core code section and executing the control operation corresponding to the slave core instruction. The invention establishes the master-slave core code section for storing the master core instruction and the slave core instruction in advance, when the CPU runs, the corresponding control operation in the master-slave core code section is executed by judging whether the master core runs or the slave core runs, the master core and the slave core share one set of codes, the code upgrading and the maintenance are simple, the storage space (ROM) of an AMP system is saved, and the code running space (RAM) is saved.
It is to be understood that the system application of the present invention is not limited to the examples described above, and that modifications and variations may be made by those skilled in the art in light of the above teachings, all of which are intended to be within the scope of the invention as defined in the appended claims.

Claims (6)

1. The control method of the common code segment of the multi-core system is characterized by comprising the following steps:
when the CPU runs, judging whether the running CPU is a master core or a slave core;
if the running CPU is a main core, reading a main core instruction from a pre-established main-slave core code section and executing a control operation corresponding to the main core instruction; the master core code segment and the slave core code segment are respectively used for storing a master core instruction and a slave core instruction;
if the running CPU is a slave core, reading a slave core instruction from the master-slave core code section and executing a control operation corresponding to the slave core instruction;
the code segments of the master core and the slave core are identical master-slave core code segments, and the data storage units of the master core and the slave core are independently divided;
the main core includes: the first memory management unit, the slave core includes: a second memory management unit;
after the CPU is operated, the step of judging whether the operated CPU is a master core or a slave core further comprises the following steps:
starting a first memory management unit, and mapping the physical address of the master and slave core code segments into a master and slave core code segment virtual address which is the same as the physical address of the master and slave core code segments;
starting a second memory management unit, and mapping the physical address of the master-slave core code segment into a master-slave core code segment virtual address which is the same as the physical address of the master-slave core code segment;
the main core includes: a first data storage unit, the slave core comprising: a second data storage unit;
after the CPU is operated, the step of judging whether the operated CPU is a master core or a slave core further comprises the following steps:
starting a first memory management unit, and mapping the physical address of the first data storage unit into a first data storage unit virtual address which is the same as the physical address of the first data storage unit;
starting a second memory management unit, and mapping the physical address of the second data storage unit into a second data storage unit virtual address which is the same as the first data storage unit virtual address;
the first memory management unit and the second memory management unit are used for managing a virtual memory, managing a control line of a physical memory, mapping a virtual address into a physical address, providing memory access authorization of a hardware mechanism and providing multi-task and multi-process operation;
if the running CPU is a main core, the steps of reading a main core instruction from the pre-established main core code segment and executing the control operation corresponding to the main core instruction comprise the following steps:
if the running CPU is a main core, determining a physical address of a main core code segment corresponding to a virtual address of a main core code segment accessed by the main core through a first memory management unit;
reading a main core instruction from a main core code segment and a slave core code segment corresponding to the physical address of the main core code segment and executing control operation corresponding to the main core instruction;
and if the running CPU is a slave core, the steps of reading a slave core instruction from the master-slave core code segment and executing the control operation corresponding to the slave core instruction comprise the following steps of:
if the running CPU is a slave core, determining a master-slave core code segment physical address corresponding to a master-slave core code segment virtual address accessed by the slave core through a second memory management unit;
and reading a slave core instruction from the master and slave core code segments corresponding to the physical addresses of the master and slave core code segments and executing the control operation corresponding to the slave core instruction.
2. The method for controlling a common code segment of a multi-core system according to claim 1, wherein the step of determining whether the running CPU is a master core or a slave core further comprises, when the CPU is running:
registers for judging whether the running CPU is a master core or a slave core are set in advance.
3. The method according to claim 2, wherein the step of determining whether the running CPU is a master core or a slave core when the CPU is running comprises:
when the CPU runs, judging whether the running CPU is a master core or a slave core according to the value of the register;
when the value of the register is 0, judging that the running CPU is a main core;
when the value of the register is N, judging that the running CPU is a slave core; wherein N is a number not equal to 0.
4. The method for controlling a common code segment of a multi-core system according to claim 1, wherein after the CPU is operated, the step of determining whether the operated CPU is a master core or a slave core further comprises:
the master-slave core code segment is set to read-only.
5. An intelligent terminal, characterized by comprising: a processor, a storage medium communicatively coupled to the processor, the storage medium adapted to store a plurality of instructions; the processor is adapted to invoke instructions in the storage medium to perform the steps of a control method implementing the common code segment of a multi-core system as claimed in any of the preceding claims 1-4.
6. A storage medium, wherein a control program of a control method of a multi-core system common code section is stored on the storage medium, and the control program of the control method of the multi-core system common code section realizes the steps of the control method of the multi-core system common code section according to any one of claims 1 to 4 when executed by a processor.
CN201910683995.9A 2019-07-26 2019-07-26 Control method for common code segment of multi-core system, intelligent terminal and storage medium Active CN110569066B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201910683995.9A CN110569066B (en) 2019-07-26 2019-07-26 Control method for common code segment of multi-core system, intelligent terminal and storage medium

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201910683995.9A CN110569066B (en) 2019-07-26 2019-07-26 Control method for common code segment of multi-core system, intelligent terminal and storage medium

Publications (2)

Publication Number Publication Date
CN110569066A CN110569066A (en) 2019-12-13
CN110569066B true CN110569066B (en) 2023-08-01

Family

ID=68773851

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201910683995.9A Active CN110569066B (en) 2019-07-26 2019-07-26 Control method for common code segment of multi-core system, intelligent terminal and storage medium

Country Status (1)

Country Link
CN (1) CN110569066B (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111427817B (en) * 2020-03-23 2021-09-24 深圳震有科技股份有限公司 Method for sharing I2C interface by dual cores of AMP system, storage medium and intelligent terminal
CN111475213B (en) * 2020-04-03 2023-04-28 深圳忆联信息系统有限公司 Power consumption reduction method and device for solid state disk with multi-core structure and computer equipment
CN113778936A (en) * 2021-08-17 2021-12-10 华东计算技术研究所（中国电子科技集团公司第三十二研究所） Performance optimization method of domestic embedded DSP operating system

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100583049C (en) * 2007-11-29 2010-01-20 上海华为技术有限公司 Multi-nucleus processor sharing code segment patching method and apparatus
CN101799750B (en) * 2009-02-11 2015-05-06 上海芯豪微电子有限公司 Data processing method and device
US9311011B2 (en) * 2013-08-07 2016-04-12 Qualcomm Incorporated Dynamic address negotiation for shared memory regions in heterogenous multiprocessor systems
CN106407156B (en) * 2016-09-23 2018-11-23 深圳震有科技股份有限公司 The method and system of one BOOTROM guidance multi-core CPU starting

Also Published As

Publication number Publication date
CN110569066A (en) 2019-12-13

Similar Documents

Publication Publication Date Title
CN110569066B (en) Control method for common code segment of multi-core system, intelligent terminal and storage medium
US4296466A (en) Data processing system including a separate input/output processor with micro-interrupt request apparatus
US10860332B2 (en) Multicore framework for use in pre-boot environment of a system-on-chip
JP5348429B2 (en) Cache coherence protocol for persistent memory
JP3136257B2 (en) Computer memory interface device
CN103782282B (en) There is the computer system of the treater locally coherence for virtualization I/O
US8255591B2 (en) Method and system for managing cache injection in a multiprocessor system
EP2307964B1 (en) Avoidance of self eviction caused by dynamic memory allocation in a flash memory storage device
US9552303B2 (en) Method and system for maintaining release consistency in shared memory programming
CN104866443A (en) Interruptible store exclusive
EP3335124A1 (en) Register files for i/o packet compression
US20090216974A1 (en) Microcomputer
JPWO2010097925A1 (en) Information processing device
CN111625546A (en) Data writing method, device, equipment and medium
US9372795B2 (en) Apparatus and method for maintaining cache coherency, and multiprocessor apparatus using the method
EP3872629B1 (en) Method and apparatus for executing instructions, device, and computer readable storage medium
KR20210093531A (en) System including a storage device for providing data to an application processor
EP1103898A2 (en) Microprocessor and memory
CN112654965A (en) External paging and swapping of dynamic modules
WO2011002371A1 (en) A programmable controller
TWI760756B (en) A system operative to share code and a method for code sharing
US6981122B2 (en) Method and system for providing a contiguous memory address space
US7386890B2 (en) Method and apparatus to preserve a hash value of an executable module
CN112506666A (en) GPU time-sharing method and system based on drive packaging
CN104969203A (en) Implementing coherency with reflective memory

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant