CN110569066A - Control method of multi-core system shared code segment, intelligent terminal and storage medium - Google Patents
Control method of multi-core system shared code segment, intelligent terminal and storage medium Download PDFInfo
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Abstract
The invention provides a control method for a multi-core system shared code segment, an intelligent terminal and a storage medium, wherein the method comprises the following steps: when the CPU runs, judging whether the running CPU is a main core or a slave core; if the running CPU is a main core, reading a main core instruction from a pre-established main core and auxiliary core code segment and executing a control operation corresponding to the main core instruction; and if the running CPU is a slave core, reading a slave core instruction from the master-slave core code section and executing the control operation corresponding to the slave core instruction. The invention establishes the master-slave core code section for storing the master core instruction and the slave core instruction in advance, executes the corresponding control operation in the master-slave core code section by judging whether the master core runs or the slave core runs when the CPU runs, and the master-slave core and the slave core share one set of codes, thereby the code upgrading and maintenance are simple, the storage space of the AMP system is saved, and the code running space is saved.
Description
Technical Field
The invention relates to the technical field of embedded systems, in particular to a control method of a multi-core system shared code segment, an intelligent terminal and a storage medium.
Background
The field of embedded systems, applications for multiple cores are classified into symmetric Multi-Processing (SMP) and Asymmetric Multi-Processing (AMP), which are adapted to various applications. Despite their great differences, multiple cores within a processor are started to execute their respective instructions and work together.
All cores of the conventional SMP system are scheduled and managed by an operating system, each process is switched among a plurality of cores during operation, the performance of the system is lost, and the performance of an N-core CPU cannot be equal to the performance N of 1 single-core CPU. And each CPU in the AMP system is responsible for processing single complementary coherent traffic, and the whole N-core CPU performance can approach one single-core CPU performance N. However, each CPU of the AMP system needs a separate code operating space (RAM), and when the system is upgraded and maintained, the code of each CPU code segment needs to be upgraded and maintained, which is cumbersome to operate and occupies a large code operating space (RAM).
Therefore, the prior art is subject to further improvement.
Disclosure of Invention
in view of the above disadvantages in the prior art, an object of the present invention is to provide a control method for a shared code segment of a multi-core system, an intelligent terminal and a storage medium, which overcome the defects that each CPU of an AMP system in the prior art needs an independent code running space (RAM), the code upgrade and maintenance are complicated, and a large code running space (RAM) is occupied.
the first embodiment disclosed by the invention is a control method for a multi-core system to share a code segment, wherein the method comprises the following steps:
The method for controlling the shared code segment of the multi-core system is characterized by comprising the following steps:
When the CPU runs, judging whether the running CPU is a main core or a slave core;
if the running CPU is a main core, reading a main core instruction from a pre-established main core and auxiliary core code segment and executing a control operation corresponding to the main core instruction; the master-slave core code segment stores a master core instruction and a slave core instruction;
and if the running CPU is a slave core, reading a slave core instruction from the master-slave core code section and executing the control operation corresponding to the slave core instruction.
the method for controlling a shared code segment of a multi-core system comprises the following steps of judging whether a running CPU is a main core or a slave core when the CPU runs:
a register for determining whether the running CPU is a master core or a slave core is set in advance.
The method for controlling the multi-core system to share the code segment, wherein when the CPU runs, the step of judging whether the running CPU is a main core or a slave core comprises the following steps:
When the CPU runs, judging whether the running CPU is a main core or a slave core according to the value of the register;
when the value of the register is 0, judging that the running CPU is a main core;
when the value of the register is N, judging that the running CPU is a slave core; wherein N is a number not equal to 0.
The method for controlling a multi-core system shared code segment, wherein the main core comprises: a first memory management unit, the slave core comprising: a second memory management unit;
After the CPU is operated, the step of judging whether the operated CPU is a main core or a slave core further comprises the following steps:
starting a first memory management unit, and mapping the physical address of the master-slave core code segment into a master-slave core code segment virtual address which is the same as the physical address of the master-slave core code segment;
and starting a second memory management unit, and mapping the physical address of the master-slave core code segment into a master-slave core code segment virtual address which is the same as the physical address of the master-slave core code segment.
the control method for the multi-core system shared code segment is characterized in that if the running CPU is a main core, the steps of reading a main core instruction from the pre-established main core and auxiliary core code segment and executing the control operation corresponding to the main core instruction comprise the following steps:
If the running CPU is a main core, determining a physical address of a main core code segment and a subordinate core code segment corresponding to a virtual address of the main core code segment and the subordinate core code segment accessed by the main core through a first memory management unit;
And reading a main core instruction from the main and slave core code sections corresponding to the physical addresses of the main and slave core code sections and executing the control operation corresponding to the main core instruction.
the method for controlling a multi-core system shared code segment, wherein if the running CPU is a slave core, the step of reading a slave core instruction from the master and slave core code segments and executing the control operation corresponding to the slave core instruction comprises the following steps:
If the running CPU is the slave core, determining the physical address of the master-slave core code segment corresponding to the virtual address of the master-slave core code segment accessed by the slave core through a second memory management unit;
and reading a slave core instruction from the master-slave core code section corresponding to the physical address of the master-slave core code section and executing the control operation corresponding to the slave core instruction.
The method for controlling a multi-core system shared code segment, wherein the main core comprises: a first data storage unit, the slave core comprising: a second data storage unit;
after the CPU is operated, the step of judging whether the operated CPU is a main core or a slave core further comprises the following steps:
Starting a first memory management unit, and mapping the physical address of the first data storage unit into a first data storage unit virtual address which is the same as the physical address of the first data storage unit;
And starting a second memory management unit, and mapping the physical address of the second data storage unit into a virtual address of the second data storage unit which is the same as the virtual address of the first data storage unit.
The method for controlling the multi-core system to share the code segment, wherein after the CPU is operated, the step of judging whether the operated CPU is a main core or a slave core further comprises the following steps:
Setting the master and slave core code segments to be read-only.
An intelligent terminal, comprising: a processor, a storage medium communicatively coupled to the processor, the storage medium adapted to store a plurality of instructions; the processor is suitable for calling instructions in the storage medium to execute the steps of the control method for realizing the multi-core system common code segment.
A storage medium, wherein a control program of a control method of a multi-core system sharing code segment is stored on the storage medium, and when executed by a processor, the control program of the control method of the multi-core system sharing code segment implements any one of the steps of the control method of the multi-core system sharing code segment.
the method has the advantages that the invention provides a control method of a multi-core system shared code segment, an intelligent terminal and a storage medium, when a CPU runs, whether the running CPU is a master core or a slave core is judged; if the running CPU is a main core, reading a main core instruction from a pre-established main core and auxiliary core code segment and executing a control operation corresponding to the main core instruction; and if the running CPU is a slave core, reading a slave core instruction from the master-slave core code section and executing the control operation corresponding to the slave core instruction. According to the method, the computer equipment and the storage medium, the master and slave core code sections for storing the master core instruction and the slave core instruction are established in advance, when the CPU runs, corresponding control operation in the master and slave core code sections is executed by judging whether the master core runs or the slave core runs, the master and slave cores share one set of codes, the code upgrading and maintenance are simple, the storage space (ROM) of an AMP system is saved, and meanwhile, the code running space (RAM) is saved.
drawings
FIG. 1 is a flowchart illustrating a method for controlling a shared code segment in a multi-core system according to an embodiment of the present invention;
Fig. 2 is a functional schematic diagram of the intelligent terminal of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention clearer and clearer, the present invention is further described in detail below with reference to the accompanying drawings and examples. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
the control method of the multi-core system shared code segment provided by the invention can be applied to a terminal. The terminal may be, but is not limited to, various personal computers, notebook computers, mobile phones, tablet computers, vehicle-mounted computers, and portable wearable devices. The terminal of the invention adopts a multi-core processor. The processor of the terminal may be at least one of a Central Processing Unit (CPU), a Graphics Processing Unit (GPU), a Video Processing Unit (VPU), and the like.
The method aims to solve the problems that each CPU of the existing AMP system needs an independent code operating space (RAM), the code upgrading and maintenance are tedious, and a large code operating space (RAM) is occupied. The invention provides a control method for sharing code segments of a multi-core system.
Referring to fig. 1, fig. 1 is a flowchart illustrating a method for controlling a shared code segment of a multi-core system according to an embodiment of the present invention.
in a first embodiment, the method for controlling a shared code segment of a multi-core system includes four steps:
s100, when the CPU runs, judging whether the running CPU is a main core or a slave core.
Each CPU in the existing AMP system is responsible for processing a single complementary coherent service, each CPU needs an independent code operating space (RAM), and when the system is upgraded and maintained, the code of each CPU code segment needs to be upgraded and maintained, which is cumbersome to operate and occupies a large code operating space (RAM). Therefore, in this embodiment, a master-slave core code segment for storing a master core instruction and a slave core instruction is pre-established, and both the master core and the slave core can read a corresponding instruction from the same master-slave core code segment and execute a control operation corresponding to the instruction when running. In the embodiment, because the main core instruction and the auxiliary core instruction are stored in the same code segment, only one code needs to be upgraded and maintained in the same code segment during system upgrading and maintenance, and the operation is simple. And because the master-slave core codes use the same set and are stored in the master-slave core code sections, the storage space (ROM) and the code running space (RAM) of the AMP system are saved.
in the actual use process, the main core instruction and the slave core instruction have differences due to the difference in functions between the main core and the slave core, and the instruction that can only run on one core needs to distinguish which core is currently running. Therefore, in this embodiment, when it is monitored that the CPU is running, it is further necessary to determine whether the currently running CPU is a master core CPU or a slave core CPU, and read a corresponding instruction from the master and slave core code segments and execute a corresponding operation according to the determined type of the currently running CPU, so that instruction reading and control operations of a plurality of CPUs can be implemented in one code segment by using one set of codes.
In this embodiment, the step of determining whether the running CPU is the master core or the slave core when the CPU runs specifically includes:
S101, when the CPU runs, judging whether the running CPU is a main core or a slave core according to the value of the register;
S102, when the value of the register is 0, judging that the running CPU is a main core;
s103, when the value of the register is N, judging that the running CPU is a slave core; wherein N is a number not equal to 0.
in specific implementation, before determining whether the running CPU is the master core or the slave core, a register for determining whether the running CPU is the master core or the slave core is further preset in this embodiment, preferably, the register in this embodiment is a WHOAMI register, and when the CPU runs, whether the currently running CPU is the master core or the slave core is determined according to a value of the WHOAMI register.
specifically, when the value of the WHOAMI register is 0, it is determined that the operating CPU is the master core, and when the value of the WHOAMI register is N, it is determined that the operating CPU is the slave core, where N is a numerical value not equal to 0. Taking a dual-core CPU as an example, it may be set that when the value of the WHOAMI register is 0, the running CPU is determined to be the master core, and when the value of the WHOAMI register is 1, the running CPU is determined to be the slave core. By analogy, when the CPU is a triple core, it may be set that the running CPU is determined to be the master core when the value of the WHOAMI register is 0, the running CPU is determined to be the first slave core when the value of the WHOAMI register is 1, and the running CPU is determined to be the second slave core when the value of the WHOAMI register is 2. Of course, the present invention is also applicable to AMP systems with more cores besides 2 cores and 3 cores, and will not be described herein.
Further, in this embodiment, the determination of whether the currently running CPU is the master core or the slave core by the WHOAMI register may be implemented in the following manner:
if(0＝＝WHOAMI)
{
A main core processing flow;
}
else
{
a slave core processing flow;
}。
In this embodiment, after the CPU runs, before the step of determining whether the running CPU is a master core or a slave core, the method further includes:
S1, starting a first memory management unit, and mapping the physical address of the master-slave core code segment into a master-slave core code segment virtual address which is the same as the physical address of the master-slave core code segment; mapping a physical address of the first data storage unit to a first data storage unit virtual address that is the same as the first data storage unit physical address;
s2, starting a second memory management unit, and mapping the physical address of the master-slave core code segment into a master-slave core code segment virtual address which is the same as the physical address of the master-slave core code segment; mapping the physical address of the second data storage unit to a second data storage unit virtual address that is the same as the first data storage unit virtual address.
In specific implementation, as is known to those skilled in the art, in addition to the code segments for storing instructions, the existing AMP system is further provided with a data storage unit for storing CPU data and variables, in this embodiment, in order to implement that the master core and the slave core share the code segments and that the independent partitions of the data storage units of the master core and the slave core are not interfered with each other, the code segments of the master core and the slave core are set as the same master-slave core code segment, and the data storage units of the master core and the slave core are set separately. Taking the 2-core AMP system as an example, the master core includes a first data storage unit, and the slave core includes a second data storage unit. The master core may access the master-slave core code section and the first data storage unit, and the slave core may access the master-slave core code section and the second data storage unit. For example, for a dual-core AMP system with a double-speed Synchronous Dynamic Random Access Memory (SDRAM) size of 1GB, a master-slave core code segment is set to be 0-64M in space, a first data storage unit is set to be 64-512M in space, and a second data storage unit is set to be 512-960M, namely, the master core can access the master-slave core code segment of 0-64M and the first data storage unit of 64-512M, and the slave core can access the master-slave core code segment of 0-64M and the second data storage unit of 512-960M.
according to the steps, the code segments are shared by the master core and the slave core, and the data storage units of the master core and the slave core are independent. Thus causing the memory space accessible to either the master or slave to be discontinuous. For example, in the foregoing steps, for a dual-core AMP system with a double-speed synchronous dynamic random access memory size of 1GB, the master core can access 0-512M of memory space, while the slave core can access 0-64M of memory space and 512-960M of memory space, and obviously, the memory space accessible by the slave core is discontinuous.
in one implementation, as will be appreciated by those skilled in the art, information is stored in units of bytes in memory, and to properly store or retrieve information, each byte unit is assigned a unique memory address, referred to as a physical address. The master and slave core code segments for storing instructions and storing data and the first and second data storage units in this embodiment each have a respective physical address, which is represented by a binary number, for example: 0x0000-0000 to 0x 0400-0000. In this embodiment, because the physical addresses accessible by the master core or the slave core are not consecutive, in this embodiment, the physical addresses of the master and slave core code segments, the physical address of the first storage unit, and the physical address of the second storage unit are further mapped to corresponding virtual addresses, so as to solve the problem that the physical addresses accessible by the master core or the slave core are not consecutive.
specifically, the master core and the slave core of this embodiment are respectively provided with a Memory Management Unit (MMU), and the Memory Management Unit (MMU) may be configured to manage control lines of the virtual memory and the physical memory, and is also responsible for mapping the virtual address to the physical address, and providing hardware mechanism memory access authorization, multitask and multiprocess operation, and the like. In this embodiment, a 2-core AMP system is described, in which a first memory management unit is disposed on a master core, and a second memory management unit is disposed on a slave core. When the physical addresses accessible by the master core are continuous and the physical addresses accessible by the slave core are discontinuous, the master core starts the first memory management unit, maps the physical addresses of the master and slave core code sections into master and slave core code section virtual addresses the same as the physical addresses of the master and slave core code sections, and maps the physical address of the first data storage unit into a first data storage unit virtual address the same as the physical address of the first data storage unit; and the slave core starts a second memory management unit, maps the physical address of the master-slave core code segment into the virtual address of the master-slave core code segment, which is the same as the physical address of the master-slave core code segment, and maps the physical address of the second data storage unit into the virtual address of the second data storage unit, which is the same as the virtual address of the first data storage unit. For example, still taking a dual-core AMP system with a 1 GB-size synchronous dynamic random access memory as an example, the master core can access 0 to 512M of memory space, the slave core can access 0 to 64M of memory space and 512 to 960M of memory space, since 0 to 64M is a master-slave core code segment that the master-slave core can access simultaneously, in this embodiment, the physical address of 0 to 512M that the master core can access is directly mapped to the virtual address of 0 to 512M, the physical address of 0 to 64M that the slave core can access is directly mapped to the virtual address of 0 to 64M, and the physical address of 512 to 960M that the slave core can access is mapped to the virtual address of 64 to 512M, so that the physical address that the slave core can access is not continuous, but the virtual addresses that the slave core can access are continuous. In this way, when the physical addresses of the master core are not continuous and the physical addresses of the slave cores are continuous, the virtual addresses with continuous mapping ranges of the physical addresses of the master core and the slave cores can also be mapped by the method, which is not described herein again. The following table 1 is a comparison table of physical addresses and virtual addresses of the master core and the slave core:
TABLE 1
as can be seen from table 1, although the physical addresses accessible by the slave core are not consecutive, the virtual address space accessible by the slave core is configured to be the same as the virtual address space accessible by the master core through a Memory Management Unit (MMU), so that the virtual address views accessible by the master and slave cores are completely the same.
Furthermore, in the embodiment, the master-slave core code segment is set to be read-only and cannot be rewritten, so that the running safety of the code is ensured. Specifically, the mapping between the master-slave core code settings and the physical addresses and the virtual addresses in the present embodiment is configured by a plurality of registers MAS0, MAS1, MAS2, MAS3, MAS7 in the AMP system:
Continuing to return to fig. 1, the method for controlling a shared code segment of a multi-core system further includes the steps of:
S200, if the running CPU is a main core, reading a main core instruction from a pre-established main core and auxiliary core code segment and executing a control operation corresponding to the main core instruction;
And S300, if the running CPU is a slave core, reading a slave core instruction from the master-slave core code segment and executing a control operation corresponding to the slave core instruction.
in specific implementation, in this embodiment, after determining whether the currently running CPU is the master core or the slave core according to the value of the processor identifier register, the instruction corresponding to the currently running CPU in the master-slave core code segment is further read, and the control operation corresponding to the instruction is executed. For example, if the currently running CPU is judged to be the master core by the value of the processor identification register, reading a master core instruction from the master-slave core code segment and executing a control operation corresponding to the master core instruction; otherwise, reading the slave core instruction from the master-slave core code segment and executing the control operation corresponding to the slave core instruction.
In this embodiment, if the running CPU is a master core, the step of reading a master core instruction from a pre-established master-slave core code segment and executing a control operation corresponding to the master core instruction specifically includes:
S201, if the running CPU is a main core, determining a physical address of a main core code segment and a subordinate core code segment corresponding to a virtual address of the main core code segment and the subordinate core code segment accessed by the main core through a first memory management unit;
S202, reading a main core instruction from a main core code section and a slave core code section corresponding to the physical address of the main core code section and executing a control operation corresponding to the main core instruction.
In specific implementation, if the running CPU is a master core, the master core starts the first memory management unit, the virtual address of the master-slave core code segment sent by the master core is intercepted by the first memory management unit, and the first memory management unit translates the virtual address into a physical address of the corresponding master-slave core code segment and sends the physical address to an external address pin of the master core chip, so as to read a master core instruction in the master-slave core code segment and execute a control operation corresponding to the master core instruction. Certainly, what the main core sends in this embodiment may also be a virtual address of the first data storage unit, the virtual address of the first data storage unit is intercepted by the first memory management unit, and the first memory management unit translates the virtual address into a corresponding physical address of the first data storage unit and sends the physical address to an external address pin of the main core chip, so as to store data or a variable.
In this embodiment, if the running CPU is a master core, the step of reading a master core instruction from the master-slave core code segment and executing the control operation corresponding to the master core instruction specifically includes:
s301, if the running CPU is a slave core, determining a physical address of a master-slave core code segment corresponding to a virtual address of the master-slave core code segment accessed by the slave core through a second memory management unit;
S302, reading a slave core instruction from the master-slave core code section corresponding to the physical address of the master-slave core code section and executing the control operation corresponding to the slave core instruction.
in specific implementation, if the running CPU is a slave core, the slave core starts the second memory management unit, the virtual address of the master and slave core code segments sent by the slave core is intercepted by the second memory management unit, and the second memory management unit translates the virtual address into the physical address of the corresponding master and slave core code segments and sends the physical address to the external address pin of the slave core chip, so as to read the master core instruction in the master and slave core code segments and execute the control operation corresponding to the slave core instruction. Certainly, what the master core sends in this embodiment may also be a virtual address of the second data storage unit, the virtual address of the second data storage unit is intercepted by the second memory management unit, and the second memory management unit translates the virtual address into a corresponding physical address of the second data storage unit and sends the corresponding physical address of the second data storage unit to the external address pin of the slave core chip, so as to store data or variables and the like.
based on the above embodiment, the present invention further provides an intelligent terminal, and a schematic block diagram thereof may be as shown in fig. 2. The intelligent terminal comprises a processor, a memory, a network interface, a display screen and a temperature sensor which are connected through a system bus. Wherein, the processor of the intelligent terminal is used for providing calculation and control capability. The memory of the intelligent terminal comprises a nonvolatile storage medium and an internal memory. The non-volatile storage medium stores an operating system and a computer program. The internal memory provides an environment for the operation of an operating system and computer programs in the non-volatile storage medium. The network interface of the intelligent terminal is used for being connected and communicated with an external terminal through a network. The computer program is executed by a processor to implement a control method of a common code segment of a multi-core system. The display screen of the intelligent terminal can be a liquid crystal display screen or an electronic ink display screen, and the temperature sensor of the intelligent terminal is arranged inside the intelligent terminal in advance and used for detecting the current operating temperature of internal equipment.
it will be understood by those skilled in the art that the block diagram of fig. 2 is only a block diagram of a part of the structure related to the solution of the present invention, and does not constitute a limitation to the intelligent terminal to which the system of the present invention is applied, and a specific intelligent terminal may include more or less components than those shown in the figure, or combine some components, or have different arrangements of components.
In one embodiment, an intelligent terminal is provided, which includes a memory and a processor, the memory stores a computer program, and the processor can realize at least the following steps when executing the computer program:
When the CPU runs, judging whether the running CPU is a main core or a slave core;
if the running CPU is a main core, reading a main core instruction from a pre-established main core and auxiliary core code segment and executing a control operation corresponding to the main core instruction;
and if the running CPU is a slave core, reading a slave core instruction from the master-slave core code section and executing the control operation corresponding to the slave core instruction.
In one embodiment, the processor, when executing the computer program, may further implement: a register for determining whether the running CPU is a master core or a slave core is set in advance.
in one embodiment, the processor, when executing the computer program, may further implement: when the CPU runs, judging whether the running CPU is a main core or a slave core according to the value of the register; when the value of the register is 0, judging that the running CPU is a main core; when the value of the register is N, judging that the running CPU is a slave core; wherein N is a number not equal to 0.
in one embodiment, the processor, when executing the computer program, may further implement: starting a first memory management unit, and mapping the physical address of the master-slave core code segment into a master-slave core code segment virtual address which is the same as the physical address of the master-slave core code segment; and starting a second memory management unit, and mapping the physical address of the master-slave core code segment into a master-slave core code segment virtual address which is the same as the physical address of the master-slave core code segment.
in one embodiment, the processor, when executing the computer program, may further implement: if the running CPU is a main core, determining a physical address of a main core code segment and a subordinate core code segment corresponding to a virtual address of the main core code segment and the subordinate core code segment accessed by the main core through a first memory management unit; and reading a main core instruction from the main and slave core code sections corresponding to the physical addresses of the main and slave core code sections and executing the control operation corresponding to the main core instruction.
In one embodiment, the processor, when executing the computer program, may further implement: if the running CPU is the slave core, determining the physical address of the master-slave core code segment corresponding to the virtual address of the master-slave core code segment accessed by the slave core through a second memory management unit; and reading a slave core instruction from the master-slave core code section corresponding to the physical address of the master-slave core code section and executing the control operation corresponding to the slave core instruction.
in one embodiment, the processor, when executing the computer program, may further implement: starting a first memory management unit, and mapping the physical address of the first data storage unit into a first data storage unit virtual address which is the same as the physical address of the first data storage unit; and starting a second memory management unit, and mapping the physical address of the second data storage unit into a virtual address of the second data storage unit which is the same as the virtual address of the first data storage unit.
In one embodiment, the processor, when executing the computer program, may further implement: setting the master and slave core code segments to be read-only.
it will be understood by those skilled in the art that all or part of the processes of the methods of the embodiments described above can be implemented by hardware instructions of a computer program, which can be stored in a non-volatile computer-readable storage medium, and when executed, can include the processes of the embodiments of the methods described above. Any reference to memory, storage, databases, or other media used in embodiments provided herein may include non-volatile and/or volatile memory. Non-volatile memory can include read-only memory (ROM), Programmable ROM (PROM), Electrically Programmable ROM (EPROM), Electrically Erasable Programmable ROM (EEPROM), or flash memory. Volatile memory can include Random Access Memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in a variety of forms such as Static RAM (SRAM), Dynamic RAM (DRAM), Synchronous DRAM (SDRAM), Double Data Rate SDRAM (DDRSDRAM), Enhanced SDRAM (ESDRAM), Synchronous Link DRAM (SLDRAM), Rambus (Rambus) direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM).
In summary, the present invention provides a method for controlling a code segment shared by multiple core systems, an intelligent terminal and a storage medium, where the method includes: when the CPU runs, judging whether the running CPU is a main core or a slave core; if the running CPU is a main core, reading a main core instruction from a pre-established main core and auxiliary core code segment and executing a control operation corresponding to the main core instruction; and if the running CPU is a slave core, reading a slave core instruction from the master-slave core code section and executing the control operation corresponding to the slave core instruction. The invention establishes the master-slave core code section for storing the master core instruction and the slave core instruction in advance, executes corresponding control operation in the master-slave core code section by judging whether the master core runs or the slave core runs when the CPU runs, and the master-slave core and the slave core share one set of codes, thereby the code upgrading and maintenance are simple, the storage space (ROM) of the AMP system is saved, and the code running space (RAM) is saved.
it is to be understood that the system of the present invention is not limited to the above examples, and that modifications and variations may be made by one of ordinary skill in the art in light of the above teachings, and all such modifications and variations are intended to fall within the scope of the appended claims.
Claims (10)
1. The method for controlling the shared code segment of the multi-core system is characterized by comprising the following steps:
when the CPU runs, judging whether the running CPU is a main core or a slave core;
If the running CPU is a main core, reading a main core instruction from a pre-established main core and auxiliary core code segment and executing a control operation corresponding to the main core instruction; the master-slave core code segment stores a master core instruction and a slave core instruction;
And if the running CPU is a slave core, reading a slave core instruction from the master-slave core code section and executing the control operation corresponding to the slave core instruction.
2. the method for controlling a multi-core system shared code segment according to claim 1, wherein the step of determining whether the running CPU is a master core or a slave core when the CPU is running further comprises:
A register for determining whether the running CPU is a master core or a slave core is set in advance.
3. the method for controlling a multi-core system shared code segment according to claim 2, wherein the step of determining whether the running CPU is a master core or a slave core when the CPU is running comprises:
when the CPU runs, judging whether the running CPU is a main core or a slave core according to the value of the register;
When the value of the register is 0, judging that the running CPU is a main core;
When the value of the register is N, judging that the running CPU is a slave core; wherein N is a number not equal to 0.
4. the method of claim 1, wherein the main core comprises: a first memory management unit, the slave core comprising: a second memory management unit;
after the CPU is operated, the step of judging whether the operated CPU is a main core or a slave core further comprises the following steps:
Starting a first memory management unit, and mapping the physical address of the master-slave core code segment into a master-slave core code segment virtual address which is the same as the physical address of the master-slave core code segment;
And starting a second memory management unit, and mapping the physical address of the master-slave core code segment into a master-slave core code segment virtual address which is the same as the physical address of the master-slave core code segment.
5. the method as claimed in claim 4, wherein if the running CPU is a master core, the step of reading a master core instruction from the pre-established master-slave core code segment and executing the control operation corresponding to the master core instruction comprises:
if the running CPU is a main core, determining a physical address of a main core code segment and a subordinate core code segment corresponding to a virtual address of the main core code segment and the subordinate core code segment accessed by the main core through a first memory management unit;
And reading a main core instruction from the main and slave core code sections corresponding to the physical addresses of the main and slave core code sections and executing the control operation corresponding to the main core instruction.
6. the method as claimed in claim 5, wherein if the operating CPU is a slave core, the step of reading a slave core instruction from the master-slave core code segment and executing the control operation corresponding to the slave core instruction comprises:
if the running CPU is the slave core, determining the physical address of the master-slave core code segment corresponding to the virtual address of the master-slave core code segment accessed by the slave core through a second memory management unit;
and reading a slave core instruction from the master-slave core code section corresponding to the physical address of the master-slave core code section and executing the control operation corresponding to the slave core instruction.
7. The method for controlling a shared code segment for a multi-core system according to claim 4, wherein the main core comprises: a first data storage unit, the slave core comprising: a second data storage unit;
after the CPU is operated, the step of judging whether the operated CPU is a main core or a slave core further comprises the following steps:
starting a first memory management unit, and mapping the physical address of the first data storage unit into a first data storage unit virtual address which is the same as the physical address of the first data storage unit;
And starting a second memory management unit, and mapping the physical address of the second data storage unit into a virtual address of the second data storage unit which is the same as the virtual address of the first data storage unit.
8. the method for controlling a shared code segment for a multi-core system according to claim 1, wherein after the CPU is operated, the step of determining whether the operated CPU is a master core or a slave core further comprises:
Setting the master and slave core code segments to be read-only.
9. An intelligent terminal, comprising: a processor, a storage medium communicatively coupled to the processor, the storage medium adapted to store a plurality of instructions; the processor is adapted to call instructions in the storage medium to execute the steps of the control method for implementing the multi-core system common code segment of any of the above claims 1-8.
10. A storage medium having stored thereon a control program of a control method of a multi-core system common code segment, the control program of the control method of the multi-core system common code segment realizing the steps of the control method of the multi-core system common code segment according to any one of claims 1 to 8 when being executed by a processor.
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