CN110568644B - GIP capacitor structure and manufacturing method - Google Patents
GIP capacitor structure and manufacturing method Download PDFInfo
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- CN110568644B CN110568644B CN201910670982.8A CN201910670982A CN110568644B CN 110568644 B CN110568644 B CN 110568644B CN 201910670982 A CN201910670982 A CN 201910670982A CN 110568644 B CN110568644 B CN 110568644B
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- 239000003990 capacitor Substances 0.000 title claims abstract description 63
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 19
- 238000002161 passivation Methods 0.000 claims abstract description 20
- 238000000034 method Methods 0.000 claims abstract description 15
- 230000004888 barrier function Effects 0.000 claims abstract description 14
- 238000003860 storage Methods 0.000 claims abstract description 8
- 239000002243 precursor Substances 0.000 claims description 18
- 238000005530 etching Methods 0.000 claims description 5
- 238000004080 punching Methods 0.000 claims description 3
- 239000010409 thin film Substances 0.000 claims 4
- 239000010410 layer Substances 0.000 description 116
- 230000000903 blocking effect Effects 0.000 description 6
- 230000000694 effects Effects 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 229910021417 amorphous silicon Inorganic materials 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 101100495256 Caenorhabditis elegans mat-3 gene Proteins 0.000 description 1
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 1
- HCHKCACWOHOZIP-UHFFFAOYSA-N Zinc Chemical compound [Zn] HCHKCACWOHOZIP-UHFFFAOYSA-N 0.000 description 1
- 230000002860 competitive effect Effects 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 230000000007 visual effect Effects 0.000 description 1
- 229910052725 zinc Inorganic materials 0.000 description 1
- 239000011701 zinc Substances 0.000 description 1
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/13338—Input devices, e.g. touch panels
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1255—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs integrated with passive devices, e.g. auxiliary capacitors
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- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Engineering & Computer Science (AREA)
- Nonlinear Science (AREA)
- Crystallography & Structural Chemistry (AREA)
- Optics & Photonics (AREA)
- Chemical & Material Sciences (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Mathematical Physics (AREA)
- Computer Hardware Design (AREA)
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- Semiconductor Integrated Circuits (AREA)
Abstract
A GIP capacitor structure comprises a base layer, a grid electrode layer GE, a grid electrode insulating layer GI, a barrier layer ES, an electrode layer SD, a passivation layer PV and a third electrode layer CM which are sequentially arranged, wherein part of the third electrode layer penetrates through the passivation layer PV, the barrier layer ES and the grid electrode insulating layer GI and is connected with the grid electrode layer GE, the electrode layer SD is not in contact with the third electrode layer CM, and the electrode layer SD is not in contact with the third electrode layer CM. The scheme forms a second storage capacitor between the touch electrode CM Layer and the SD electrode with the TIC structure under the condition of being compatible with the original manufacture procedure, original C1 and C2 are connected in parallel, and Cox is equal to C1+ C2. The capacitance value can be improved, or the area of the capacitor can be effectively reduced, and if the design of the original 7T2C GIP circuit is adopted, a narrow frame is realized.
Description
Technical Field
The invention relates to a novel capacitor structure design of a GIP circuit, in particular to a manufacturing method of a GIP capacitor structure.
Background
IGZO is an amorphous oxide containing indium, gallium and zinc, the carrier mobility is 20-30 times of that of amorphous silicon, the charge-discharge rate of a TFT to a pixel electrode can be greatly improved, the response speed of the pixel is improved, the panel refreshing frequency is higher, and the ultrahigh-resolution TFT-LCD can be realized. Meanwhile, the existing amorphous silicon production line can be compatible with the IGZO process only by slightly changing, so that the cost is more competitive than that of low-temperature polycrystalline silicon (LTPS).
And due to the narrow frame, a larger screen occupation ratio can be obtained, and the visual effect is better. The narrow frame design can reduce the thickness and the weight of the machine body, and the machine body is more portable. And the narrowing of the frame can induce changes in the details of other products. As the pursuit of consumers in performance and portability becomes higher, how to narrow the border of the screen is undoubtedly a new focus of discussion.
In-Cell touch panels are formed by directly forming touch lines between front and rear conductive glasses of a panel (Cell) to form an In-Cell. It is characterized in that: better luminousness, thinner, narrow limit design, sensor ITO are located inside the LCD, fall the rear Lens and break and do not influence the touch-control function. The GIP circuit can replace conventional wiring to achieve a narrow frame design. The method is suitable for high resolution and high PPI design. And smaller IC Size can reduce cost because the number of output lines is reduced. The capacitance occupies a larger position in the GIP region. The capacitance value of the capacitor is improved, the area of the capacitor can be reduced, and the frame is further reduced.
Disclosure of Invention
Therefore, it is desirable to provide a new large capacitor structure on a GIP panel, which achieves the technical effects of reducing the area of the panel during use and facilitating the wiring.
In order to achieve the above object, the present invention provides a GIP capacitor structure, which includes a substrate layer, a gate electrode layer GE, a gate insulating layer GI, a barrier layer ES, an electrode layer SD, a passivation layer PV, and a third electrode layer CM sequentially arranged, wherein a portion of the third electrode layer penetrates through the passivation layer PV, the barrier layer ES, and the gate insulating layer GI, and is connected to the gate electrode layer GE, the electrode layer SD is not in contact with the third electrode layer CM, and the electrode layer SD is not in contact with the third electrode layer CM.
A GIP capacitor structure comprises a base layer, a grid electrode layer GE, a grid electrode insulating layer GI, a blocking layer ES, an electrode layer SD, a passivation layer PV, a third electrode layer CM and a common electrode layer BC which are sequentially arranged, wherein one part of the common electrode layer penetrates through the passivation layer PV, the blocking layer ES and the grid electrode insulating layer GI and is connected with the grid electrode layer GE, the other part of the common electrode layer is connected with the third electrode layer CM, the electrode layer SD is not in contact with the third electrode layer CM, and the electrode layer SD is not in contact with the third electrode layer CM.
A manufacturing method of a GIP capacitor structure comprises the steps of preparing a precursor, wherein the precursor comprises a base layer, a grid layer GE, a grid insulating layer GI, a barrier layer ES and an electrode layer SD which are sequentially arranged;
manufacturing a passivation layer PV on the precursor, then punching a hole in the GIP region until the GE grid layer is exposed, and developing an OC hole of the planarization layer OC in the OC manufacturing process; and forming a third electrode in the pattern designed in the CM process GIP area, and forming a second storage capacitor with the SD.
A manufacturing method of a GIP capacitor structure comprises the steps of preparing a precursor, wherein the precursor comprises a base layer, a grid layer GE, a grid insulating layer GI, a barrier layer ES, an electrode layer SD and a passivation layer PV which are sequentially arranged;
fabricating a planarization layer OC on the precursor and then developing OC holes exposing the planarization layer OC; in the OC downthehole, PV layer top forms the CM electrode, and VA digs the hole again and in order to realize the inter-electrode overlap joint, through the shallow hole of VA, BC and CM overlap joint, refabricate the VA layer, the shallow hole of etching VA exposes the CM electrode, and the deep hole of etching VA exposes the GE electrode, makes common electrode layer BC, and the BC layer passes shallow hole and CM overlap joint, BC and GE overlap joint in the VA deep hole.
Different from the prior art, the scheme forms a second storage capacitor between the touch electrode CM Layer and the SD electrode with a TIC structure under the condition of being compatible with the original manufacturing process, the original capacitor C1 is connected in parallel with the capacitor C2, and Cox is equal to C1+ C2. The capacitance value can be improved, or the area of the capacitor can be effectively reduced, and if the design of the original 7T2C GIP circuit is adopted, a narrow frame is realized.
Drawings
FIG. 1 is a 7T2C GIP circuit design according to an embodiment;
FIG. 2 is a schematic diagram of a GIP capacitor structure according to an embodiment;
FIG. 3 is a schematic cross-sectional view of a GIP pixel structure according to an embodiment;
FIG. 4 is a schematic process flow diagram according to an embodiment;
FIG. 5 is a schematic cross-sectional view of a GIP pixel structure according to an embodiment;
FIG. 6 is a schematic process flow diagram according to an embodiment.
Detailed Description
To explain technical contents, structural features, and objects and effects of the technical solutions in detail, the following detailed description is given with reference to the accompanying drawings in conjunction with the embodiments.
The TIC-structured Array substrate has three metal mantel layers, but the conventional design M3 has no trace reserved in the GIP area.
In the present technical proposal, a piece of plastic is etched to form a mat 3, i.e., a CM layer, on a panel designed based on TIC as a third electrode of the GIP, and a second storage capacitor (which may be referred to as a second capacitor, denoted by C2, the same applies hereinafter) is formed between the CM electrode and the SD electrode of the touch electrode having a TIC structure and is connected in parallel with a capacitor C1 (which may be referred to as a first capacitor, the same applies hereinafter) between the GE electrode and the SD electrode, and Cox is equal to C1+ C2. The capacitance can be increased or the area of the capacitor can be effectively reduced, and in some 7T2C GIP circuit designs, as shown in fig. 1, a narrow bezel can be achieved.
In some embodiments, the GIP capacitor structure is shown in fig. 2, where the capacitance C1 between GE and SD is defined by the thickness of the GI + ES film (C1 ═ S/4 π kd, where S is the overlapping area, and d ═ d1+ d2 is the thickness of the insulating layer).
In the scheme, the capacitance Cox is C1+ C2, C2 is the storage capacitance between the third electrode CM and the second electrode SD, C2 is ∈ S/4 pi kd, wherein S is the overlapping area, d is the thickness of the insulating layer PV, and the same capacitance Size can be increased to 2.5 times of the original capacitance Size by taking the conventional GI:2000A, ES1000A and PV2000A as examples. The same capacitance. The Size may be reduced to 1/4. Therefore, in our solution, the structure for fabricating the GIP capacitor can be designed by adding a layer of CM electrode, with a PV layer sandwiched between the CM electrode and the SD, and still designing a GI and ES interlayer between the SD electrode and the gate GE as a medium. The CM electrode may be designed to be connected to the GE electrode.
In the embodiment shown in fig. 3, a GIP capacitor structure is proposed, which includes a base layer, a gate electrode layer GE, a gate insulating layer GI, a blocking layer ES, an electrode layer SD, a passivation layer PV, and a third electrode layer CM sequentially arranged, where a portion of the third electrode layer penetrates through the passivation layer PV, the blocking layer ES, and the gate insulating layer GI and is connected to the gate electrode layer GE, and the electrode layer SD is not in contact with the third electrode layer CM. The process scheme of the structure is shown in fig. 4, the PV pre-process is not changed, and a precursor can be prepared, wherein the precursor comprises a base layer, a gate electrode layer GE, a gate insulating layer GI, a barrier layer ES and an electrode layer SD which are sequentially arranged; manufacturing a passivation layer PV on the precursor, then punching a hole in the GIP region until the GE grid layer is exposed, and developing an OC hole of the planarization layer OC in the OC manufacturing process; a third electrode is patterned in the CM process GIP region to form a capacitor C2 with the SD. In a specific operation example, holes may be punched in the GIP region to GE in the PV process, the pattern design in the GIP region may be directly performed to form the third electrode, the second storage capacitor may be formed with SD, the second storage capacitor may be connected in parallel to GE and the capacitor C1, and then the OC layer may be covered. The PV mask implementation needs to be added. In summary, the technical solution of the present invention achieves the technical effects of designing the second capacitor and increasing the capacitance of the GIP structure.
In other embodiments, as shown in fig. 5, a GIP capacitor structure includes a base layer, a gate electrode layer GE, a gate insulating layer GI, a blocking layer ES, an electrode layer SD, a passivation layer PV, a third electrode layer CM, and a common electrode layer BC sequentially arranged, where a portion of the common electrode layer penetrates through the passivation layer PV, the blocking layer ES, and the gate insulating layer GI and is connected to the gate electrode layer GE, another portion is connected to the third electrode layer CM, and the electrode layer SD is not in contact with the third electrode layer CM. Fig. 6 shows a corresponding manufacturing method, in which an OC front process is the same as an original Array process, and a precursor is prepared in a front stage, and the precursor includes a base layer, a gate electrode layer GE, a gate insulating layer GI, a barrier layer ES, an electrode layer SD, and a passivation layer PV, which are sequentially arranged; a planarization layer OC is formed on the precursor and the OC process develops the OC holes. In the OC hole, form the CM electrode above the PV layer, carry out digging the hole of VA insulating layer in order to realize the inter-electrode overlap joint again, we can see in the picture that the VA layer has appeared one left two through-holes about, and left hole is lighter, exposes the CM layer, and the hole on right side is darker, directly exposes the GE layer. Through the shallow hole of VA layer, BC and CM overlap joint, refabricate the VA layer, the shallow hole of etching VA exposes the CM electrode, etches the VA deep hole, exposes the GE electrode, makes common electrode layer BC, and the BC layer passes shallow hole and CM overlap joint, BC and GE overlap joint in the VA deep hole to realize that CM and GE are connected, electric capacity C1 and electric capacity C2 are parallelly connected. This solution does not require the addition of a mask. Meanwhile, the technical effect of increasing the capacitance is achieved.
It should be noted that, although the above embodiments have been described herein, the invention is not limited thereto. Therefore, based on the innovative concepts of the present invention, the technical solutions of the present invention can be directly or indirectly applied to other related technical fields by making changes and modifications to the embodiments described herein, or by using equivalent structures or equivalent processes performed in the content of the present specification and the attached drawings, which are included in the scope of the present invention.
Claims (4)
1. A GIP capacitor structure is characterized by comprising a base layer, a grid electrode layer GE, a grid electrode insulating layer GI, a barrier layer ES, an electrode layer SD, a passivation layer PV and a third electrode layer CM which are sequentially arranged, wherein part of the third electrode layer penetrates through the passivation layer PV, the barrier layer ES and the grid electrode insulating layer GI and is connected with the grid electrode layer GE, the electrode layer SD is not in contact with the third electrode layer CM,
the gate electrode layer GE and the electrode layer SD form a first capacitor, the electrode layer SD and the third electrode layer form a second capacitor, the first capacitor and the second capacitor are applied to the GIP circuit,
the GIP circuit includes a thin film transistor: the driving end of the circuit is connected with the enabling end of T2, the source end of T3, the enabling end of T4 and one end of a second capacitor, the source end of T4 is connected with the source end of T5, the source end of T6 and the other end of the second capacitor, the source end of T2 is connected with the enabling end of T3, the enabling end of T6 and one end of C1, and the drain end of T2, the drain end of T3, the drain end of T5 and the drain end of T6 are connected with an on-chip low-voltage VGL.
2. A GIP capacitor structure is characterized by comprising a base layer, a grid electrode layer GE, a grid electrode insulating layer GI, a barrier layer ES, an electrode layer SD, a passivation layer PV, a third electrode layer CM and a common electrode layer BC which are sequentially arranged, wherein one part of the common electrode layer penetrates through the passivation layer PV, the barrier layer ES and the grid electrode insulating layer GI and is connected with the grid electrode layer GE, the other part of the common electrode layer is connected with the third electrode layer CM, the electrode layer SD is not in contact with the third electrode layer CM,
the gate electrode layer GE and the electrode layer SD form a first capacitor, the electrode layer SD and the third electrode layer form a second capacitor, the first capacitor and the second capacitor are applied to the GIP circuit,
the GIP circuit includes a thin film transistor: the driving end of the circuit is connected with the enabling end of T2, the source end of T3, the enabling end of T4 and one end of a second capacitor, the source end of T4 is connected with the source end of T5, the source end of T6 and the other end of the second capacitor, the source end of T2 is connected with the enabling end of T3, the enabling end of T6 and one end of C1, and the drain end of T2, the drain end of T3, the drain end of T5 and the drain end of T6 are connected with an on-chip low-voltage VGL.
3. A manufacturing method of a GIP capacitor structure is characterized in that a precursor is prepared, and the precursor comprises a base layer, a grid electrode layer GE, a grid electrode insulating layer GI, a barrier layer ES and an electrode layer SD which are sequentially arranged;
manufacturing a passivation layer PV on the precursor, then punching a hole in the GIP region until the GE grid layer is exposed, and developing an OC hole of the planarization layer OC in the OC manufacturing process; forming a third electrode on the pattern designed in the GIP region of the CM process, forming a second storage capacitor with the SD,
the gate electrode layer GE and the electrode layer SD form a first capacitor, the electrode layer SD and the third electrode layer form a second capacitor, the first capacitor and the second capacitor are applied to the GIP circuit,
the GIP circuit includes a thin film transistor: the driving end of the circuit is connected with the enabling end of T2, the source end of T3, the enabling end of T4 and one end of a second capacitor, the source end of T4 is connected with the source end of T5, the source end of T6 and the other end of the second capacitor, the source end of T2 is connected with the enabling end of T3, the enabling end of T6 and one end of C1, and the drain end of T2, the drain end of T3, the drain end of T5 and the drain end of T6 are connected with an on-chip low-voltage VGL.
4. A manufacturing method of a GIP capacitor structure is characterized in that a precursor is prepared, wherein the precursor comprises a base layer, a grid electrode layer GE, a grid electrode insulating layer GI, a barrier layer ES, an electrode layer SD and a passivation layer PV which are sequentially arranged;
fabricating a planarization layer OC on the precursor and then developing OC holes exposing the planarization layer OC; forming a CM electrode above a PV layer in an OC hole, digging a VA hole to realize the lap joint between electrodes, lapping the BC and the CM through a VA shallow hole, then manufacturing the VA layer, etching the VA shallow hole to expose the CM electrode, etching the VA deep hole to expose the GE electrode, manufacturing a common electrode layer BC, enabling the BC layer to pass through the shallow hole to lap joint with the CM, lapping the BC and the GE in the VA deep hole,
the gate electrode layer GE and the electrode layer SD form a first capacitor, the electrode layer SD and the third electrode layer form a second capacitor, the first capacitor and the second capacitor are applied to the GIP circuit,
the GIP circuit includes a thin film transistor: the driving end of the circuit is connected with the enabling end of T2, the source end of T3, the enabling end of T4 and one end of a second capacitor, the source end of T4 is connected with the source end of T5, the source end of T6 and the other end of the second capacitor, the source end of T2 is connected with the enabling end of T3, the enabling end of T6 and one end of C1, and the drain end of T2, the drain end of T3, the drain end of T5 and the drain end of T6 are connected with an on-chip low-voltage VGL.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102650783A (en) * | 2011-12-29 | 2012-08-29 | 京东方科技集团股份有限公司 | Display device, TFT-LCD (Thin Film Transistor-Liquid Crystal Display) pixel structure and manufacturing method of TFT-LCD pixel structure |
| CN103854568A (en) * | 2012-11-30 | 2014-06-11 | 乐金显示有限公司 | Flat display panel having narrow bezel |
| CN104681565A (en) * | 2013-11-29 | 2015-06-03 | 乐金显示有限公司 | Array Substrate And Method Of Fabricating The Same |
| CN204679740U (en) * | 2015-05-22 | 2015-09-30 | 信利（惠州）智能显示有限公司 | A kind of capacitance structure for Thin Film Transistor-LCD |
| CN106257677A (en) * | 2015-06-19 | 2016-12-28 | 乐金显示有限公司 | Thin film transistor base plate and the display device of this thin film transistor base plate of use |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR101980766B1 (en) * | 2012-12-27 | 2019-05-21 | 엘지디스플레이 주식회사 | Organic light emitting diode display device including touch panel |
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Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102650783A (en) * | 2011-12-29 | 2012-08-29 | 京东方科技集团股份有限公司 | Display device, TFT-LCD (Thin Film Transistor-Liquid Crystal Display) pixel structure and manufacturing method of TFT-LCD pixel structure |
| CN103854568A (en) * | 2012-11-30 | 2014-06-11 | 乐金显示有限公司 | Flat display panel having narrow bezel |
| CN104681565A (en) * | 2013-11-29 | 2015-06-03 | 乐金显示有限公司 | Array Substrate And Method Of Fabricating The Same |
| CN204679740U (en) * | 2015-05-22 | 2015-09-30 | 信利（惠州）智能显示有限公司 | A kind of capacitance structure for Thin Film Transistor-LCD |
| CN106257677A (en) * | 2015-06-19 | 2016-12-28 | 乐金显示有限公司 | Thin film transistor base plate and the display device of this thin film transistor base plate of use |
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