CN110556289B - Preparation method of semiconductor element with super junction structure and semiconductor element - Google Patents
Preparation method of semiconductor element with super junction structure and semiconductor element Download PDFInfo
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- CN110556289B CN110556289B CN201810559080.2A CN201810559080A CN110556289B CN 110556289 B CN110556289 B CN 110556289B CN 201810559080 A CN201810559080 A CN 201810559080A CN 110556289 B CN110556289 B CN 110556289B
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 41
- 238000002360 preparation method Methods 0.000 title description 6
- 230000007935 neutral effect Effects 0.000 claims abstract description 49
- 239000000758 substrate Substances 0.000 claims abstract description 23
- 238000000034 method Methods 0.000 claims abstract description 19
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 17
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 17
- 239000010703 silicon Substances 0.000 claims abstract description 17
- 229920002120 photoresistant polymer Polymers 0.000 claims description 22
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 claims description 12
- 150000002500 ions Chemical class 0.000 claims description 10
- 238000004519 manufacturing process Methods 0.000 claims description 8
- 239000011261 inert gas Substances 0.000 claims description 7
- 229910052786 argon Inorganic materials 0.000 claims description 6
- 229910052796 boron Inorganic materials 0.000 claims description 6
- 238000002513 implantation Methods 0.000 claims description 6
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 4
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 claims description 4
- 229910052733 gallium Inorganic materials 0.000 claims description 4
- 239000000969 carrier Substances 0.000 abstract 1
- 238000005468 ion implantation Methods 0.000 description 20
- 239000002019 doping agent Substances 0.000 description 9
- 239000000463 material Substances 0.000 description 7
- 239000012535 impurity Substances 0.000 description 6
- 230000015556 catabolic process Effects 0.000 description 4
- 239000007943 implant Substances 0.000 description 3
- 229910052754 neon Inorganic materials 0.000 description 3
- GKAOGPIIYCISHV-UHFFFAOYSA-N neon atom Chemical compound [Ne] GKAOGPIIYCISHV-UHFFFAOYSA-N 0.000 description 3
- 238000000137 annealing Methods 0.000 description 2
- 210000000746 body region Anatomy 0.000 description 2
- -1 boron ions Chemical class 0.000 description 2
- 238000006731 degradation reaction Methods 0.000 description 2
- 239000012530 fluid Substances 0.000 description 2
- 230000007547 defect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000004744 fabric Substances 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000007261 regionalization Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Thyristors (AREA)
Abstract
A semiconductor device with a super junction structure and a method for fabricating the same, the semiconductor device comprising: a silicon substrate and a first conductive epitaxial layer thereon; a plurality of second conductive pillars formed on the upper surface of the first conductive epitaxial layer; wherein the plurality of second conductivity type pillars have a neutral element implanted in an appropriate amount. When the semiconductor element is at the preset operation temperature, the releasing amount of the carrier of the neutral element at the preset operation temperature can just offset or partially offset the number of the other carriers additionally released by the epitaxial layer where the second conductive type doping is positioned because of the temperature rise, and the surge voltage resistance of the super junction semiconductor element is prevented from being reduced.
Description
Technical Field
The present invention relates to a semiconductor structure and a method for fabricating the same, and more particularly, to a semiconductor device having a super junction structure and a method for fabricating the same.
Background
Since the concept of super junction (super junction) was proposed in 1991 by Chen assist in, for example, see U.S. Pat. No. 5,216,275, there have been many attempts to develop and enhance the super junction effect of the above-mentioned invention.
For example, U.S. Pat. No. 6,608,350 proposes a trench-type super junction device, referring to fig. 6, for illustrating the concept of the trench-type super junction device, the trench-type super junction MOS device mainly includes a substrate 81, an N-type epitaxial layer 82, a plurality of parallel trenches 83, a P-type layer 84 on the sidewalls of the parallel trenches 83, a P-type substrate (base)93 on the N-type epitaxial layer 82, a gate oxide layer 87 and a gate 88 between the two parallel trenches 83 and on the N-type epitaxial layer 82, a source region 89 and a source electrode 91 on the P-type substrate 93, and a dielectric (not shown) in the P-type layer 84. In the on mode, a bias voltage is applied to the gate 88 and the source electrode 89 is grounded. A channel is formed between the P-substrate 93 and the gate oxide 87, and a small bias is applied to the channel to generate current in the device, and the P-layer 84 in the trench 83 provides a low on-resistance RDSON. In conventional MOS devices, to reduce the on-resistance RDSON, the resistivity of N-type epitaxial layer 82 must be reduced, i.e., the doping concentration must be increased. However, if the doping concentration of the N-type epitaxial layer 82 is increased, the voltage endurance of the MOS device is affected. By means of the super junction structure, the high voltage endurance and low on-resistance can be achieved.
Referring to fig. 1, a graph of breakdown voltage versus impurity concentration of the power semiconductor is shown, wherein the vertical axis BVDss is reverse voltage (reverse bias voltage) and the horizontal axis is the change of carrier concentration balance. At room temperature, the conventional semiconductor device with a super junction structure (such as the structure shown in fig. 6) generally has an operating point P1. As the device temperature increases, holes in the P-type layer 84 are released more slowly and less because the N-epitaxial layer releases more electrons, which causes the operating point P1 to shift leftward (e.g., to P2), resulting in a poor surge voltage (surge) withstanding capability of the super junction semiconductor device.
Disclosure of Invention
In order to overcome the problems of the prior art, an object of the present invention is to provide a semiconductor device having a super junction structure and a method for fabricating the same, which can prevent the degradation of surge voltage (surge voltage) resistance of the super junction semiconductor device at high operating temperature.
In order to achieve the above object, the present invention provides a method for manufacturing a semiconductor device having a super junction structure, comprising: (a) providing a silicon substrate; (b) forming a first conductive type epitaxial layer on the silicon substrate; (c) manufacturing a mask layer on the first conductive epitaxial layer; (d) implanting a second conductive type ion and a neutral element into the first conductive type epitaxial layer uncovered by the mask layer; (e) removing the mask layer; (f) repeating the steps (b) to (e) to form a plurality of first conductive type epitaxial layers, wherein the first conductive type epitaxial layers have second conductive type ions and neutral elements.
In order to achieve the above object, the present invention provides a semiconductor device having a super junction structure, comprising: a silicon substrate; a first conductive type epitaxial layer on the silicon substrate; a plurality of second conductive pillars formed on the upper surface of the first conductive epitaxial layer; wherein the plurality of second conductivity type pillars have an implanted neutral element.
The semiconductor device is a super junction MOSFET, a super junction MESFET, a super junction Schottky transistor, a super junction IGBT, a gate fluid (thyristor), or a super junction diode.
By implanting an appropriate amount of neutral element into the second conductive type pillar, when the semiconductor device is at a predetermined operating temperature, the amount of electrons (or holes) released by the neutral element N at the predetermined operating temperature can just offset or partially offset the number of extra holes (or electrons) released by the epitaxial region where the second conductive type doping is located due to temperature rise, thereby preventing the surge voltage (surge voltage) resistance of the super junction semiconductor device from being deteriorated.
Drawings
Fig. 1 is a graph showing a relationship between a breakdown voltage and an impurity concentration of a power semiconductor.
FIGS. 2-4 illustrate a method for fabricating a semiconductor device having a super junction structure according to an embodiment of the present invention.
FIG. 5 is a diagram of a semiconductor device with a super junction structure according to the present invention.
FIG. 6 is a side view of a prior art trench-type superjunction device.
Description of the main elements
[ conventional ]
Substrate 81N type epitaxial layer 82
Parallel trench 83P-type layer 84
Gate 88 source region 89
Source electrode 91
[ invention ]
High doping concentration N-type silicon substrate 100
Low doping concentration N-type epitaxial layer 110
Photoresist pattern PR
N-type epitaxial layer 112
20-N of material layers 20-1, 20-2, 20-3
P-shaped column 20
P-type body region 38
N + doped region 34
Gate oxide layer 36
Detailed Description
Referring to fig. 2-4, a method for fabricating a semiconductor device having a super junction structure according to an embodiment of the invention is shown. Referring to fig. 2, a substrate 100, such as a high-doping concentration N-type silicon substrate (N + silicon substrate), is provided, and a low-doping concentration N-type epitaxial layer 110 (N-epitaxial layer) is provided on the substrate 100. In the present invention, the conductivity of the substrate is defined as the first conductivity type doping, which for the above-described embodiment is an N-type doping; the second conductive type doping is P type doping. However, it is to be understood that the first conductive type dopant can also be a P-type dopant; under this condition, the second conductive type doping is N type doping.
After preparing the structure including the high-dopant-concentration N-type silicon substrate 100 and the low-dopant-concentration N-type epitaxial layer 110, a mask layer corresponding to the super junction structure (e.g., corresponding to the P-type layer 84 shown in fig. 6) may be formed on the structure. According to one implementation of the present invention, the mask layer is, for example, the photoresist pattern PR shown in fig. 2, but it is understood that other material layers capable of masking the implanted ions in the ion implantation process can be used as the mask layer of the present invention. The photoresist pattern PR is formed on the outer side of the super junction structure by using a photoresist and an etching cloth shape preparation method. The photoresist pattern PR is formed by covering, exposing and developing the photoresist pattern to transfer the pattern corresponding to the photomask to the N-type epitaxial layer 110 with low doping concentration.
After the photoresist pattern PR is formed, the photoresist pattern PR may be used as a mask to perform ion implantation (ion implantation) on the portion not covered by the photoresist pattern PR, and since the ion implantation is performed on the portion of the low-doping-concentration N-type epitaxial layer 110 not covered by the photoresist pattern PR (i.e., the portion of the low-doping-concentration N-type epitaxial layer 110 exposed), low-energy ion implantation may be used. In addition, for the implant for ion implantation of the present invention, the implant cannot pass through the mask of the photoresist pattern PR, so that the ion implantation region is not formed on the portion of the N-type epitaxial layer 110 with low doping concentration covered by the photoresist pattern PR.
In the ion implantation step, besides the P-type doping (for example, boron or gallium, and other trivalent elements), a neutral element (neutral element) is implanted. According to one embodiment of the present invention, the neutral element may be an inert gas element such as argon (Ar) or neon (Ne). The neutral element hardly releases electrons or holes at normal temperature (e.g., room temperature), and when the operating temperature of the semiconductor device is increased or UIS test is performed to conduct backward avalanche current, more holes can be released by increasing the number of collisions between boron ions and neutral molecules to counteract the electron release problem of the N-type epitaxial layer in the P-type doped region (e.g., the structure shown in FIG. 6) caused by the increased operating temperature at P1 shown in FIG. 1. As the device temperature increases, electrons in the P-type layer 84 are released due to the faster release rate of electrons in the N-epitaxial layer, causing the operating point to shift to the left (toward P2), which deteriorates the surge voltage (surge) endurance of the super junction semiconductor device, if a proper amount of neutral molecules are implanted, more holes are released due to the increased number of collisions between boron ions and neutral molecules, so as to counteract the electrons released from the N-epitaxial region where the P-type dopant is located due to the increased operating temperature, and thus the operating point only moves slightly between the range of P3 and P4.
As shown in fig. 2, in the ion implantation region, P-type doping is represented by symbol H, and neutral elements are represented by symbol N. According to one embodiment, the concentration of neutral element N during this (first) implantation may be proportional to the volume of the trench (e.g., parallel trench 83 of FIG. 6) of the super junction structure and the doping concentration of N-type impurity in N-type epitaxial layer 110 with low doping concentration, so as to offset or partially offset the number of electrons additionally released from N-type epitaxial layer 110 with P-type doping due to temperature increase during operation temperature increase. In addition, although the above description has been made with reference to P-type impurities and inert gas elements, according to the spirit of the present invention, if the semiconductor device having the super junction structure is a P-type substrate and has an N-type pillar doped N-type, the neutral elements may be materials that remain neutral at room temperature and release holes when the temperature is increased.
Referring to fig. 3, an optional annealing step may be performed after the first ion implantation to eliminate lattice defects caused by the first ion implantation. In addition, after the photoresist pattern PR is removed, an epitaxial preparation method is performed on the obtained structure to cover the obtained structure with an epitaxial silicon layer 112. The epitaxial silicon layer 112 is, for example, similar to the low-dopant-concentration N-type epitaxial layer 110 on the lower side thereof, and is also a low-dopant-concentration N-type epitaxial layer. After the epitaxial silicon layer 112 is covered, a photoresist pattern similar to the photoresist pattern PR shown in fig. 2 may be formed by using a photoresist and a pattern formation method, and then a second ion implantation may be performed on the resulting structure using the photoresist pattern as a mask. Similarly, in the ion implantation step, besides the P-type dopant H (e.g., boron, gallium, and other trivalent elements), a neutral element N may be implanted, and the neutral element N may be argon (Ar) or neon (Ne), for example. In one embodiment, the concentration of neutral element N during the second implantation may be proportional to the volume of the trench (e.g., parallel trench 83 in FIG. 6) of the super junction structure and the doping concentration of N-type impurity in N-type epitaxial layer 110 with low doping concentration, so that the hole release amount of neutral element N at the predetermined operating temperature may just cancel or partially cancel the number of electrons additionally released by N-type epitaxial layer 110 with P-type doping due to temperature rise when the operating temperature rises.
According to another embodiment of the present invention, the first ion implantation preparation method may be performed without implanting the neutral element N; that is, only the ion-implantation P type dopant H is implanted into a portion corresponding to the portion not covered by the photoresist pattern PR to form a portion like the P type layer 84 shown in fig. 6. Then, during the second ion implantation, besides the P-type doping, a neutral element N is implanted at the same time, and the implantation amount of the neutral element N is such that when the semiconductor device is at the predetermined operating temperature, the hole release amount of the neutral element N at the predetermined operating temperature can exactly offset the number of electrons additionally released by the N-type epitaxial layer 110 where the first and second P-type doping are located due to the temperature rise. In other words, the present invention does not necessarily require implanting the neutral element N in addition to the P-type dopant H during each ion implantation, but rather, compared to the conventional fabrication method in which only the P-type dopant H is implanted, the neutral element N (e.g., argon) is also implanted in at least some of the ion implantation fabrication methods, so that the amount of holes released from the neutral element N at the predetermined operating temperature can exactly offset the number of electrons additionally released from the N-type epitaxial layer 110 in which the P-type dopant is located due to the temperature increase when the semiconductor device is at the predetermined operating temperature.
As shown in fig. 4, the manufacturing method shown in fig. 2-3 is repeated, i.e., the photoresist pattern PR is removed, an epitaxial silicon layer 112 (e.g., a low doping concentration N-type epitaxial layer) is covered on the resulting structure, the photoresist pattern PR is made to define the next ion implantation applying region (i.e., the region not covered by the photoresist pattern PR), and ion implantation is performed to implant at least P-type doping H (or P-type doping H and neutral element H). After repeating the fabrication process several times and appropriate annealing steps, the P-type pillar region 20 shown in fig. 4 can be obtained. The P-type pillar region 20 includes a plurality of material layers 20-1, 20-2, 20-3. Each of the material layers 20-1, 20-2, 20-3.. 20-N is doped with an ion implanted P-type dopant H. Furthermore, at least one of the material layers 20-1, 20-2, 20-3.. 20-N has a neutral element N (e.g., an inert gas such as argon or neon) such that the increased hole release amount of the neutral element N at the high temperature of the predetermined operation of the semiconductor device at the predetermined operation temperature can exactly offset the number of electrons additionally released by the P-doped N-type epitaxial layer 110 due to the temperature rise. In addition, according to one embodiment of the present invention, a neutral element N may be implanted into each of the material layers 20-1, 20-2, 20-3.. 20-N by implantation; similarly, the hole release amount of the neutral element N at the predetermined operating temperature can just offset the number of electrons additionally released by the P-doped N-type epitaxial layer 110 due to the temperature rise.
As shown in fig. 5, after the P-type pillar 20 is fabricated, the P-type body region 38, the N + doped region 34, the gate electrode 30, the gate oxide layer 36, the gate insulating layer 32 and the source electrode 40 may be formed by other fabrication methods, thereby completing the semiconductor device 10 with the super junction structure of the present invention. Since the preparation method is similar to the prior art, it is not described herein. The semiconductor device with super junction structure comprises super junction MOSFET, super junction MESFET, super junction Schottky transistor, super junction IGBT, gate fluid (thyristor), and super junction diode.
Referring again to fig. 1, in the semiconductor device with the super junction structure of the present invention, at least one P-type pillar 20 has a neutral element N implanted therein. The concentration of neutral element N is proportional to the volume of P-type column 20 and also proportional to the N-type impurity doping concentration of N-type epitaxial layer 110. The hole release amount of the neutral element N at the predetermined operating temperature can exactly offset (or partially offset) the number of electrons additionally released by the P-type doped N-type epitaxial layer 110 due to the temperature rise. Therefore, the operating point of the semiconductor device with the super junction structure of the present invention can be maintained at P1 when the operating temperature rises; instead, in the absence of the neutral element N, as the device temperature increases, the N-type epitaxial layer 110 releases electrons, so that the operating point shifts to the right to P2, resulting in the degradation of the device surge voltage (surge) resistance.
The present invention is capable of other embodiments, and various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (11)
1. A method for fabricating a semiconductor device having a super junction structure, comprising:
(a) providing a silicon substrate;
(b) forming a first conductive type epitaxial layer on the silicon substrate;
(c) manufacturing a mask layer on the first conductive epitaxial layer;
(d) implanting a second conductive type ion and/or a neutral element into the first conductive type epitaxial layer not covered by the mask layer;
(e) removing the mask layer;
(f) repeating the steps (b) to (e) to form a plurality of first conductive type epitaxial layers, wherein the first conductive type epitaxial layers have second conductive type ions and neutral elements or only have the second conductive type ions;
wherein, when the implantation times in the step (d) are multiple, the neutral element is implanted only in part of the implantation times;
the hole release amount of the neutral element at a preset operation temperature just completely offsets the number of electrons additionally released by the ions of the second conduction type doped in the P type in the epitaxial layer of the first conduction type doped in the N type due to the temperature rise.
2. The method as claimed in claim 1, wherein the mask layer is a photoresist layer.
3. The method according to claim 1, wherein the second conductivity type ions are boron or gallium.
4. The method according to claim 1, wherein the neutral element is inert gas.
5. The method according to claim 4, wherein the inert gas is argon.
6. The method according to claim 1, wherein a concentration of the neutral element is proportional to a doping concentration of the first conductive type epitaxial layer.
7. A semiconductor device having a super junction structure, comprising:
a silicon substrate;
a first conductive type epitaxial layer on the silicon substrate;
a plurality of second conductive pillars formed on the upper surface of the first conductive epitaxial layer;
wherein the plurality of second conductivity type pillars have an implanted neutral element;
wherein, only part of the second conductive columns are implanted with the neutral elements;
the hole release amount of the neutral element at a preset operation temperature just completely offsets the number of electrons additionally released by the P-doped second conductive type column at the N-doped first conductive type epitaxial layer due to temperature rise.
8. The semiconductor device of claim 7, wherein the second conductivity type ions are boron or gallium.
9. The semiconductor device with a super-junction structure as claimed in claim 7, wherein the neutral element is an inert gas.
10. The semiconductor device with a super-junction structure as claimed in claim 9, wherein the inert gas is argon.
11. The semiconductor device of claim 7 wherein the concentration of the neutral element is proportional to the doping concentration of the epitaxial layer of the first conductivity type.
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| CN106229339A (en) * | 2016-08-26 | 2016-12-14 | 上海长园维安微电子有限公司 | The terminal structure of a kind of superjunction MOS and manufacture method thereof |
| CN107768422A (en) * | 2016-08-23 | 2018-03-06 | 富士电机株式会社 | The manufacture method of semiconductor device and semiconductor device |
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| TWI450327B (en) * | 2011-12-27 | 2014-08-21 | Anpec Electronics Corp | Method for fabricating power semiconductor device |
| CN103474465B (en) * | 2013-09-06 | 2016-06-08 | 无锡新洁能股份有限公司 | A kind of super-junction MOSFET device and manufacture method thereof |
| DE102015116576B4 (en) * | 2015-09-30 | 2021-11-25 | Infineon Technologies Austria Ag | Superjunction semiconductor device having oppositely doped semiconductor regions formed in trenches, and method of manufacture |
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| CN107768422A (en) * | 2016-08-23 | 2018-03-06 | 富士电机株式会社 | The manufacture method of semiconductor device and semiconductor device |
| CN106229339A (en) * | 2016-08-26 | 2016-12-14 | 上海长园维安微电子有限公司 | The terminal structure of a kind of superjunction MOS and manufacture method thereof |
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